ECE448 Lecture15 ASIC Design
ECE448 Lecture15 ASIC Design
Lecture 15
ASICs vs. FPGAs
FPGAs
Off-the-shelf
Low development costs
Low power
Short time to the market
Low cost (but only
in high volumes)
Reconfigurability
Local
Memory
19.68 mm
19.80 mm
51x
2.7 mm
2.82 mm
10
Reference
Implementation
C, C++
stdcell lib
Logic Synthesis
Layout
VCS
Hercules
Calibre
die area
pin count
LVS
Mentor Calibre
Synopsys StarRCXT
Parasitic Extraction
latency
throughput
(post-synthesis)
Simulation
Synopsys IC Compiler
Cadence Encounter
process lib
Design
Quality
test vectors
VCD
Simulation
PrimeTime
latency
throughp
ut
(post
P&R)
power diss
11
Synthesis
Timing Analysis
Floorplanning
Placement
Clock Tree Synthesis
Routing
Design for Manufacturing
12
31
Cadence
Magma
13
Synthesis
Timing Analysis
Synopsys
Tools
Design Compiler
Primetime
Floorplanning
Placement
Clock Tree Synthesis
Astro
Routing
Design for Manufacturing
ECE 448 FPGA and ASIC Design with VHDL
14
31
IP
15
28
ASICs
FPGAs
Computer
Organization
ECE 431
Digital Circuit Design
ECE 447
Single Chip
Microcomputers
ECE 448
FPGA and ASIC Design with VHDL
ECE 511
ECE 611
Microprocessors
Advanced
Microprocessors
ECE 545
ECE 645
ECE 586
Digital
Integrated
Circuits
ECE 681
VLSI Design
for ASICs