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System Bus in Computer Architecture: Goran Wnis Hama Ali

The system bus connects major computer components like the processor, memory, and input/output devices. It consists of several sub-buses including the data bus, address bus, and control bus. The data bus transfers data, the address bus indicates the memory or device location, and the control bus manages the signals for read, write, and interrupt operations on the shared bus. Arbitration is needed because only one device can use the bus at a time, and policies like priority and waiting time determine which device gains control of the bus for transferring information.

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Goran Wnis
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145 views

System Bus in Computer Architecture: Goran Wnis Hama Ali

The system bus connects major computer components like the processor, memory, and input/output devices. It consists of several sub-buses including the data bus, address bus, and control bus. The data bus transfers data, the address bus indicates the memory or device location, and the control bus manages the signals for read, write, and interrupt operations on the shared bus. Arbitration is needed because only one device can use the bus at a time, and policies like priority and waiting time determine which device gains control of the bus for transferring information.

Uploaded by

Goran Wnis
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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System Bus in

Computer Architecture
GO R A N WN IS H A MA A LI

INTRODUCTION
The CPU sends various data values, instructions and
information to all the devices and components inside the
computer.

If you look at the bottom of a motherboard you'll see a


whole network of lines or electronic pathways that join the
different components together.

This network of wires or electronic pathways is called the


'Bus'.

INTRODUCTION (contd)
Bottom of motherboard

BUS
A bus is a communication pathway connecting two or more
devices.
A key characteristic of a bus is that it is a shared transmission
medium.
Multiple devices connect to the bus, and a signal transmitted
by any one device is available for reception by all other
devices attached to the bus.
If two devices transmit during the same time period, their
signals will overlap and become garbled. Thus, only one device
at a time can successfully transmit.

BUS contd
Typically, a bus consists of multiple communication
pathways, or lines. Each line is capable of transmitting
signals representing binary 1 and binary 0.
several lines of a bus can be used to transmit binary digits
simultaneously (in parallel).
For example, an 8-bit unit of data can be transmitted over
eight bus lines.
Computer systems contain a number of different buses
that provide pathways between components at various
levels of the computer system hierarchy.

SYSTEM BUS
A bus that connects major computer components (processor,
memory, I/O) is called a system bus.
A system bus consists, typically, of from about fifty to hundreds of
separate lines. Each line is assigned a particular meaning or function
System bus usually is separated into three functional groups .
1.

Data Bus

2.

Address Bus

3.

Control Bus

In addition, there may be power distribution lines that supply power


to the attached modules.

SYSTEM BUS MODEL

DATA BUS
A collection of wires through which data is transmitted from
one part of a computer to another.
Data Bus can be thought of as a highway on which data
travels within a computer.
This bus connects all the computer components to the CPU
and main memory.
The data bus may consist of 32, 64, 128, or even more
separate lines.
The number of lines being referred to as the width of the
data bus. Because each line can carry only 1 bit at a time,
the number of lines determines how many bits can be
transferred at a time.

DATA BUS contd


It is a bidirectional bus.
The size (width) of bus determines how much data can be
transmitted at one time.
E.g.
A 16-bit bus can transmit 16 bits (2 bytes)of data at a time.
32-bit bus can transmit 32 bits(4 bytes) at a time.

The size (width) of bus is a critical parameter in determining


system performance.
The wider the data bus, the better, but they are expensive.

ADDRESS BUS
A
collection of wires used to identify particular location in
main memory is called Address Bus.

Or in other words, the information used to describe the


memory locations travels along the address bus.
Clearly, the width of the address bus determines the
maximum possible memory capacity of the system.
N address lines directly address memory locations.

ADDRESS BUS contd


It is an unidirectional bus.
The CPU sends address to a particular memory locations
and I/O ports.

The address bus consists of 16 , 20 , 24 or more parallel


signal lines.

ADDRESS BUS contd


8086: 20 address lines
Could address 1 MB of memory
Pentium: 32 address lines
Could address 4 GB of memory
Itanium: 64 address lines
Could address 264 bytes of memory

CONTROL BUS
Because the data and address lines are shared by all
components, there must be a means of controlling their
use.
The control lines regulates the activity on the bus.
Control signals transmit both command and timing
information among system modules.
The control bus carries signals that report the status of
various devices.

CONTROL BUS
Typical control bus signals are :
Memory Read : causes data from the addressed
location to be placed on the data bus.
Memory Write : causes data on the bus to be written
into the addressed location
I/O write: causes data on the bus to be output to the
addressed I/O port
I/O read: causes data from the addressed I/O port to be
placed on the bus

Example : Memory Read


The following figure shows how the CPU reads the value
12 from the memory location 2453:

Example: Memory Read contd


CPU sends out the address value 2453 on theaddress
bus
Simultaneously, CPU sends out the signalR/W = 1on
thecontrol bus,which indicates aREADoperation
CPU then waits for the data from memory on thedata
bus
TheR/W = 1signal and the address bus value 2453 will
cause the memory to retrieve the value at memory
location 2453 to be sent out on the data bus

Memory Read a Closer look


Address of next instruction is in PC
Address (MAR) is placed on address bus
Control unit issues READ command
Result (data from memory) appears on data bus
Data from data bus copied into MBR
PC incremented by 1 .
Data (instruction) moved from MBR to IR
MBR is now free for further data fetches

Example: Memory Write


The following figure shows how the CPU writes the value
53 from the memory location 2453:

Example: Memory Write contd


CPU sends out the address value 2453 on theaddress
bus
Simultaneously, CPU also sends out the value 53 on
thedata bus
And the signalR/W = 0on thecontrol buswhich
indicating a WRITE operation
TheR/W = 0signal along with the address bus value
2453 and data bus value 53 will cause the memory to
store the value 53 at the location 2453...

Control Bus contd


Control lines also include :
Transfer ACK: indicates that data have been accepted
from or placed on the bus.
Bus request: indicates that a module needs to gain
control of the bus.
Bus grant: indicates that a requesting module has
been granted control of the bus.

Control Bus contd


Interrupt request: indicates that an interrupt is
pending.
Interrupt ACK: acknowledges that the pending
interrupt has been recognized.
Reset: initializes all modules.

Bus Design Issues


Need to consider several design issues :
Bus width
Data and address buses.

Bus type
Dedicated or multiplexed.

Bus operations
Read, write, block transfer, interrupt,

Bus arbitration
Centralized or distributed.

Bus timing
Synchronous or asynchronous

Bus Type
Dedicated buses
Separate buses dedicated to carry data and address information.
Good for performance.
But increases cost.

Multiplexed buses
Data and address information is time multiplexed(defined in the next
slide ) on a shared bus.
Poor Performance
But Reduces cost.

Time Multiplexed Bus


Address and data information may be transmitted over
the same set of lines using an Address Valid control line.
At the beginning of a data transfer, the address is placed
on the bus and the Address Valid line is activated. At this
point, each module has a specified period of time to copy
the address and determine if it is the addressed module.
The address is then removed from the bus, and the same
bus connections are used for the subsequent read or
write data transfer. This method of using the same lines
for multiple purposes is known as time multiplexing. The
advantage of time multiplexing is the use of fewer lines.

Bus Operations
Basic operations
Read and write.

Block transfer operations.


Read or write several contiguous memory locations.
Example: cache line fill.

Interrupt operation.

Bus Arbitration
In all but the simplest systems, more than one module may need
control of the bus.
For example, an I/O module may need to read or write directly to
memory, without sending the data to the processor.
Because only one unit at a time can successfully transmit over
the bus, some method of arbitration is needed.
Bus arbitration can be done either
Statically.
Dynamically.

Static Bus Arbitration


Done in a predetermined way.
For example , we might use round-robin allocation that
rotates the bus among the masters.
Easy to implement.
A master may be given a bus even it does not need it.
This kind of allocation leads to inefficient use of the bus.

Dynamic Bus Arbitration


Bus allocated only in response to a request.
Each master is equipped with;
Bus request line.
Bus grant line.

A master uses the bus request line to let others know that it
needs the bus.
Before a master can use the bus, it must receive permission to
use the bus via the bus grant line.

Dynamic Bus Arbitration contd


Distributed arbitration
Arbitration hardware is distributed among the masters.
A distributed arbitration algorithm is used to determine who
should get the bus.

Bus Allocation Policies


Fixed priority
Each master is assigned a fixed priority.
Highest priority master always gets the bus.
Priorities can be assigned based on the importance of service.

Rotating priority
Priority is not fixed
Several ways of changing priority
Increase the priority as a function of waiting time
Lowest priority for the master that just received the bus

Bus Release Policies


Governs the conditions under which the current master
releases the bus
Two types
Non-preemptive.
Current master voluntarily releases the bus.
Disadvantage
May hold bus for long time.
Preemptive
Forces the current master to release the bus without completing its
bus transaction.

Non-Preemptive Bus Release Policies


Transaction-based release
Releases bus after completing the current transaction.
Requests bus again if it has more transactions.
Easy to implement.
Unnecessary overhead if only one master needs the bus.

Demand-driven release
Avoids unnecessary bus requests of the previous policy.
Releases the bus only if another master requests the bus.
More efficient.

Centralized bus arbitration


Daisy-chaining
Uses a single, shared bus request signal
Central arbiter sends the grant signal to the first master in the
chain
Each master passes the grant signal to its neighbor if it does need the
bus
Grabs the grant signal if it wants the bus

Easy to implement

Centralized bus arbitration contd


Independent requests
Arbiter is connected to each master
Variety of bus allocation policies can be implemented.

Disadvantages
Complex to implement.

PCI uses this implementation technique.

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