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Project Reciew - Final

This document summarizes a project to design a simple/superscalar processor using Bluespec System Verilog (BSV) and verify it using an SoC framework. The project implements a pipeline processor in BSV to optimize concurrency, scheduling, parallelism and hazards. Its performance is compared to a sequential processor. Functionality is verified using a cycle-accurate simulator. Altera timing analysis is used to verify timing and address multi-corner issues. Future work involves extending the design to a superscalar processor and evaluating its performance.

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hariharankalyan
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56 views

Project Reciew - Final

This document summarizes a project to design a simple/superscalar processor using Bluespec System Verilog (BSV) and verify it using an SoC framework. The project implements a pipeline processor in BSV to optimize concurrency, scheduling, parallelism and hazards. Its performance is compared to a sequential processor. Functionality is verified using a cycle-accurate simulator. Altera timing analysis is used to verify timing and address multi-corner issues. Future work involves extending the design to a superscalar processor and evaluating its performance.

Uploaded by

hariharankalyan
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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DEVELOPMENT OF SIMPLE/SUPERSCALAR

PROCESSOR WITH BLUESPEC SYSTEM


VERILOG (BSV) AND VERIFICATION OF THE
SAME WITH SoC FRAMEWORK

Guided By
Dr. Jayanta Biswas

Presented By
N. Siva Kumar
115040011

Whats the need for designing a Synthesizable processor?


Application specific cores for system-on-chip applications
An ASIP is an hardware architectural concept meant to
fill the gap between ASICs (Application Specific
Integrated Circuits) and DSPs (Digital Signal Processors)
Flexibility: designed to support at least minor variations
of the implemented algorithm
System efficiency: it implies computational power, area
and cost
Multicore emulation for architectural design space exploration

Abstract
This project implements a pipeline processor with Bluespec
System Verilog (BSV) using the concepts of concurrency, scheduling,
parallelism and pipeline hazards optimization. The pipeline processor
performance is compared with a sequential processor in terms of cycles
per instruction (CPI) and average execution time for a single instruction.
The functionality of the designed processors is verified with GTK cycle
accurate simulator. Altera design flow is adopted to verify the static
timing analysis and to exploit multi-corner timing issues.

Project Layout
Problem Definition
The major problem of executing
multiple instructions in a scalar
program is the handling of data
dependencies. If data dependencies
are not effectively handled, it is
difficult to achieve an execution
rate of more than one instruction
per clock cycle.

Bluespec
System
Verilog
Sequential
Processor
Pipeline
Processor
Altera Timing
Analysis

Pipeline Architecture

Instruction Format

MB
Ack.

Source2
Register
Or
Read2
Register
6-bit
32 regs

Source1
Register
Or
Read1
Register
6-bit
32 regs

Address Fields

Destination
Register
Or
Write
Register
6-bit
32 regs

Opcode
5-bit
32 inss

Mnemonics & Opcodes


Include arithmetic, logical, load-store, branching and machine control instructions
Commonly utilized instructions in a RISC processor architecture

Data Forwarding - analysis of dependent instructions


Dependent instructions consumes more processing cycles till the availability of data in the
destination address of previous instruction
This degrades the performance of the processor and increases the timing constraints

The saving of ALU result prior to write-back stage helps in forwarding data to the
successive dependent instruction.

TIMING ANALYSIS
Compiled in Altera Quartus II version 9.1 web edition for Stratix-III
platform
Fmax for the sequential processor is obtained at 18 MHz
For pipeline processor the value of Fmax is 168 MHz
This variation is due to resources overlapping in the sequential
design along with data hurdles and timing synchronization issues
4187 LUTs are utilized by the pipeline design

FUTURE SCOPE : SUPERSCALAR PROCESSOR DESIGN


The design is extended to execute multiple instructions in a single cycle using Bluespec
System Verilog
Pipeline also allows several instructions executing in the same cycle, but in different
stages
The designed pipeline processor is reused as a base design for implementing superscalar
architecture and carrying out performance evaluation for superscalar architecture

CONCLUSION
A Sequential processor is designed without pipeline register implementation. The
design is analysed to gain the insight for hurdles and timing issues. The verilog version
of the design program is obtained from Bluespec and static timing analysis is performed
using Altera Quartus II tool. A Pipeline processor is designed using pipeline registers and
analyzed in terms of concurrency, cycles per instruction and hazards optimization.
Detailed analysis is performed with optimization protocols for maximum throughput.
Scheduling analysis is throughly worked out for timing synchronization between the
pipeline stages. Timing analysis is performed using the same Altera tool and is
determained to work at 168 MHz for Stratix-III platform.

PUBLICATION

Hazards Analysis In A Processor Using Bluespec System Verilog


Siva Kumar Nagulapati, Dr. Jayanta Biswas
INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH
(IJAER)
SCOPUS INDEXED JOURNAL
Accepted

References
1. In-System FPGA Prototyping of an Itanium Microarchitecture,
Roland E. Wunderlich and James C. Hoe, IEEE International
Conference on Computer Design (ICCD04).
2. 802.11a Transmitter: A Case Study in Microarchitectural
Exploration, Nirav Dave, Michael Pellauer, Steve Gerding, &
Arvind, 4th IEEE/ACM International Conference on Formal
Methods and Models for Co-Design, 2006.
3. Modular Compilation of Guarded Atomic Actions, Muralidaran
Vijayaraghavan, Nirav Dave, and Arvind, 978-1-4799-09056/13/2013 IEEE
4. A tool to support Bluespec System Verilog coding based on UML
diagrams, Sergio H. M. Durand and Vanderlei Bonato, 978-1-46732421-2/12/2012 IEEE
5. Computer Architecture-A Quantitative Approach. 4E, John L.
Hennessy and David A. Patterson

6. A H.264 Decoder: A Design Style Comparison- Case Study, Hristo


Nikolov, Adarsha Rao, Ed F Deprettere, S. K. Nandy and Ranjani
Narayan, 978-1-4244-5827-1/09/2009 IEEE
7. Composable Guarded Atomic Actions: a Bridging Model for SoC
Design, Rishiyur S. Nikhil, Seventh International Conference on
Application of Concurrency to System Design (ACSD 2007), 07695-2902-X/07 / 2007 IEEE
8. Reliable Design with Multiple Clock Domains, Ed Czeck, Ravi
Nanavati and Joe Stoy, 1-4244-0421-5/06/2005 IEEE
9. Application Specific Processors for Multimedia Applications,
Muhammad Rashid, Ludovic Apvrille and Renaud Pacalet,IEEE
10. Computer Organization and Architecture Designing for Performance
-8E, William Stallings.
11. www.ece.ucsb.edu/its/bluespec
12. http://www.simplescalar.com
13. http://www.altera.com

THANK YOU

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