Z80 CPU Instruction

Description

158 different instruction types

Instruction groups

Load and Exchange

Block Transfer and Search
Arithmetic and Logical
Rotate and Shift
Bit Manipulation (Set, Reset, Test)
Jump, Call, and Return
Input/Output
Basic CPU Control

Addressing
Modes
Immediate
Addressing LD A,5

Immediate Extended
LD HL,7FC6H
Modified Page Zero Addressing RST 8
Relative Addressing
JR label
Jump Relative (2 byte)
One Byte Op Code
8-Bit Twos Complement Displacement (A+2)

Extended Addressing

JP label

Absolute jump
One byte opcode
2 byte address

Indexed Addressing

INC (IX+2)

(Index Register + Displacement) (IX+d)

2 byte opcode
1 byte displacement

Addressing Modes
Register
Addressing
(cont.)

LD C,B
Implied Addressing
Op Code implies other operand(s)
SUB E
; A is implied (A = A - E)
Register Indirect Addressing
16-bit CPU register pair as pointer (such as HL)
ADD A,(HL)
Bit Addressing
set, reset, and test instructions.
SET 3,A

RES 7,B

Z80 Assembly Language

Instruction Format
(Fields)
<-------- instruction ----->

START:
label field

LD A, (VAL1)
opcode or
operand or address field
mnemonic field

LABELS:

Label field (may be blank) is the first field in an assembly language instruction.
Address of the first program byte for that instruction is associated with the
label
You may use the label as data or as an address in another instruction's operand
field.

Machine Code
Instruction Format
MachineCodeInstructionOpcode+Operands
Z80instruction ranges from one byte to four bytes
Opcode varies from 1 to 2 bytes
Operands varies from 1 to 2 bytes
Operands could be memory locations , registers, I/O
addresses , or memory addresses

Z80 instruction Set

Instructionscanbeclassifiedto:
1-Byteinstructions
2-Byteinstructions
3-Byteinstructions
4-Byteinstructions

Z80 instruction Set

1-ByteInstruction
The opcode and operands are included in the
same byte
Ex.
LD A,B load B into A 01 111 000
LD 01 , A 111 , and B 000

For microprocessor internal usage only

7

Z80 instruction Set

2-ByteInstruction
Opcode First Byte
Operand Second Byte
Ex. LD B, 32H 0000 0110 (06H) byte 1
0011 0010 (32H) byte 2
Load the 32 value into register B
LD B is represented by 06H and the second byte
includes 32
8

Z80 instruction Set

3-ByteInstruction
One byte Opcode and two bytes Operand
Ex. LD BC, 2080H
0000 0001 byte 1 LD BC (01H)
1000 0000 byte 2 80H
0010 0000 byte 3 20H
Loads the value 2080H into the two registers B and
C
Note: the load starts by the low order byte followed by
the high order 80 then 20
9

Z80 instruction Set

4-ByteInstructions
2 bytes Opcode and 2 bytes Operand
Ex. LD IX , 2000H Loads the value 2000H into IX register
first 2 bytes are opcode bytes (DDH and 21H)
1101 1101 (DDH) byte 1 (opcode)
0010 0001 (21H) byte 2 (opcode)
0000 0000 (00H) byte 3 (operand low-byte)
0010 0000 (20H) byte 4 (operand high-byte)

10

Z80 instruction Set

InstructionCategories
Data Copy transfer or load operations
Arithmetic Operations
Logic Operations
Bit Manipulation
Branch Operation
Machine Control Operations

11

Z80 instruction Set (LD)

LD (load)

does not affect the flags

LD r,data8 ==> 2 bytes

r: A,B,C,D,E,H,L
Load 8-bit immediate data to the register r.

examples: LD A,2AH
LD L,80H

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

LD r1,r2 ==> 1 byte r1,r2: A,B,C,D,E,H,L examples: LD A,B

Load the contents of register r2 to the register r1.
LD E,D
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

LD A,(address)

==> 3 bytes

Load the contents of the memory location

address to the accumulator . *direct addressing

example: LD A,(084AH)

address memory
084A
4F
A<== 4FH

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

LD A,(rp) ==> 1 byte

rp: BC,DE,HL
Load the contents of the memory location
pointed by the given register pair to the
accumulator. * indirect addressing

example: LD A,(BC)
assume BC contains 084AH
address memory
084A
4F
A<== 4FH

Z80 instruction Set (LD)

LD I,A ==> 2 bytes
LD R,A
Load the contents of the accumulator to the register I or R
LD A,I
Load the contents of the register I to the accumulator.
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

LD HL,(address) ==> 3 bytes

LD rp,(address) ==> 4 bytes
LD IX,(address)
LD IY,(address)
example: LD DE,(49FFH)

rp: BC,DE,HL
Load the contents of the memory location
address to the register pair or index registers.
* 2 bytes of data move from memory to registers

address memory
49FF
B8
==> E
4A00
33
==> D
DE <== 33B8H

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

LD rp,data16 ==> 3 bytes

rp: BC,DE,HL,SP
Load 16-bit immediate data to the register pair or index register.
LD IX,data16 ==> 4 bytes
examples:
LD HL,BE00H
LD IY,data16
LD IY,9F44H

Z80 instruction Set (LD)

LD r,(HL) ==> 1 byte
r: A,B,C,D,E,H,L d:displacement byte [-128,127]
LD r,(IX+d) ==> 3 bytes Load the contents of the memory location (8-bit)
pointed by HL or index registers to the register r.
LD r,(IY+d)
examples:
LD HL,4F00H
address memory
LD B,(HL)
B <== 2AH
4F00H
2A
4F01H
47
LD IX,4F00H
4F02H
3D
LD C,(IX+2)
C <== 3DH
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

LD SP,HL ==> 1 byte

LD SP,IX ==> 2 bytes
LD SP,IY

Load the contents of HL or index registers to the SP.

14

Z80 instruction Set (LD)

LD (address),A

==> 3 bytes

example:
LD A,4FH
A <==
4FH
LD (084AH),A

Load the contents of the accumulator to the

memory location address. *direct addressing
address memory
084A
4F

stored in memory after the

execution of the instructions

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

LD (address),HL
LD (address),rp
LD (address),IX
LD (address),IY

==> 3 bytes
==> 4 bytes

rp: BC,DE,HL
Load the contents of the register pair or index
registers to the memory location address.
* 2 bytes of data move from registers to memory

example:

after the execution of the instructions:

LD BC,3C2AH
LD (084AH),BC

address memory
084AH
2A <== C
084BH
3C
<== B

Z80 instruction Set (LD)

Load 8-bit immediate data to the memory
LD (HL),data8 ==> 2 bytes location (8-bit) pointed by HL or index registers.
LD (IX+d),data8 ==> 4 bytes
after the execution of the instructions:
LD (IY+d),data8
address memory
example: LD IX,4F00H
4F00H
LD (IX+1),3F
4F01H
3F
----------------------------------------------------------------------------------------------------------------------

LD (HL),r ==> 1 byte

LD (IX+d),r ==> 3 bytes
LD (IY+d),r
example: LD C,3FH
LD HL,4F00H
LD (HL),C

r: A,B,C,D,E,H,L d:displacement byte [-128,127]

Load the contents of the register r to the memory
location (8-bit) pointed by HL or index registers.
after the execution of the instructions:

address memory
4F00H 3F
<== C

Z80 instruction Set (LD)

LD (rp),A ==> 1 byte

example:
LD BC,084AH
LD A,3FH
LD (BC),A

rp: BC,DE,HL
Load the contents of the memory location
pointed by the given register pair to the
accumulator.
* indirect addressing
address memory
084A
3F
<== A

Z80 instruction Set (ADC)

ADC (add with carry) S,Z,H,P/V,CY are affected, N=0 (addition
instruction)

ADC A,data8 ==> 2 bytes Add the immediate 8-bit data to the accumulator
with carry bit. A=A+data8+carry
example : LD A,3AH
00111010 B
58 (decimal)
ADC A,7CH 01111100 B 124 (decimal) result = 182 >127
+
0 <== carry
0 10110110 = B6H ==> A (-74 signed decimal)
CY=0
Z=0 (result is nonzero) S=1 (MSB of result)
N=0 (addition)
P/V= carry XOR carry out of 6th bit = 0 XOR 1 = 1 (overflow) : result is wrong!

When signed numbers are manipulated:

if addition of two positive numbers results in a negative number, or
if addition of two negative numbers results in a positive number
==> result is wrong!!!

Z80 instruction Set (ADC)

Thereasonforawrongresult
An 8-bit register can contain a signed number in the range
[-128,127]
If expected result is out of this range
8-bit register will contain a wrong result !
Overflow indicates that the correct result requires:
8 bits for value + 1 bit for the sign = 9 bits total

Z80 instruction Set (ADC)

==> 1 bytes

r: A,B,C,D,E,H,L Add the contents of 8-bit register

r to the accumulator with carry bit. A=A+r+carry

ADC A,(HL)
==> 1 bytes
ADC A,(IX+d) ==> 3 bytes
ADC A,(IX+d)

Add the contents of memory location pointed by HL

or index register to the accumulator with carry bit.
A=A+(HL)+carry

ADC A,r

---------------------------------------------------------------------------------------------------------------------------16-bit addition with carry:

ADC HL,rp ==> 2 bytes

example: ADC HL,BC

rp: BC,DE,HL,SP
HL=HL+rp+carry
Assume that HL=A536H, BC=1044H and carry=1

1010 0101 0011 0110

0001 0000 0100 0100
1 <== carry
+
0 1011 0101 0111 1011

CY=0 (no carry out of 15th bit)

S=1 (MSB of the result)
Z=0 (result is nonzero)
N=0 (no subtraction)
P/V= carry XOR carry out of 14th bit
= 0 XOR
0
=
0
(no overflow) result is correct !

Z80 instruction Set (ADD)

ADD (add without carry)

S,Z,H,P/V,CY are affected,

N=0 (addition instruction)

ADD A,data8 ==> 2 bytes Add the immediate 8-bit data
A=A+data8
ADD A,r
==> 1 bytes
Add the 8-bit register r
A=A+r
ADD A,(HL) ==> 1 bytes
Add the contents of memory (HL) A=A+(HL)
ADD A,(IX+d) ==> 3 bytes
Add the contents of memory (IX+d)
A=A+(IX+d)
ADD A,(IY+d)
(IY+d) A=A+(IY+d)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

16-bit addition without carry: watchout! only CY is affected and N=0

ADD HL,rp ==> 1 bytes
rp: BC,DE,HL,SP
ADD IX,rp ==> 2 bytes
rp: BC,DE,SP
ADD IY,rp
rp: BC,DE,SP
IY=IY+rp
ADD IX,IY and ADD IY,IX are notavailable !
but
ADD IX,IX and ADD IY,IY are available

HL=HL+rp
IX=IX+rp

Z80 instruction Set (AND)

AND (logical AND)

S,Z,P are affected, N=0 , CY=0

AND data8 ==> 2 bytes

Perform logical AND operation between the contents
of accumulator and immediate 8-bit data bit by bit.
A=A.data8
example : LD A,3AH
00111010 B
AND 7CH
01111100 B
&
00111000 B = 38H ==> A
CY=0
(AND operation)
Z=0 (result is nonzero)
S=0 (MSB of
result)
N=0 (AND operation) P = 0 (odd parity; three 1 bits in the result, an odd number)
AND r
==> 1 bytes
AND (HL) ==> 1 bytes
AND (IX+d) ==> 3 bytes
AND (IY+d)
(IY+d)
A=A.r

A=A.(HL)

AND with the 8-bit register r

AND with the contents of memory (HL)
AND with the contents of memory (IX+d)
A=A.(IX+d)

A=A.(IY+d)

Z80 instruction Set (ORXOR)

OR (logical OR)
XOR (logical XOR)

S,Z,P are affected, N=0 , CY=0

S,Z,P are affected, N=0 , CY=0

Perform logical OR/XOR operation between the contents of accumulator and

operand specified in the instruction. Same groups of instructions as AND
instruction are available.
OR data8
OR r
OR (HL)
OR (IX+d)
OR (IY+d)
XOR data8
XOR r
XOR (HL)
XOR (IX+d)
XOR (IY+d)

Z80 instruction Set (BIT)

BITb (test bit b)

flag Z only is affected, N=0

BIT b,r ==> 2 bytes

b: 0,1,2,....,7
MSB==> 7 6 5 4 3 2 1 0 <==LSB
r:A,B,C,D,E,H,L
Complement of the indicated bit of the register r is copied into the zero flag.
example:

LD C,EFH
; 11101111
BIT 4,C ; 4th bit is zero, so Z=1 after the execution

BIT b,(HL) ==> 2 bytes

BIT b,(IX+d) ==> 4 bytes
BIT b,(IY+d)

Complement of the indicated bit of the contents of

memory location is copied into the zero flag

Z80 instruction Set (CCF)

CCF==> 1 byte Complement carry flag.
(make 0 if it is 1, make 1 if it is 0)

SCF==> 1 byte Set carry flag (make logic 1)

Z80 instruction Set (JP)

JP (jump)
JP label ==> 3 bytes

example:

flags are not affected

Unconditional Jump:
Load the contents of Jump instruction machine code
second and third bytes into the PC; this becomes the
memory address for the next instruction to be executed.
The previous PC contents are lost.

.
.
JP NEXT ; ADD instruction will be executed after the JP instruction.
AND 7FH
.
.
NEXT ADD A,(HL)

Z80 instruction Set (JP)

JP condition, label ==> 3 bytes

Conditional Jump:
Identical to JP instruction except
that the jump will be performed
only if the condition is satisfied,
otherwise the instruction
sequentially following the JP
condition instruction will be
executed.

condition
NZ
NonZero
Z
Zero
NC
No Carry
C
Carry
PO
Parity Odd
PE
Parity Even
P
Sign Positive
M
Sign Negative

related flag
Z (if Z=0)
Z (if Z=1)
C (if C=0)
C (if C=1)
P/O (if P/O =0)
P/O (if P/O =1)
S (if S=0)
S (if S=1)

example:
.
.
JP NC, FORWARD ; if carry=0, OR instruction is executed
AND 7FH
; next, otherwise AND instruction
FORWARD
OR B
; is executed
.
.

Z80 instruction Set (JR)

JR (jump relative)

flags are not affected

JR closelabel ==> 2 bytes

Unconditional Jump relative:
closelabel must exist in the label field of an instruction relatively close to the JR
instruction .
2-byte JR instruction is more efficient than 3-byte JP instruction in terms of
memory space and execution time.
machine code :
1st byte:
2nd byte:

18H
disp

(JR op-code byte)

(displacement byte) in the range [ -128,127]

disp = jump range - 2 (a signed 8-bit number)

the jump range from the JR instruction:
-126 bytes (backward) to
129 bytes (forward)
When the instuction is executed: PC=PC+disp+2

Z80 instruction Set (JR)

example:

LABEL

NEXT

.
.
JR NEXT
AND 7FH
.
.
ADD A,(HL)
.
.

Number of machine code bytes from the

JR NEXT instruction to the instruction
that starts with label NEXT must be less
than 130 bytes.

Z80 instruction Set (JR)

JR C,closelabel ==> 2 bytes
JR NC,closelabel
JR Z,closelabel
JR NZ,closelabel

example:

Conditional Jump relative:

Identical to the JR instruction except that the jump
will be performed only if the specified condition
(C,NC,Z,NZ) is satisfied, otherwise the instruction
sequentially following the JR condition instruction
will be executed. * There are only four conditions
available with the instruction!

.
.
ADD A,0
; A=A+0
JR Z,FORWARD ; if zero flag=1 (zero result) OR instruction is
AND 7FH
; executed next, otherwise AND instruction is
.
; executed
.
FORWARD
OR B
.

Z80 instruction Set (CP)

CP (compare with accumulator)

S,Z,H,P/V,CY are affected,

N=1 (subtaction instruction)

CP data8 ==> 2 bytes

Subtract the immediate 8 bit data from the accumulator.
The result is discarded. The contents of the accumulator are not changed, only
the flags are affected.
A - data8

example :

LD A,E3H
CP A0H

11100011 B
10100000 B
_
borrow for 7th bit (MSB) copied into the carry flag 0 01000011
CY=0 (no borrow)
Z=0 (result is nonzero)
S=0 (MSB of result)
H=0 (no borrow)
N=1 (subtraction)
P/V= carry XOR borrow for 6th bit = 0 XOR 0 = 0 (no overflow)
When signed numbers are manipulated: ==> result is correct

Z80 instruction Set (CP)

CP r ==> 1 bytes

Subtract the contents of register r from the accumulator.

The result is discarded. The contents of the accumulator are
not changed, only the flags are affected. A - r

example :

LD A,93H
LD B,C0H
CP B
borrow for 7th bit (MSB) copied into the carry flag 1

10010011 B
11000000 B
_
11010011

CY=1 (borrow)
Z=0 (result is nonzero)
S=1 (MSB of result)
H=0 (no borrow)
N=1 (subtraction)
P/V= carry XOR borrow for 6th bit = 1 XOR 1 = 0 (no overflow)
When signed numbers are manipulated: ==> result is correct

Z80 instruction Set (CP)

CP (HL)
==> 1 bytes
CP (IX+d) ==> 3 bytes
CP (IY+d)

Subtract the contents of memory location pointed by

HL (or index register) from the accumulator. The
result is discarded. The contents of the accumulator
or memory location are not changed, only the flags
are affected.
A (HL)
A (IX+d)
A (IY+d)
example :

LD A,E3H
11100011 B
LD (HL),A0
10100000 B

CP (HL)
_
borrow for 7th bit (MSB) copied into the carry flag 0 01000011
CY=0 (no borrow)
Z=0 (result is nonzero)
S=0 (MSB of result)
H=0 (no borrow)
N=1 (subtraction)
P/V= carry XOR borrow for 6th bit = 0 XOR 0 = 0 (no overflow)
When signed numbers are manipulated: ==> result is correct

Z80 instruction Set (CPLNEG)

CPL==> 1 byte

Complement the contents of the accumulator

H=1, N=1, other flags are not affected
A=(not)A

example:
LD A,3AH
CPL

NEG==> 2 byte

A <== 00111010
A <== 11000101

Negate (take 2s complement of) the accumulator

S,Z,P/V,CY are affected, N=1
A=(not)A+1

example:
LD A,5AH
NEG

A <== 01011010
A <== 10100110 (2's complement of 5AH )

Z80 instruction Set

(DEC/INC)

DEC/INC (decrement/increment by one)

S,Z,H,P/V are

affected, N=1/0 (dec/inc) , CY is not affected

DEC r / INC r
==> 1 bytes
r = r-1 / r = r+1
DEC (HL) / INC (HL)
==> 1 bytes dec/inc contents of memory
DEC (IX+d) / INC (IX+d) ==> 3 bytes
DEC (IY+d) / INC (IY+d)
example :
LD A,50H
DEC A
A <==
4FH
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

16-bit decrement / increment;

Watchout!Flags are not affected by these 16-bit DEC/INC instructions
DEC rp / INC rp ==> 1 bytes
rp = rp-1 / rp = rp+1 rp: BC,DE,HL,SP
DEC IX / INC IX ==> 2 bytes
IX=IX-1 / IX=IX+1
DEC IY / INC IY
example :
LD IY,5FFFH
INC IY
IY <==
6000H

Z80 instruction Set

(machine

control instr.)

Flags and registers are not affected.

NOP==> 1 byte

(no operation)
opcode: 00H
- PC is incremented but Z80 performs no operation during the instruction cycle.
- Used to increase time delays and delete and insert instructions during
troubleshooting.

LD B,100
; 7T
LOOP NOP
; 4T
NOP ; 4T
NOP ; 4T
DEC B
; 4T
JR NZ,LOOP
;12T

Time delay = B.[(n+1).(4T)+12T]

= 4.B.T.(n+4)
n: number of NOP instructions
T: clock period

HALT==> 1 byte
- Suspends (halts) all operationstop the program execution.
- Z80 requires an interrupt or a reset to restart execution.
- During the halt PC is not incremented and Z80 continues to execute NOP
instruction to maintain memory refresh cycles.

Simple Programs

Simple Programs

Simple Programs

Simple Programs

Simple Programs