ELEC 2200-002

Digital Logic Circuits

Fall 2012
Binary Arithmetic (Chapter 1)
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
[email protected]
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

Why Binary Arithmetic?

Hardware can only deal with binary digits,
0 and 1.
Must represent all numbers, integers or
floating point, positive or negative, by
binary digits, called bits.
Can devise electronic circuits to perform
arithmetic operations: add, subtract,
multiply and divide, on binary numbers.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

Positive Integers
Decimal system: made of 10 digits, {0,1,2, . . . , 9}
41 = 4101 + 1100
255 = 2102 + 5101 + 5100
Binary system: made of two digits, {0,1}
00101001
= 027 + 026 + 125 + 024
+123 + 022 + 021 + 120
= 32 + 8 +1 = 41
11111111 = 255, largest number with 8
binary digits, 28-1
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

Base or Radix
For decimal system, 10 is called the base or
radix.
Decimal 41 is also written as 4110 or 41ten
Base (radix) for binary system is 2.
Thus, 41ten = 1010012 or 101001two

Also,

111ten

= 1101111two

and

111two

= 7ten

What about negative numbers?

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

Signed Magnitude What Not to Do

Use fixed length binary representation
Use left-most bit (called most significant
bit or MSB) for sign:
0 for positive
1 for negative

Example:

+18ten = 00010010two
18ten = 10010010two

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

Difficulties with Signed Magnitude

Sign and magnitude bits should be differently
treated in arithmetic operations.
Addition and subtraction require different logic
circuits.
Overflow is difficult to detect.
Zero has two representations:
+ 0ten = 00000000two
0ten = 10000000two

Signed-integers are not used in modern

computers.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

Problems with Finite Math

Finite size of representation:
Digital circuit cannot be arbitrarily large.
Overflow detection easy to determine when
the number becomes too large.
Infinite
-
universe
of integers

-4

0000
0

0100
4

1000
8

1100
12

10000 10100
16
20

4-bit numbers

Represent negative numbers:

Unique representation of 0.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

4-bit Universe
1111

Modulo-16
(4-bit)
universe

15

0000
16/0

0001

1100 12

4
8

0100

1000

0000
1111
15 0
-0

0001

1100 12 -3

4
-7
8
1000

0100

7
0111

Only 16 integers: 0 through 15, or 7 through 7

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

One Way to Divide Universe

1s Complement Numbers
0000
1111
15 0
-0

0001

1100 12 -3

4
-7
8
1000

Decimal
magnitude

0100

7
0111

Negation rule: invert bits.

Problem: 0 0
Fall 2012, Aug 20 . . .

Binary number
Positive Negative

0000

1111

0001

1110

0010

1101

0011

1100

0100

1011

0101

1010

0110

1001

0111

1000

ELEC2200-002 Lecture 2

Another Way to Divide Universe

2s Complement Numbers
0000
1111
15 0
-1

0001

1100 12 -4

Subtract 1
on this side

4
-8
8
1000

0100

7
0111

Negation rule: invert bits

and add 1

Fall 2012, Aug 20 . . .

Binary number

Decimal
magnitude

Positive

0000

0001

1111

0010

1110

0011

1101

0100

1100

0101

1011

0110

1010

0111

1001

ELEC2200-002 Lecture 2

Negative

1000

10

Integers With Sign Two Ways

Use fixed-length representation, but no
explicit sign bit:
1s complement: To form a negative number,
complement each bit in the given number.
2s complement: To form a negative number, start
with the given number, subtract one, and then
complement each bit, or
first complement each bit, and then add 1.

2s complement is the preferred

representation.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

11

2s-Complement Integers
Why not 1s-complement? Dont like two zeros.
Negation rule:
Subtract 1 and then invert bits, or
Invert bits and add 1

Some properties:
Only one representation for 0
Exactly as many positive numbers as negative numbers
Slight asymmetry there is one negative number with no
positive counterpart

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ELEC2200-002 Lecture 2

12

General Method for Binary

Integers with Sign
Select number (n) of bits in representation.
Partition 2n integers into two sets:
000 through 011 are 2n/2 positive integers.
100 through 111 are 2n/2 negative integers.

Negation rule transforms negative to positive, and viceversa:

Signed magnitude: invert MSB (most significant bit)
1s complement: Subtract from 2n 1 or 11 (same as
inverting all bits)
2s complement: Subtract from 2n or 100 (same as 1s
complement + 1)
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

13

Three Systems (n = 4)
1111
7

2
1010

0000
0

0010

7
0111

1000
1010 = 2

Signed magnitude
Fall 2012, Aug 20 . . .

1111
0

0000

1111

5 7
1010
1000

10000
0000
0

0111

1010 = 5

6
1010

1000

6
0111

1010 = 6

1s complement integers 2s complement integers

ELEC2200-002 Lecture 2

14

Three Representations
Sign-magnitude

1s complement

2s complement

000 = +0
001 = +1
010 = +2
011 = +3
100 = - 0
101 = - 1
110 = - 2
111 = - 3

000 = +0
001 = +1
010 = +2
011 = +3
100 = - 3
101 = - 2
110 = - 1
111 = - 0

000 = +0
001 = +1
010 = +2
011 = +3
100 = - 4
101 = - 3
110 = - 2
111 = - 1
(Preferred)

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

15

2s Complement Numbers (n = 3)
0
000

subtraction

addition

-1 111

001 +1
s
ber
um
en
itiv
s
Pos
ber
num

a
Neg

tive

-2 110

010

+2

011 +3

-3 101
100

ow
l
f
r
Ove

Negation

-4
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

16

2s Complement n-bit Numbers

Range: 2n 1 through 2n 1 1
Unique zero: 00000000 . . . . . 0
Negation rule: see slide 11 or 13.
Expansion of bit length: stretch the left-most bit all the
way, e.g., 11111101 is still 101 or 3. Also, 00000011 is
same as 011 or 3.
Most significant bit (MSB) indicates sign.
Overflow rule: If two numbers with the same sign bit
(both positive or both negative) are added, the overflow
occurs if and only if the result has the opposite sign.
Subtraction rule: for A B, add B and A.

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

17

Summary
For a given number (n) of digits we have a
finite set of integers. For example, there are
103 = 1,000 decimal integers and 2 3 = 8 binary
integers in 3-digit representations.
We divide the finite set of integers [0, r n 1],
where radix r = 10 or 2, into two equal parts
representing positive and negative numbers.
Positive and negative numbers of equal
magnitudes are complements of each other: x
+ complement (x) = 0.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

18

Summary: Defining Complement

Decimal integers:
10s complement: x = Complement (x) = 10n x
9s complement: x = Complement (x) = 10 n 1 x

For 9s complement, subtract each digit from 9

For 10s complement, add 1 to 9s complement

Binary integers:
2s complement: x = Complement (x) = 2n x
1s complement: x = Complement (x) = 2n 1 x

For 1s complement, subtract each digit from 1

For 2s complement, add 1 to 1s complement
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

19

Understanding Complement
Complement means something that
completes:
e.g., X + complement (X) = Whole.
Complement also means opposite,
e.g., complementary colors are placed
opposite in the primary color chart.
Complementary numbers are like electric
charges. Positive and negative charges
of equal magnitudes annihilate each
other.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

20

2s-Complement Numbers
Infinite - . . . -1
universe
of integers

Finite
Universe of
3-digit
Decimal
numbers

999

000
0

001
1

1000
000

501

010
2

011
3

111

1000
000

001

001

499

011

101

500
Fall 2012, Aug 20 . . .

100
4

101
5...

Finite
Universe
of 3-bit
binary
numbers

100
ELEC2200-002 Lecture 2

21

Examples of Complements
Decimal integers (r = 10, n = 3):
10s complement: 50 = Compl (50) = 103 50 =
950; 50 + 950 = 1,000 = 0 (in 3 digit representation)
9s complement: 50 = Compl (50) = 10n 1 50 =
949; 50 + 949 = 999 = 0 (in 9s complement rep.)

Binary integers (r = 2, n = 4):

2s complement: 5 = Complement (5) = 24 5 =
1110 or 1011; 5 + 11 = 16 = 0 (in 4-bit representation)
1s complement: 5 = Complement (5) = 24 1 5 =
1010 or 1010; 5 + 10 = 15 = 0 (in 1s complement
representation)
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

22

2s-Complement to Decimal
Conversion
n-2

bn-1 bn-2 . . . b1 b0 = 2n-1bn-1 + 2i bi

i=0

8-bit conversion box

-128 64 32 16 8 4 2
Example -128 64 32 16
1
1 1 1

8
1

4
1

2
0

1
1
1

128 + 64 + 32 + 16 + 8 + 4 + 1 = 128 + 125 = 3

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

23

For More on 2s-Complement

Donald E. Knuth (1938 - )

Abu Abd-Allah ibn Musa

alKhwarizmi (~780 850)

Chapter 4 in D. E. Knuth, The Art of Computer Programming:

Seminumerical Algorithms, Volume II, Second Edition, AddisonWesley, 1981.
A. alKhwarizmi, Hisab al-jabr wal-muqabala, 830.
Read: A two part interview with D. E. Knuth, Communications
of the ACM (CACM), vol. 51, no. 7, pp. 35-39 (July), and no. 8,
pp. 31-35 (August), 2008.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

24

Addition
Adding bits:
0+0=
0
0+1=
1
1+0=
1
1 + 1 = (1) 0

carry

Adding integers:

0 0 0...... 0
0 0 0...... 0

1
1

1
1

1 two =
0 two =

7ten
6ten

= 0 0 0 . . . . . . 1 (1)1 (1)0 (0)1 two = 13ten

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

25

Subtraction
Direct subtraction
0 0 0......0
0 0 0......0

1
1

1
1

1 two =
0 two =

7ten
6ten

= 0 0 0...... 0

1two =

1ten

Twos complement subtraction by adding

+

1 1 1......1
0 0 0......0
1 1 1......1

1
1
0

0
1
1

1 two = 7ten
0 two = 6ten

= 0 0 0 . . . . . . 0 (1) 0 (1) 0 (0)1 two =

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

1ten
26

Overflow: An Error
Examples: Addition of 3-bit integers (range - 4 to +3)
-2-3 = -5
110 = -2
+ 101 = -3
= 1011 = 3 (error)

000
0

111
-1

1
+

2 010

110 -2

3+2 = 5

011 = 3
010 = 2
= 101 = -3 (error)

101

-3

-4

001

011

100 Overflow
crossing

Overflow rule: If two numbers with the same sign bit

(both positive or both negative) are added, the overflow
occurs if and only if the result has the opposite sign.
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ELEC2200-002 Lecture 2

27

Overflow and Finite Universe

Decrease

1111
1110
1101
1100

0000

1011
1010

1001 1000
Fall 2012, Aug 20 . . .

0010

Increase
0011 0100

0001
0010
Increase

Infinite - . . .1111
universe
of integers
No overflow

Decrease
0000
0001

0011
0100
0101
0110
0111

Forbidden fence

ELEC2200-002 Lecture 2

0101 . . .

Finite
Universe
of 4-bit
binary
integers

28

Adding Two Bits

a

s = a+b
Decimal

Binary

00

01

01

10

CARRY
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

SUM
29

Half-Adder Adds two Bits

Adding two bits:
a b
0
0
1
1

0
1
0
1

half_sum carry_out
h_s(a, b) c_o(a, b)
a
0
0
1
0
b
1
0
0
1

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

XOR

half_sum

HA
AND

carry_out

30

Adding Three Bits

a

s=a+b+c
Decimal

Binary

00

01

01

10

01

10

10

11
CARRY

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

SUM
31

Full-Adder Adds Three Bits

c_in
XOR

HA
AND

Fall 2012, Aug 20 . . .

FA

h_s
(a, b)

XOR
c_o
(a, b)

HA
AND

ELEC2200-002 Lecture 2

h_s
(h_s(a, b), c_in)

sum

c_o
(h_s(a, b), c_in)

OR

c_out

32

32-bit Ripple-Carry Adder

c0=0
a0
b0

FA0
a1
b1

sum0

FA1
a2
b2

sum1

FA2

sum2

a31
b31

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

FA31

sum31

33

How Fast is Ripple-Carry Adder?

Longest delay path (critical path) runs from
(a0, b0) to sum31.
Suppose delay of full-adder is 100ps.
Critical path delay = 3,200ps
Clock rate cannot be higher than 1/
(3,20010 12) Hz = 312MHz.
Must use more efficient ways to handle
carry.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

34

Speeding Up the Adder

b0-b15
cin
a16-a31
b16-b31
0
a16-a31
b16-b31
1
Fall 2012, Aug 20 . . .

16-bit
ripple
carry
adder
16-bit
ripple
carry
adder
16-bit
ripple
carry
adder

sum0-sum15

0
Multiplexer

a0-a15

sum16-sum31

ELEC2200-002 Lecture 2

This is a carry-select adder

35

Fast Adders
In general, any output of a 32-bit adder can
be evaluated as a logic expression in terms
of all 65 inputs.
Number of levels of logic can be reduced to
log2N for N-bit adder. Ripple-carry has N
levels.
More gates are needed, about log 2N times
that of ripple-carry design.
Fastest design is known as carry
lookahead adder.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

36

N-bit Adder Design Options

Type of adder

Time complexity
(delay)

Space complexity
(size)

Ripple-carry

O(N)

O(N)

Carry-lookahead

O(log2N)

O(N log2N)

Carry-skip

O(N)

O(N)

Carry-select

O(N)

O(N)

Reference: J. L. Hennessy and D. A. Patterson, Computer Architecture:

A Quantitative Approach, Second Edition, San Francisco, California,
1990, page A-46.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

37

Binary Multiplication (Unsigned)

1 0 0 0 two

= 8ten

multiplicand

1 0 0 1 two
____________

= 9ten

multiplier

1000
0000
0000
1000
____________
1 0 0 1 0 0 0two

Fall 2012, Aug 20 . . .

partial products

= 72ten

ELEC2200-002 Lecture 2

Basic algorithm: For n = 1, 32,

only If nth bit of multiplier is 1,
then add multiplicand 2 n 1
to product

38

Multiplication Flowchart
Start

Initialize product register to 0

Partial product number, n = 1

Add multiplicand to
product and place result
in product register

LSB
of multiplier
?

Left shift multiplicand register 1 bit

Right shift multiplier register 1 bit
Done

Fall 2012, Aug 20 . . .

n = 32

n=?

ELEC2200-002 Lecture 2

n < 32

n=n+1

39

Serial Multiplication
shift left

shift right

Multiplicand (expanded 64-bits)

64

shift

64

add

64-bit ALU

LSB
=1

64
64-bit product register

Fall 2012, Aug 20 . . .

32-bit multiplier

write

ELEC2200-002 Lecture 2

Test LSB
32 times

LSB = 0

3 operations per bit:

shift right
shift left
add
Need 64-bit ALU
40

Serial Multiplication (Improved)

2 operations per bit:
shift right
add
32-bit ALU

Multiplicand
32

32

add

Test LSB
32 times

32-bit ALU
LSB
1

32
64-bit product register

e
rit

shift right

00000 . . . 00000 32-bit multiplier Initialized product register

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

41

Example: 0010two 0011two

0010two 0011two = 0110two, i.e., 2ten 3ten = 6ten
Iteration

Step

Multiplicand

Product

Initial values

0010

0000 0011

LSB =1 => Prod = Prod + Mcand

0010

0010 0011

Right shift product

0010

0001 0001

LSB =1 => Prod = Prod + Mcand

0010

0011 0001

Right shift product

0010

0001 1000

LSB = 0 => no operation

0010

0001 1000

Right shift product

0010

0000 1100

LSB = 0 => no operation

0010

0000 1100

Right shift product

0010

0000 0110

2
3
4

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

42

Multiplying with Signs

Convert numbers to magnitudes.
Multiply the two magnitudes through 32
iterations.
Negate the result if the signs of the multiplicand
and multiplier differed.
Alternatively, the previous algorithm will work
with some modifications. See B. Parhami,
Computer Architecture, New York: Oxford
University Press, 2005, pp. 199-200.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

43

Example 1: 1010two 0011two

1010two 0011two = 101110two, i.e., 6ten 3ten = 18ten
Iteration

Step

Multiplicand

Product

Initial values

11010

00000 0011

LSB = 1 => Prod = Prod + Mcand

11010

11010 0011

Right shift product

11010

11101 0001

LSB = 1 => Prod = Prod + Mcand

11010

10111 0001

Right shift product

11010

11011 1000

LSB = 0 => no operation

11010

11011 1000

Right shift product

11010

11101 1100

LSB = 0 => no operation

11010

11101 1100

Right shift product

11010

11110 1110

2
3
4

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

44

Example 2: 1010two 1011two

1010two 1011two = 011110two, i.e., 6ten ( 5ten) = 30ten
Iteration

Step

Multiplicand

Product

Initial values

11010

00000 1011

LSB =1 => Prod = Prod + Mcand

11010

11010 1011

Right shift product

11010

11101 0101

LSB =1 => Prod = Prod + Mcand

11010

10111 0101

Right shift product

11010

11011 1010

LSB = 0 => no operation

11010

11011 1010

Right shift product

11010

11101 1101

LSB =1 => Prod = Prod Mcand*

00110

00011 1101

Right shift product

11010

00001 1110

2
3
4

*Last iteration with a negative multiplier in 2s complement.

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

45

Adding Partial Products

y3
y2
y1
y0
x3
x2
x1
x0
________________________
x0y3 x0y2 x0y1 x0y0
carry x1y3 x1y2 x1y1 x1y0
carry x2y3 x2y2 x2y1 x2y0
carry x3y3
x3y2 x3y1 x3y0
__________________________________________________
p7
p6
p5
p4
p3
p2
p1
p0

multiplicand
multiplier
four
partial
products
to be
summed

Requires three 4-bit additions. Slow.

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

46

Array Multiplier: Carry Forward

y3
y2
y1
y0
x3
x2
x1
x0
________________________
x0y3 x0y2 x0y1 x0y0
x1y3 x1y2 x1y1 x1y0
x2y3 x2y2 x2y1 x2y0
x3y3 x3y2 x3y1 x3y0
__________________________________________________
p7
p6
p5
p4
p3
p2
p1
p0

multiplicand
multiplier
four
partial
products
to be
summed

Note: Carry is added to the next partial product (carry-save addition).

Adding the carry from the final stage needs an extra (ripple-carry
stage. These additions are faster but we need four stages.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

47

Basic Building Blocks

Two-input AND
Full-adder
yi

x0

yi

xk

sum bit
from (k-1)th
sum

carry bits
from (k-1)th
sum
Full
adder

p0i = x0yi
0 partial product
th

Fall 2012, Aug 20 . . .

carry bits
to (k+1)th
sum

ELEC2200-002 Lecture 2

ith bit of
kth partial
product

Slide 24

sum bit
to (k+1)th
sum
48

y3

Array Multiplier
ppk
yj

xi

y2

y1

y0

x0
0

x1

ci

FA
x2
co
ppk+1

0
x3

Critical path
0

FA
p7
Fall 2012, Aug 20 . . .

FA
p6

FA
p5

FA
p4

ELEC2200-002 Lecture 2

0
p3

p2

p1

p0
49

Types of Array Multipliers

Baugh-Wooley Algorithm: Signed product
by twos complement addition or
subtraction according to the MSBs.
Booth multiplier algorithm
Tree multipliers
Reference: N. H. E. Weste and D. Harris,
CMOS VLSI Design, A Circuits and
Systems Perspective, Third Edition,
Boston: Addison-Wesley, 2005.
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ELEC2200-002 Lecture 2

50

Binary Division (Unsigned)

13
11/147
11
37
33
4

Fall 2012, Aug 20 . . .

Quotient
00001101
Divisor / Dividend 1 0 1 1 / 1 0 0 1 0 0 1 1
1011
Partial remainder
001110
1011
Remainder
001111
1011
100

ELEC2200-002 Lecture 2

51

Iteration 4 Iteration 3

6
= 1, remainder 2
4

Iteration 1

Dividend: 6 = 0110
Divisor: 4 = 0100
4 = 1100

0001
0000110
1100
1100

Iteration 2

4-bit Binary Division (Unsigned)

Fall 2012, Aug 20 . . .

0100
0000110
1100
1101

negative quotient bit

restore remainder

negative quotient bit

0100
000110
1100
1111

restore remainder

negative quotient bit

0100
00110
1 0 20
ELEC2200-002 1
Lecture

restore remainder
52

32-bit Binary Division Flowchart

Start

$R = 0, $M = Divisor, $Q = Dividend, count = n

Shift 1-bit left $R, $Q

$R and $M have
one extra sign bit
beyond 32 bits.

$R $R $M
$Q0 = 1

No

Yes

$R < 0?

count = count 1
No

Fall 2012, Aug 20 . . .

count = 0?

$R (33 b) | $Q (32 b)

Yes

ELEC2200-002 Lecture 2

$Q0=0
$R $R + $M
Restore $R
(remainder)
Done
$Q = Quotient
$R = Remainder
53

count
4

4-bit Example: 6/4 = 1, Remainder 2

Actions

$R, $Q

$M = Divisor

Initialize

00000|0110

00100

Shift left $R, $Q

00000|1100

00100

Add $M (11100) to $R

11100|1100

00100

Restore, add $M (00100) to $R

00000|1100

00100

Shift left $R, $Q

00001|1000

00100

Add $M (11100) to $R

11101|1000

00100

Restore, add $M (00100) to $R

00001|1000

00100

Shift left $R, $Q

00011|0000

00100

Add $M (11100) to $R

11111|0000

00100

Restore, add $M (00100) to $R

00011|0000

00100

Shift left $R, $Q

00110|0000

00100

Add $M (11100) to $R

00010|0000

00100

Set LSB of $Q = 1

00010|0001
Remainder | Quotient

00100

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

54

Division
33-bit $M (Divisor)
33

33 Step 2: Subtract $R $R $M

33-bit ALU
Initialize
Step 1: 1- bit left shift $R and $Q 32 times
33
$R0
33-bit $R (Remainder)
32-bit $Q (Dividend)
Step 3: If sign-bit ($R) = 0, set Q0 = 1
If sign-bit ($R) = 1, set Q0 = 0 and restore $R
V. C. Hamacher, Z. G. Vranesic and S. G. Zaky, Computer Organization, Fourth Edition,
New York: McGraw-Hill, 1996.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

55

Example: 8/3 = 2, Remainder = 2

Iteration 1

Initialize

$R

= 00000

$Q =

1 0 0 0 $M =

= 00001
= 11101
= 11110

$Q =

0000

$Q =

0000

$R
= 00010
$M = 1 1 1 0 1
$R = 1 1 1 1 1

$Q =

0 0 0 0 $M =

Step 3, Set Q0
Restore + $M = 0 0 0 1 1
$R = 0 0 0 1 0

$Q =

0000

Iteration 2

Step 1, L-shift $R
Step 2, Add
$M
$R
Step 3, Set Q0
Restore + $M
$R
Step 1, L-shift
Step 2, Add

Fall 2012, Aug 20 . . .

00011

= 00011
= 00001

ELEC2200-002 Lecture 2

00011

56

Example: 8/3 = 2 (Remainder = 2)

(Continued)

Iteration 4

Iteration 3

$R

= 00010

$Q =

0 0 0 0 $M =

00011

= 00100
= 11101
= 00001

$Q =

0 0 0 0 $M =

00011

$Q =

0001

$R,Q = 0 0 0 1 0
$M = 1 1 1 0 1
$R = 1 1 1 1 1

$Q =

0 0 1 0 $M =

Step 3, Set Q0
Restore + $M = 0 0 0 1 1
$R
= 00010

$Q =

0 0 1 0 Final quotient

Step 1, L-shift $R
Step 2, Add
$M
$R
Step 3, Set Q0
Step 1, L-shift
Step 2, Add

00011

Remainder
Note Restore $R in Steps 1, 2 and 4. This method is known as
the RESTORING DIVISION. An improved method, NON-RESTORING
DIVISION, is possible (see Hamacher, et al.)
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

57

Non-Restoring Division
Avoid unnecessary addition (restoration).
How it works?
Initially $R contains dividend 2 n for n-bit numbers. Example (n = 8):

In some iteration after left shift, suppose $R = x and divisor is y

Subtract divisor, $R = x y
Restore: If $R is negative, add y, $R = x
Next step: Left shift, $R = 2x+b, and subtract y, $R = 2x y + b

Fall 2012, Aug 20 . . .

Dividend

00101101

$R, $Q

00000000 00101101

ELEC2200-002 Lecture 2

58

How It Works: Last two Steps

Suppose we do not restore and go to next step:
Left shift, $R = 2(x y) + b = 2x 2y + b, and add y, then $R = 2x
2y + y + b = 2x y + b (same result as with restoration)

Non-restoring division
Initialize and start iterations same as in restoring
division by subtracting divisor
In any iteration after left shift and subtraction/addition
If $R is positive, subtract divisor (y) in next iteration
If $R is negative, add divisor (y) in next iteration

After final iteration, if $R is negative then restore it by

adding divisor (y)

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

59

Example: 8/3 = 2, Remainder = 2

Non-Restoring Division

Iteration 2

Iteration 1

Initialize

$R

= 00000

$Q =

1 0 0 0 $M =

Step 1, L-shift $R = 0 0 0 0 1
Step 2, Add
$M = 1 1 1 0 1
$R = 1 1 1 1 0
Step 3, Set Q0

$Q =

0000

$Q =

0000

Step 1, L-shift
Step 2, Add

$Q =

0 0 0 0 $M =

$Q =

0000

$R
= 11100
+ $M = 0 0 0 1 1
$R = 1 1 1 1 1

00011

00011

Step 3, Set Q0
Add + $M in next iteration

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

60

Example: 8/3 = 2 (Remainder = 2)

Non-Restoring Division (Continued)

Iteration 4

Iteration 3

$R

= 11111

$Q =

0 0 0 0 $M =

00011

= 11110
= 00011
= 00001

$Q =

0 0 0 0 $M =

00011

$Q =

0001

$R,Q = 0 0 0 1 0
$M = 1 1 1 0 1
$R = 1 1 1 1 1

$Q =

0 0 1 0 $M =

$Q =

0 0 1 0 Final quotient = 2

Step 1, L-shift $R
Step 2, Add
+ $M
$R
Step 3, Set Q0
Step 1, L-shift
Step 2, Add

Step 3, Set Q0
Restore + $M = 0 0 0 1 1
$R
= 00010

00011

Remainder = 2

See, V. C. Hamacher, Z. G. Vranesic and Z. G. Zaky, Computer

Organization, Fourth Edition, McGraw-Hill, 1996, Section 6.9, pp.
281-285.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

61

Signed Division
Remember the signs and divide
magnitudes.
Negate the quotient if the signs of divisor
and dividend disagree.
There is no other direct division method
for signed division.

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

62

Symbol Representation
Early versions (60s and 70s)
Six-bit binary code (Control Data Corp., CDC)
EBCDIC extended binary coded decimal
interchange code (IBM)

Presently used
ASCII American standard code for information
interchange 7 bit code specified by American
National Standards Institute (ANSI), see Table 1.11
on page 63; an eighth MSB is often used as parity
bit to construct a byte-code.
Unicode 16 bit code and an extended 32 bit
version
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

63

ASCII
Each byte pattern represents a character (symbol)
Convenient to write in hexadecimal, e.g., with even parity,
00000000 0ten 00hex
null
01000001 65ten 41hex
A
11100001 225ten E1hex
a
Table 1.11 on page 63 gives the 7-bit ASCII code.
C program string terminating with a null byte (odd
parity):
01000101
01000011
01000101
10000000
69ten or 45hex 67ten or 43hex 69ten or 45hex 128ten or 80hex
E
C
E
(null)

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

64

Error Detection Code

Errors: Bits can flip due to noise in circuits
and in communication.
Extra bits used for error detection.
Example: a parity bit in ASCII code
7-bit ASCII code

Even parity code for A

01000001
Parity bits

(even number of 1s)

Odd parity code for A

11000001

(odd number of 1s)

Single-bit error in 7-bit code of A, e.g., 1000101, will change

symbol to E or 1000000 to @. But error will be detected in
the 8-bit code because the error changes the specified parity.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

65

Richard W. Hamming
Error-correcting codes
(ECC).
Also known for
Hamming distance (HD)
= Number of bits two
binary vectors differ in
Example:
HD(1101, 1010) = 3
Hamming Medal, 1988
1915 -1998
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

66

The Idea of Hamming Code

Code space contains 2N possible N-bit code words:
0010
2

1110
E

HD = 1

HD = 1

1010
A

1-bit error in A

HD = 1
HD = 1
1000
8

1011
B

Error not correctable. Reason: No redundancy.

Hammings idea: Increase HD between valid code words.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

N=4
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Symbol
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F 67

Hammings Distance 3 Code

1110100

0010101

HD = 4

HD = 4

HD = 3

HD = 3

1-bit error in A
shortest distance
decoding eliminates
error

0010010

HD = 1

1010010

0011110

HD = 2

HD = 4
1000111

HD = 3

HD = 3

8
1011001

B
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

68

Minimum Distance-3 Hamming Code

Symbol

Original
code

Odd-parity
code

ECC, HD 3

0000

10000

0000000

0001

00001

0001011

0010

00010

0010101

0011

10011

0011110

0100

00100

0100110

0101

10101

0101101

0110

10110

0110011

0111

00111

0111000

1000

01000

1000111

1001

11001

1001100

1010

11010

1010010

1011

01011

1011001

1100

11100

1100001

1101

01101

1101010

1110

01110

1110100

1111

11111

1111111

Fall 2012, Aug 20 . . .

Original code: Symbol 0 with a

single-bit error will be Interpreted as
1, 2, 4 or 8.
Reason: Hamming distance between
codes is 1. A code with any bit error will
map onto another valid code.
Remedy 1: Design codes with HD 2.
Example: Parity code. Single bit error
detected but not correctable.
Remedy 2: Design codes with HD 3.
For single bit error correction, decode
as the valid code at HD = 1.
For more error bit detection or
correction, design code with HD 4.

ELEC2200-002 Lecture 2

69

Integers and Real Numbers

Integers: the universe is infinite but discrete
No fractions
No numbers between consecutive integers, e.g., 5 and 6
A countable (finite) number of items in a finite range
Referred to as fixed-point numbers
Real numbers the universe is infinite and continuous
Fractions represented by decimal notation
Rational numbers, e.g., 5/2 = 2.5
Irrational numbers, e.g., 22/7 = 3.14159265 . . .
Infinite numbers exist even in the smallest range
Referred to as floating-point numbers
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

70

Wide Range of Numbers

A large number:
976,000,000,000,000 = 9.76 1014
A small number:
0.0000000000000976 = 9.76 10 14

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

71

Scientific Notation
Decimal numbers
0.513105, 5.13104 and 51.3103 are written in
scientific notation.
5.13104 is the normalized scientific notation.

Binary numbers
Base 2
Binary point multiplication by 2 moves the point
to the right.
Normalized scientific notation, e.g., 1.0two2 1

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

72

Floating Point Numbers

General format
1.bbbbbtwo2eeee
or (-1)S (1+F) 2E
Where
S =
F =

sign, 0 for positive, 1 for negative

fraction (or mantissa) as a binary integer,
1+F is called significand
E =
exponent as a binary integer, positive or
negative (twos complement)
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

73

Binary to Decimal Conversion

Binary

(-1)S (1.b1b2b3b4) 2E

Decimal

(-1)S (1 + b12-1 + b22-2 + b32-3 + b42-4) 2E

Example:

-1.1100 2-2 (binary)

= - (1 + 2-1 + 2-2) 2-2

= - (1 + 0.5 + 0.25)/4
= - 1.75/4
= - 0.4375 (decimal)

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

74

William Morton (Velvel) Kahan

Architect of the IEEE floating point standard

1989 Turing Award Citation:

For his fundamental contributions to
numerical analysis. One of the
foremost experts on floating-point
computations. Kahan has dedicated
himself to "making the world safe
for numerical computations."

b. 1933, Canada
Professor of Computer Science, UC-Berkeley
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

75

Numbers in 32-bit Formats

Twos complement integers
Expressible numbers
0
-231
231-1

Floating point numbers

Positive underflow

Negative underflow
Negative zero

Negative
Overflow

Positive zero
Expressible
positive
numbers

Expressible
negative
numbers

- (2 2-23)2128

-2-127

2-127

+
Positive
Overflow

(2 2-23)2128

Ref: W. Stallings, Computer Organization and Architecture, Sixth

Edition, Upper Saddle River, NJ: Prentice-Hall.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

76

IEEE 754 Floating Point Standard

Biased exponent: true exponent range
[-126,127] is changed to [1, 254]:
Biased exponent is an 8-bit positive binary integer.
True exponent obtained by subtracting 127ten or
01111111two

First bit of significand is always 1:

1.bbbb . . . b 2E
1 before the binary point is implicitly assumed.
Significand field represents 23 bit fraction after the
binary point.
Significand range is [1, 2), to be exact [1, 2 2 -23]
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

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Examples
Biased exponent (0-255), bias 127 (01111111) to be subtracted
1.1010001 210100 = 0 10010011 10100010000000000000000 = 1.6328125 220
-1.1010001 210100 = 1 10010011 10100010000000000000000 = -1.6328125 220

1.1010001 2-10100 = 0 01101011 10100010000000000000000 = 1.6328125 2-20

-1.1010001 2-10100 = 1 01101011 10100010000000000000000 = -1.6328125 2-20

1.0
0.5
0.125
0.0078125
1.6328125
Fall 2012, Aug 20 . . .

8-bit biased exponent

107 127
Sign bit
= 20

ELEC2200-002 Lecture 2

23-bit Fraction (F)

of significand

78

Example: Conversion to Decimal

normalized E
bits 23-30

Sign bit S

F
bits 0-22

1 10000001 01000000000000000000000

Sign bit is 1, number is negative

Biased exponent is 27+20 = 129
The number is
(-1)S (1 + F) 2(exponent bias) =
=
=
=

Fall 2012, Aug 20 . . .

(-1)1 (1 + F) 2(129 127)

- 1 1.25 22
- 1.25 4
- 5.0

ELEC2200-002 Lecture 2

79

IEEE 754 Floating Point Format

Floating point numbers
Sign bit S

normalized E
bits 23-30

F
bits 0-22

1 1011001 01001100000000010001101
Positive integer 127 = E

Positive underflow

Negative underflow

Negative
Overflow

- (2 2

Expressible
negative
numbers
-23

)2

Fall 2012, Aug 20 . . .

127

+0
Expressible
positive
numbers

-2-126

2-126

ELEC2200-002 Lecture 2

Positive
Overflow

(2 2-23)2127
80

Positive Zero in IEEE 754

0 00000000 00000000000000000000000
Biased
exponent

Fraction

+ 1.0 2127
Smallest positive number in single-precision
IEEE 754 standard.
Interpreted as positive zero.
True exponent less than 126 is positive
underflow; can be regarded as zero.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

81

Negative Zero in IEEE 754

1 00000000 00000000000000000000000
Biased
exponent

Fraction

1.0 2127
Smallest negative number in single-precision
IEEE 754 standard.
Interpreted as negative zero.
True exponent less than 126 is negative
underflow; may be regarded as 0.
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

82

Positive Infinity in IEEE 754

0 11111111 00000000000000000000000
Biased
exponent

Fraction

+ 1.0 2128
Largest positive number in single-precision IEEE
754 standard.
Interpreted as +
If true exponent = 128 and fraction 0, then the
number is greater than . It is called not a
number or NaN and may be interpreted as .
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

83

Negative Infinity in IEEE 754

1 11111111 00000000000000000000000
Biased
exponent

Fraction

1.0 2128
Smallest negative number in single-precision
IEEE 754 standard.
Interpreted as -
If true exponent = 128 and fraction 0, then the
number is less than - . It is called not a number
or NaN and may be interpreted as - .
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

84

Addition and Subtraction

0. Zero check
-

Change the sign of subtrahend, i.e., convert to summation

If either operand is 0, the other is the result

1. Significand alignment: right shift significand of

smaller exponent until two exponents match.
2. Addition: add significands and report error if
overflow occurs. If significand = 0, return result
as 0.
3. Normalization
-

Shift significand bits to normalize.

report overflow or underflow if exponent goes out of range.

4. Rounding
Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

85

Example (4 Significant Fraction Bits)

Subtraction: 0.5ten 0.4375ten
Step 0:

Floating point numbers to be added

1.000two 2 1 and 1.110two 2 2

Step 1:

Significand of lesser exponent is shifted

right until exponents match
1.110two 2 2 0.111two 2 1

Step 2:
01000
+11001
00001

Add significands, 1.000two + ( 0.111two)

Result is 0.001two 2 1

2s complement addition, one bit added for sign

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

86

Example (Continued)
Step 3: Normalize, 1.000two 2

No overflow/underflow since
127 exponent 126

Step 4: Rounding, no change since the sum

fits in 4 bits.
1.000two 2
Fall 2012, Aug 20 . . .

4=

(1+0)/16 = 0.0625ten

ELEC2200-002 Lecture 2

87

FP Multiplication: Basic Idea

1. Separate sign
2. Add exponents (integer addition)
3. Multiply significands (integer multiplication)
4. Normalize, round, check

overflow/underflow
5. Replace sign

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

88

FP Multiplication: Step 0
Multiply, X Y = Z

X = 0?
yes

no

Y = 0?

no

Steps 1 - 5

yes

Z=0

Return

Fall 2012, Aug 20 . . .

ELEC2200-002 Lecture 2

89

FP Multiplication Illustration
Multiply 0.5ten and 0.4375ten
(answer = 0.21875ten) or
Multiply 1.000two2 1 and 1.110two2
Step 1: Add exponents
1 + (2) = 3
Step 2: Multiply significands

1.000
1.110
0000
1000
1000
1000
1110000
Fall 2012, Aug 20 . . .

Product is 1.110000
ELEC2200-002 Lecture 2

90

FP Mult. Illustration (Cont.)

Step 3:
Normalization: If necessary, shift significand right and
increment exponent.
Normalized product is 1.110000 2 3
Check overflow/underflow: 127 exponent 126

Step 4: Rounding: 1.110 2 3

Step 5: Sign: Operands have opposite signs,
Product is 1.110 2 3
(Decimal value = (1+0.5+0.25)/8 = 0.21875ten)

Fall 2012, Aug 20 . . .

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91

FP Division: Basic Idea

Separate sign.
Check for zeros and infinity.
Subtract exponents.
Divide significands.
Normalize and detect overflow/underflow.
Perform rounding.
Replace sign.
Fall 2012, Aug 20 . . .

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92