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Electronic Syatem Design PPT - Design For Testability

This document discusses design for testability (DFT) techniques. It covers bare board tests to test for opens and shorts, as well as loaded board tests which specify considerations like one test node per circuit and probe spacing. The document also describes classification of tests based on strategy, including vector tests using test vectors to test functionality, and scan tests to exercise parts through functions. Finally, it discusses design for test fixtures like bed-of-nails and flying probe testers.

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Anoop Mathew
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233 views9 pages

Electronic Syatem Design PPT - Design For Testability

This document discusses design for testability (DFT) techniques. It covers bare board tests to test for opens and shorts, as well as loaded board tests which specify considerations like one test node per circuit and probe spacing. The document also describes classification of tests based on strategy, including vector tests using test vectors to test functionality, and scan tests to exercise parts through functions. Finally, it discusses design for test fixtures like bed-of-nails and flying probe testers.

Uploaded by

Anoop Mathew
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Course: ES 10 105 A /VL 11 105 A - Electronic System design

Design for Testability (DFT)

Faculty: Anoop Mathew, HoD ECE

3/21/15

Introduction
Design for Test (DFT), also known as Design
for Testability, is the first part of the test
techniques.
Design for test attempts to minimize the cost
and maximize the success and value of the
test process.
Faults that occur during the manufacturing
process are checked at shorts/opens,
Manufacturing Defect Analyzer (MDA), and
in-circuit tests are known as manufacturing
defects.
The design and test teams must understand
which type of faults are most likely to occur
in their product and design to minimize these
expected faults.

Bare Board Tests


Bare-board test is the first step in the series
of tests used in circuit board assembly.
Bare board testing must include tests for
continuity of traces, vias, through-holes to
rule out any opens and isolation tests to rule
out shorts between adjacent traces and vias.

Loaded Board Tests


General test considerations require:
One test node per circuit net
Test fixture probe spacing of 0.080 in (2 mm) minimum
Probe-to-device clearance of 0.030 in (0.9 mm) minimum
All test node accessible from one side of the board
A test node on any active unused pins
Provision of extra gates to control and back-drive clock
circuits
Insertion of extra gates or jumpers in feedback loops and
where needed to control critical circuit paths
Unused inputs tied to pull-up or pull-down resistors so
that individual devices may be isolated and back-driven
by the ATE system
Provision of a simple means of initializing all registers,
flip-flops, counters, and state machines in the circuit
Testability built into microprocessor-based boards

Classification of Tests
based on physical strategies
Incoming inspection to verify individual
component specs
Production in-circuit tests (ICT)
Functional tests on the assembly/product

Vector Tests
Vector tests are primarily designed to test
the functionality of a digital device before it
becomes part of an assembly.
A test vector is a set of input conditions that
result in defined output(s).
Test vectors for programmable devices such
as PLDs, CPLDs, and FPGAs can be generated
automatically, using an automatic test
program generator (ATPG).

Scan Test for Digital Devices


Scan tests are designed to develop a test
vector, or set of test vectors, to exercise the
part through its functions.
Boundary scan, a.k.a. JTAG or 1149.1 test, is
a more closely defined series of tests for
digital devices.

Design for Test Fixtures


1. Design for Bed-of-Nails Fixtures
2. Design for Flying Probe Testers

Thank You

Queries ???
Mail to: [email protected]
3/21/15

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