Digital Design:

An Embedded Systems
Approach Using Verilog
Chapter 3
Numeric Basics

Portions of this work are from the book, Digital Design: An

Embedded Systems Approach Using Verilog, by Peter J. Ashenden,
published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier
Inc. All rights reserved.

Verilog

Numeric Basics

Representing and processing

numeric data is a common
requirement

unsigned integers
signed integers
fixed-point real numbers
floating-point real numbers
complex numbers
Digital Design Chapter 3 Numeric Basi

Verilog

Unsigned Integers

Non-negative numbers (including 0)

Represent real-world data

Also used in controlling operation of a

digital system

e.g., temperature, position, time,

e.g., counting iterations, table indices

Coded using unsigned binary (base

2) representation

analogous to decimal representation

Digital Design Chapter 3 Numeric Basi

Verilog

Binary Representation

Decimal: base 10

Binary: base 2

12410 = 1102 + 2101 + 4100

12410
= 126+125+124+123+122+021+020
= 11111002

In general, a number x is represented using

n bits as xn1, xn2, , x0, where

x xn 1 2 n 1 xn 2 2 n 2 x0 20
Digital Design Chapter 3 Numeric Basi

Verilog

Binary Representation

Unsigned binary is a code for numbers

n bits: represent numbers from 0 to 2n 1

To represent x: 0 x N 1, need
log2N bits

Computers use

0: 000000; 2n 1: 111111

8-bit bytes: 0, , 255

32-bit words: 0, , ~4 billion

Digital circuits can use what ever size

is appropriate
Digital Design Chapter 3 Numeric Basi

Verilog

Unsigned Integers in
Verilog

Use vectors as the representation

Can apply arithmetic operations

module multiplexer_6bit_4_to_1
( output reg [5:0] z,
input
[5:0] a0, a1, a2, a3,
input
[1:0] sel );
always @*
case (sel)
2'b00: z = a0;
2'b01: z = a1;
2'b10: z = a2;
2'b11: z = a3;
endcase
endmodule

Digital Design Chapter 3 Numeric Basi

Verilog

Octal and Hexadecimal

Short-hand notations for vectors of bits

Octal (base 8)

Each group of 3 bits represented by a digit

0: 000, 1:001, 2: 010, , 7: 111
2538 = 010 101 0112
110010112 11 001 0112 = 3138

Hex (base 16)

Each group of 4 bits represented by a digit

0: 0000, , 9: 1001, A: 1010, , F: 1111
3CE16 = 0011 1100 11102
110010112 1100 10112 = CB16
Digital Design Chapter 3 Numeric Basi

Verilog

Extending Unsigned
Numbers

To extend an n-bit number to m bits

Add leading 0 bits

e.g., 7210 = 1001000 = 000001001000

x0
x1

y0
y1

xn 1

yn 1
yn
ym 2
y

wire [3:0] x;
wire [7:0] y;
assign y = {4'b0000, x};

assign y = {4'b0, x};

assign y = x;

Digital Design Chapter 3 Numeric Basi

Verilog

Truncating Unsigned
Numbers

To truncate from m bits to n bits

Discard leftmost bits

Value is preserved if discarded bits are 0
Result is x mod 2n
y0
y1

x0
x1

yn 1
yn

xn 1

assign x = y[3:0];

ym 2
ym 1

Digital Design Chapter 3 Numeric Basi

Verilog

Unsigned Addition

Performed in the same way as decimal

0 0 1 1 1 1 0 0 0 0

carry
bits

1 1 0 0 1

1 0 1 0 1 1 1 1 0 0
0 0 1 1 0 1 0 0 1 0

0 1 0 0 1
1 1 1 0 1

1 1 1 0 0 0 1 1 1 0

1 0 0 1 1 0
overflo
w

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Verilog

Addition Circuits

Half adder

for least-significant bits

s0 x0 y0
xi

yi

ci

si

ci+1

si xi yi ci

ci 1 xi yi xi yi ci

c1 x0 y0

Full adder

for remaining bits

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Verilog

Ripple-Carry Adder

Full adder for each bit, c0 = 0

xn1
c

sn

overflo
w

xi

full
adder

sn1

cn1

ci+1

yi

full
adder

x1
ci

c2

si

y1

full
adder

s1

x0
c1

y0

full
adder

c0

s0

Worst-case delay

from x0, y0 to sn
carry must ripple through intervening
stages, affecting sum bits

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Verilog

Improving Adder
Performance

Carry kill:

ki xi yi

Carry propagate: pi xi yi
Carry generate:

g i xi yi

Adder equations

si pi ci

xi

yi

ci

si

ci+1

ci 1 g i pi ci

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Verilog

Fast-Carry-Chain Adder

Also called Manchester adder

xi

yi

xi

pi

ci+1

Xilinx
FPGAs
include
this
structure

gi

ci

si

yi

pi

ki

ci+1

ci

si

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Verilog

Carry Lookahead
ci 1 g i pi ci
c1 g 0 p0 c0

c2 g1 p1 g 0 p0 c0 g1 p1 g 0 p1 p0 c0
c3 g 2 p2 g1 p2 p1 g 0 p2 p1 p0 c0
c4 g 3 p3 g 2 p3 p2 g1
p3 p2 p1 g 0 p3 p2 p1 p0 c0
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Verilog

Carry-Lookahead Adder

Avoids chained carry circuit

x3

y3

g3

p3

x2

y2

g2

p2

x1

y1

g1

p1

x0

y0

g0

c4

c0
p3

s3

p0

c3

p2

s2

c2

p1

s1

c1

p0

s0

Use multilevel lookahead for wider numbers

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Verilog

Other Optimized Adders

Other adders are based on other

reformulations of adder equations
Choice of adder depends on
constraints

e.g., ripple-carry has low area, so is

ok for low performance circuits
e.g., Manchester adder ok in FPGAs
that include carry-chain circuits

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Verilog

Adders in Verilog

Use arithmetic + operator

wire [7:0] a, b, s;
...
assign s = a + b;
wire [8:0] tmp_result;
wire
c;
...
assign tmp_result = {1'b0, a} + {1'b0, b};
assign c
= tmp_result[8];
assign s
= tmp_result[7:0];
assign {c, s} = {1'b0, a} + {1'b0, b};
assign {c, s} = a + b;

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Verilog

Unsigned Subtraction

As in decimal
b
x:
y:

1 0 1 0 0 1 1 0
0 1 0 0 1 0 1 0

d:

0 1 0 1 1 1 0 0

0 1 0 1 1 0 0 0

borro
w bits

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Verilog

Subtraction Circuits

For least-significant
bits
d 0 x0 y0
b1 x0 y0

For remaining
bits
d x y b
i

bi 1 xi yi xi yi bi

xi

yi

bi

si

bi+1

Digital Design Chapter 3 Numeric Basi

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Verilog

Adder/Subtracter Circuits

Many systems add and subtract

Trick: use complemented borrows

Addition

Subtraction

si xi yi ci

d i xi yi bi

ci 1 xi yi xi yi ci

bi 1 xi yi xi yi bi

Same hardware can perform both

For subtraction: complement y, bset

0 1
Digital Design Chapter 3 Numeric Basi

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Verilog

Adder/Subtracter Circuits
xn1

x1 x0

yn1

y1

y0

xn1 x1 x0

yn1

y1

cn

y0
c0

sn1

s1

s0

s1/d1

s0/d0

sn1/dn1

Adder can be any of those we have seen

depends on constraints
Digital Design Chapter 3 Numeric Basi

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Verilog

Subtraction in Verilog
module adder_subtracter ( output [11:0]
output
input [11:0]
input
assign {ovf_unf, s} = !mode ? (x + y)
endmodule

s,
ovf_unf,
x, y,
mode );
: (x - y);

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Verilog

Increment and Decrement

Adding 1: set y = 0 and c0 = 1

si xi ci

These are equations for a half adder

xn1
c
sn

ci 1 xi ci

cn1

half
adder

sn1

xi
ci+1

ci

half
adder

si

x1
c2

c1

x0

half
adder

half
adder

s1

s0

Similarly for decrementing: subtracting 1

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Verilog

Increment/Decrement in
Verilog

Just add or subtract 1

wire [15:0] x, s;
...

assign s = x + 1;

// increment x

assign s = x - 1;

// decrement x

Note: 1 (integer), not 1'b1 (bit)

Automatically resized

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Verilog

Equality Comparison

XNOR gate: equality of two bits

x0
y0
x1
y1
xn1
yn1

Apply bitwise to two unsigned numbers

In Verilog, x == y
gives a bit result

eq

1'b0 for false, 1'b1 for

true

assign eq = x == y;

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Verilog

Inequality Comparison

Magnitude comparator for x > y

xn1
yn1

xn1 > yn1

xn2
yn2

xn2 > yn2

gt

xn1 = yn1
xn20 > yn20

xn2 = yn2

x1
y1

x1 > y1

x0
y0

x0 > y0

x1 = y1

x10 > y10

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Verilog

Comparison Example in
Verilog

Thermostat with target termperature

Heater or cooler on when actual

temperature is more than 5 from target

module thermostat ( output

heater_on, cooler_on,
input [7:0] target, actual );
assign heater_on = actual < target - 5;
assign cooler_on = actual > target + 5;
endmodule

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Verilog

Scaling by Power of 2
x xn 1 2 n 1 xn 2 2 n 2 x0 20
2 k x xn 1 2 k n 1 xn 2 2 k n 2 x0 2 k 0 2 k 1 (0)2 0

This is x shifted left k places, with k

bits of 0 added on the right

logical shift left by k places

e.g., 000101102 23 = 000101100002

Truncate if result must fit in n bits

overflow if any truncated bit is not 0

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Verilog

Scaling by Power of 2
x xn 1 2 n 1 xn 2 2 n 2 x0 2 0
x / 2 k xn 1 2 n 1 k xn 2 2 n 2 k xk 20 xk 1 2 1 x0 2 k

This is x shifted right k places, with

k bits truncated on the right

logical shift right by k places

e.g., 011101102 / 23 = 011102

Fill on the left with k bits of 0 if

result must fit in n bits
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Verilog

Scaling in Verilog

Shift-left (<<) and shift-right (>>) operations

result is same size as operand

s = 000100112 =
1910

s = 000100112 =
1910

assign y = s << 2;

assign y = s >> 2;

y = 010011002 =
7610

y = 0001002 = 410

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Verilog

Unsigned Multiplication

xy x yn 1 2 n 1 yn 2 2 n 2 y0 20

yn 1 x 2 n 1 yn 2 x 2 n 2 y0 x 20

yi x 2i is called a partial product

if yi = 0, then yi x 2i = 0

if yi = 1, then yi x 2i is x shifted left by i

Combinational array multiplier

AND gates form partial products
adders form full product

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Verilog
xn1 xn2

Unsigned
Multiplication

cn

y0
s0

x1

x0

yn1 yn2

y1

y1

y0
c0

adder

sn1 s2 s1

xn1

y1

xn2 x1 x0

xn2

y0

c0

xn1 xn2

xn1

yn1 yn2

adder

sn1 s2 s1

xn1 xn2

s0
x1

x0

y2

x1 x0

cn

yn1 yn2

y1

sn1 s2 s1

y0
c0

adder

s0

xn1 xn2

cn
sn1
p2n2

x1 x0

s2

s1

pn+1

pn

x1

x0

yn1

p2n1

x1 x0

cn

Adders can be any of

those we have seen
Optimized multipliers
combine parts of
adjacent adders

x0

xn2

xn1

x1

yn1 yn2

y1

y0
c0

pn1

Digital Design Chapter 3 Numeric Basi

p2

p1

p0

33

Verilog

Product Size

Greatest result for n-bit operands:

(2 n 1)(2 n 1) 2 2 n 2 n 2 n 1 2 2 n 2 n 1 1

Requires 22n bits to avoid overflow

Adding n-bit and m-bit operands

requires n + m bits

wire [ 7:0] x; wire [13:0] y; wire [21:0] p;

...
assign p = {14'b0, x} * {8'b0, y};
assign p = x * y;

// implicit resizing

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Verilog

Other Unsigned
Operations

Division, remainder

More complicated than multiplication

Large circuit area, power

Complicated operations are often

performed sequentially

in a sequence of steps, one per clock

cycle
cost/performance/power trade-off
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Verilog

Gray Codes

Important for position encoders

Only one bit changes at a time

Segme
nt

Code

Segme
nt

Code

0000

1100

0001

1101

0011

10

1111

0010

11

1110

0110

12

1010

0111

13

1011

0101

14

1001

0100
15
1000
See book for n-bit Gray code

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Verilog

Signed Integers

Positive and negative numbers (and

0)
n-bit signed magnitude code

Signed-magnitude rarely used for

integers now

1 bit for sign: 0 +, 1

n 1 bits for magnitude

circuits are too complex

Use 2s-complement binary code

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Verilog

2s-Complement
Representation
x xn 1 2

x0 2

10000 = 2n1

Most-positive number

xn 2 2

n2

Most-negative number

n 1

01111 = +2n1 1

xn1 = 1 negative,
xn1 = 0 non-negative

Since 2 n 2 2 0 2 n 1 1
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Verilog

2s-Complement Examples

00110101

10110101

= 125 + 124 + 122 + 120 = 53

= 127 + 125 + 124 + 122 + 120
= 128 + 53 = 75

00000000
11111111
10000000
01111111

=
=
=
=

0
1
128
+127

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Verilog

Signed Integers in Verilog

Use signed vectors

wire signed [ 7:0] a;
reg signed [13:0] b;

Can convert between signed and

unsigned interpretations

wire
[11:0] s1;
wire signed [11:0] s2;
...
assign s2 = $signed(s1);

// s1 is known to be
// less than 2**11

...
assign s1= $unsigned(s2); // s2 is known to be nonnegative

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Verilog

Octal and Hex Signed

Integers

Dont think of signed octal or hex

E.g., 84410 is 001101001100

Just treat octal or hex as shorthand

for a vector of bits
In hex: 0011 0100 1100 34C

E.g., 4210 is 1111010110

In octal: 1 111 010 110 1726 (10

bits)
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Verilog

Resizing Signed Integers

To extend a non-negative number

Add leading 0 bits

e.g., 5310 = 00110101 = 000000110101

To truncate a non-negative number

Discard leftmost bits, provided

discarded bits are all 0

sign bit of result is 0

E.g., 4110 is 00101001

Truncating to 6 bits: 101001 error!

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Verilog

Resizing Signed Integers

To extend a negative number

Add leading 1 bits

See textbook for proof

e.g., 7510 = 10110101 =

111110110101

To truncate a negative number

Discard leftmost bits, provided

discarded bits are all 1

sign bit of result is 1

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Verilog

Resizing Signed Integers

In general, for 2s-complement integers

Extend by replicating sign bit

sign extension

Truncate by discarding leading bits

Discarded bits must all be the same, and the

same as the sign bit of the result

x0
x1

y0
y1

xn 1

yn 1
yn
ym 2
y

wire signed [ 7:0] x;

wire signed [15:0] y;
...
assign y = {{8{x[7]}}, x};
assign y = x;
...
assign x = y;

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Verilog

Signed Negation

Complement and add 1

Note thatxi 1 xi

x 1 (1 xn 1 )2 n 1 (1 xn 2 )2 n 2 (1 x0 )2 0 1
2 n 1 xn 1 2 n 1 2 n 2 xn 2 2 n 2 20 x0 2 0 1
( xn 1 2 n 1 xn 2 2 n 2 x0 2 0 )
2 n 1 (2 n 2 20 ) 1
x 2 n 1 2 n 1 x

E.g., 43 is 00101011
so 43 is 11010100 + 1 = 11010101
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Verilog

Signed Negation

What about negating 2n1?

Recall range of n-bit numbers is not

symmetric

100000 011111 + 1 = 100000

Result is 2n1!

Either check for overflow, extend by

one bit, or ensure this case cant arise

In Verilog: use operator

E.g., assign y = x;
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Verilog

Signed Addition
x xn 1 2 n 1 xn 20
x y ( xn 1 yn 1 )2

y yn 1 2 n 1 yn 20
n 1

xn 20 yn 20
yields cn1

Perform addition as for unsigned

Overflow if cn1 differs from cn

See textbook for case analysis

Can use the same circuit for signed

and unsigned addition
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Verilog

Signed Addition Examples

0 0 0 0 0 0 0 0

1 1 0 0 0 0 0 0

0 0 0 0 0 0 0 0

72:
49:

0 1 0 0 1 0 0 0
0 0 1 1 0 0 0 1

63:
32:

1 1 0 0 0 0 0 1
1 1 1 0 0 0 0 0

42:
8:

1 1 0 1 0 1 1 0
0 0 0 0 1 0 0 0

121:

0 1 1 1 1 0 0 1

95:

1 0 1 0 0 0 0 1

34:

1 1 0 1 1 1 1 0

no overflow

no overflow

0 1 0 0 1 0 0 0

72:
105:

0 1 0 0 1 0 0 0
0 1 1 0 1 0 0 1
1 0 1 1 0 0 0 1
positive overflow

no overflow

1 0 0 0 0 0 0 0

63:
96:

1 1 1 1 1 0 0 0

1 1 0 0 0 0 0 1
1 0 1 0 0 0 0 0

42:
8:

0 0 1 0 1 0 1 0
1 1 1 1 1 0 0 0

0 1 1 0 0 0 0 1

34:

0 0 1 0 0 0 1 0

negative overflow

no overflow

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Verilog

Signed Addition in Verilog

Result of + is same size as operands

wire signed [11:0] v1, v2;

wire signed [12:0] sum;
...
assign sum = {v1[11], v1} + {v2[11], v2};
...
assign sum = v1 + v2; // implicit sign extension

To check overflow, compare signs

wire signed [7:0] x, y, z;

wire
ovf;
...
assign z
= x + y;
assign ovf = ~x[7] & ~y[7] & z[7] | x[7] & y[7] & ~z[7];

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Verilog

Signed Subtraction
x y x ( y ) x y 1

Use a 2s-complement adder

Complement y and set c0 = 1

xn1

x1 x0

yn1

y1

y0

xn1 x1 x0

yn1

y1

cn
cn1

y0
c0

sn1

s1

s0

s1/d1

s0/d0

sn1/dn1

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Verilog

Other Signed Operations

Increment, decrement

Comparison

same as unsigned
=, same as unsigned
xn 1 yn 1
>, compare sign bits using

Multiplication

Complicated by the need to sign

extend partial products
Refer to Further Reading
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Verilog

Scaling Signed Integers

Multiplying by 2k

logical left shift (as for unsigned)

truncate result using 2s-complement
rules

Dividing by 2k

arithmetic right shift

discard k bits from the right, and
replicate sign bit k times on the left
e.g., s = "11110011" -- 13
shift_right(s, 2) = "11111100" -- 13 / 2 2
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Verilog

Fixed-Point Numbers

Many applications use non-integers

especially signal-processing apps

Fixed-point numbers

allow for fractional parts

represented as integers that are
implicitly scaled by a power of 2
can be unsigned or signed

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Verilog

Positional Notation

In decimal
10.2410 1101 0 100 2 10 1 4 10 2

In binary

101.012 1 2 2 0 21 1 20 0 2 1 1 2 2 5.2510

Represent as a bit vector: 10101

binary point is implicit

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Verilog

Unsigned Fixed-Point

n-bit unsigned fixed-point

m bits before and f bits after binary point

x xm 1 2 m 1 x0 2 0 x1 2 1 x f 2 f

Range: 0 to 2m 2f
Precision: 2f
m may be 0, giving fractions only

e.g., m= 2: 0.0001001101
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Verilog

Signed Fixed-Point

n-bit signed 2s-complement fixed-point

m bits before and f bits after binary point

x xm 1 2 m 1 x0 2 0 x1 2 1 x f 2 f

Range: 2m1 to 2m1 2f

Precision: 2f
E.g., 111101, signed fixed-point, m = 2

11.11012 = 2 + 1 + 0.5 + 0.25 + 0.0625

= 0.187510
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Verilog

Choosing Range and

Precision
Choice depends on application

Need to understand the numerical

behavior of computations performed

In DSP

some operations can magnify quantization

errors
fixed-point range affects dynamic range
precision affects signal-to-noise ratio

Perform simulations to evaluate effects

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Verilog

Fixed-Point in Verilog

Use vectors with implied scaling

Index range matches powers of

weights
Assume binary point between indices
0 and 1

module fixed_converter ( input

[5:-7] in,
output signed [7:-7] out );
assign out = {2'b0, in};
endmodule

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Verilog

Fixed-Point Operations

Just use integer hardware

e.g., addition:

x y (x 2 y 2 ) / 2
f

Ensure binary points

are aligned

a7
a6
a5
a4

10-bit
adder
x0

a3

x7
x8
x9

b4

y0

b3
b4
b5

y7
y8
y9

s0

Digital Design Chapter 3 Numeric Basi

c4
c3
c4
c5

59

Verilog

Floating-Point Numbers

Similar to scientific notation for decimal

e.g., 6.022141991023, 1.602176531019

Allow for larger range, with same

relative precision throughout the range
6.022141991023
mantissa

radix

exponent

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Verilog

IEEE Floating-Point Format

e bits

s exponen
t

m bits

mantissa

x M 2 (1 s ) 1.mantissa 2
E

s: sign bit (0 non-negative, 1 negative)

Normalize: 1.0 |M| < 2.0

exponent 2 e1 1

M always has a leading pre-binary-point 1 bit, so

no need to represent it explicitly (hidden bit)

Exponent: excess representation: E + 2e11

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Verilog

Floating-Point Range

Exponents 000...0 and 111...1 reserved

Smallest value

Largest value

exponent: 000...01 E = 2e1 + 2

mantissa: 0000...00 M = 1.0
exponent: 111...10 E = 2e1 1
mantissa: 111...11 M 2.0

Range:

2 e1 2

x 2

2 e1

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Verilog

Floating-Point Precision

Relative precision approximately 2

m

all mantissa bits are significant

m bits of precision

m log102 m 0.3 decimal digits

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Example Formats

IEEE single precision, 32 bits

e = 8, m = 23
range 1.2 1038 to 1.7 1038
precision 7 decimal digits

Application-specific, 22 bits

e = 5, m = 16
range 6.1 105 to 6.6 104
precision 5 decimal digits
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Denormal Numbers

Exponent = 000...0 hidden bit is 0

x M 2 (1 s ) 0.mantissa 2
E

Smaller than normal numbers

2 e1 1

allow for gradual underflow, with

diminishing precision

Mantissa = 000...0
x M 2 (1 s ) 0.0 2
E

2 e1 1

0.0

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Infinities and NaNs

Exponent = 111...1, mantissa = 000...0

Infinity
Can be used in subsequent calculations,
avoiding need for overflow check

Exponent = 111...1, mantissa 000...0

Not-a-Number (NaN)
Indicates illegal or undefined result

e.g., 0.0 / 0.0

Can be used in subsequent calculations

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Floating-Point Operations

Considerably more complicated

than integer operations

E.g., addition

unpack, align binary points, adjust

exponents
add mantissas, check for exceptions
round and normalize result, adjust
exponent

Combinational circuits not feasible

Pipelined sequential circuits

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Summary

Unsigned: x xn 1 2 n 1 xn 2 2 n 2 x0 20
Signed: x xn 1 2 n 1 xn 2 2 n 2 x0 20
Octal and Hex short-hand
Operations: resize, arithmetic,
compare
Arithmetic circuits trade off
speed/area/power
Fixed- and floating-point non-integers
Gray codes for position encoding
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