Basic Multiplier Circuit: Week 9
Basic Multiplier Circuit: Week 9
Week 9
Multiplication in Verilog
Multiplication
ab
b ab
Multiplication in Verilog
1
0
1
1
0
1
1
0
Multiplicand
Multiplier
0
1
Partial products
0
0
1
1
0
1
1
0
0
1
0
0
Product
Multiplication in Verilog
+
C3
B1
A1
B0
A0
A1B1
A0B1
A1B0
A0B0
C2
C1
C0
Multiplication in Verilog
Multiplication in Verilog
module booth_encoder(mr,md,x,z);
input[3:0] mr,md;
output [3:0] x,z;
//reg [3:0]
mr,md;
reg [3:0]
x,z;
reg [1:0]
i;
always@(mr or md)
begin
x[0]=md[0];
z[0]=md[0];
x[1]=md[1]&~md[0];
z[1]=md[1]^md[0];
x[2]=md[2]&~md[1];
z[2]=md[2]^md[1];
x[3]=md[3]&~md[2];
z[3]=md[3]^md[2];
end
endmodule // booth_encoder
Multiplication in Verilog
More on multipliers
Multiplication in Verilog
(in decimal, 3 x 2 = 6)
(in decimal, 6 2 = 3)
Multiplication in Verilog
Adder and multiplier circuits mimic human algorithms for addition and
multiplication.
Adders and multipliers are built hierarchically.
We start with half adders or full adders and work our way up.
Building these functions from scratch with truth tables and K-maps
would be pretty difficult.
The arithmetic circuits impose a limit on the number of bits that can be
added. Exceeding this limit results in overflow.
There is a tradeoff between simple but slow circuits (ripple carry
adders) and complex but fast circuits (carry lookahead adders).
Multiplication and division by powers of 2 can be handled with simple
shifting.
Multiplication in Verilog