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Electronic Test Design For Testability Standards

This document discusses electronic test and design for testability standards. It covers topics like increased complexity of integrated circuits, design for testability techniques, boundary scan testing, and standards like IEEE 1149.1 and 1500. It also describes the boundary scan environment (EBS) software and hardware that can be used to perform boundary scan testing experiments on prototype boards.

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Mohammad Johar
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101 views

Electronic Test Design For Testability Standards

This document discusses electronic test and design for testability standards. It covers topics like increased complexity of integrated circuits, design for testability techniques, boundary scan testing, and standards like IEEE 1149.1 and 1500. It also describes the boundary scan environment (EBS) software and hardware that can be used to perform boundary scan testing experiments on prototype boards.

Uploaded by

Mohammad Johar
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Electronic test

Design for Testability Standards


Part of
New Media and e-Science MSc Programme
Fall semester, 2004/2005
Franc Novak
Joef Stefan Institute
Ljubljana, Slovenia

Course contents

design automation
essential issues in synthesis
design description
high-level synthesis algorithms
electronic test and testable design

electronic test and testable design

test challenges
design-for-test
standardized solutions
experimental boundary-scan environment

increased complexity
Moors law (1965) continues to hold:
the number of transistors on a square
inch of silicon doubles every 12 months

at the late 1970s: 18 months


at 2000: 18 to 24 months
(M.L.Bushnell, V.D.Agrawal:
Essentials of Electronic Testing)

increased transistor density in comparison


with the number of pins
d

number of transistors Nt = d2
number of I/O pins Np = 4d

increase of test complexity: Nt / Np

(1997-2001) Nt / Np = 1.1 x 104


(2003-2009) Nt / Np = 2.6 x 104
(2009-2012) Nt / Np = 6.7 x 104

increased speed and ATE cost

microprocessor clock
ATE signal generation/data capture
installed ATE (typical)
current ATE cost
SIA roadmap: prices of ATE
expected ATE cost by 2010

> 1GHz
~ 1.6 GHz
100 MHz

~ 3000$ per pin


20 million $
50 million $

Design for testability (DFT)


The difficulty of testing can be qualified in terms of
cost of test development,
cost of test application,
cost (or economic consequences) of test escape.
The Rule of Ten: The cost of discovering a defective chip increases
by an order of magnitude at each successive level of integration,
from die/ package, board and system.
Design for testability is defined as changes to a given circuit or
system design that make the overall testing less difficult.

Testability measures
Controllability of a digital circuit is defined as the difficulty of
setting a particular signal of the circuit to logical 0 or 1.
Observability of a digital circuit is defined as the difficulty of
observing the state of a particular signal of the circuit.
Testability = controllability + observability
Testability analysis
involves circuit topological analysis,
does not involve test vectors,
has linear complexity.
Goldstein(1979): SCOAP Controllability and Observability

Embedded test approach

test pattern generation


result compression
test pattern generation using Linear Feedback Shift Register
(LSFR)
result compression using LSFR response compactor
(R.A.Frohwerk Signature analysis: A new digital field service method, Hewlett-Packard
Journal, 1977

test of embedded memories


Conventional ad-hoc techniques
additional logic to route the embedded memory inputs/outputs to
external pins
a scan chain around the embedded memory

Alternative way
memory BIST approach with on-chip (on-board) generation of test
patterns and compression of test results
S.K.Jain, C.E.Stroud Built-in self-testing of embedded memories, IEEE
Design & Test of Computers, 1986

problems
In-circuit test: problems in mechanical access
complex ICs with smaller pin-to-pin spacing
decreased distance between PCB interconnects
direct mounting of chips on both sides of a PCB

solution
to build the test probe directly into the silicon chip

IEEE Std 1149.1


boundary-scan principle:
a shift register boundary
cell is placed adjacent to
each component pin
boundary-scan cells are
interconnected into a shift
register

IEEE Std 1149.1


components on a board are connected via one or more serial boundaryscan lines

IEEE Std 1149.1


mandatory instructions:
external test
sample/preload
bypass

non-mandatory instructions:
intest, runbist, clamp,
idcode, usercode,etc.

IEEE Std 1149.1- extest

IEEE Std. 1149.1


More information:
1149.1-2001 Test Access Port and Boundary-Scan
Architecture (IEEE), IEEE catalog number: ST01120,
212 pages. 2001. ISBN 0-7381-2994-5
Kenneth P. Parker: The Boundary-scan Handbook,
second edition, Kluwer Academic Publishers, ISBN 07923-8277-3
Harry Bleeker, Peter van den Eijnden, Franc de Jong:
Boundary-scan Test, A Practical Approach, Kluwer
Academic Publishers, ISBN 0-7923-9296-5

IEEE Std 1149.4


can be regarded as extension of IEEE 1149.1 to mixed-signal test

IEEE Std.1149.4 (Mixed-Signal Test Bus)

Analog Boundary Module (ABM)

IEEE Std. 1149.4


This standard defines features that provide standardized approaches to:
interconnect test (testing for opens and shorts among the
interconnections in a printed circuit assembly)
parametric test (analog characterization measurements, and testing
for presence and value of discrete components in a printed circuit
assembly)
internal test (testing the internal circuitry of the mixed-signal chip)

IEEE Std.1149.4
mandatory instructions:
external test
sample/preload
bypass
(these instructions are already defined by IEEE 1149.1)
aditional mandatory instruction:
probe instruction allows analog pins to be monitored
on the analog bus and/or stimulated from the analog
bus during normal operation

IEEE Std. 1149.4


More information:
IEEE 1149.4 Mixed-Signal Test Bus Working Group:
http://grouper.ieee.org/groups/1149/4/
An overview of the standard, along with a discussion of
the architecture and how to use it :
http://grouper.ieee.org/groups/1149/4/basic_present.ppt
Adam Osseiran: Analog and Mixed-Signal BoundaryScan: A Guide to the IEEE 1149.4 Test Standard,
Kluwer Academic Publishers, 1999

System-on-chip(SOC)
pre-designed, pre-verified, reusable building blocks:
embedded cores
shortened design cycle, higher performance, lower
power consumption, smaller volume

Embedded core types


Soft core (RTL code)
Firm core (netlist)
Hard core (layout)
Intellectual Property (IP) !!!

System-on-chip(SOC) test problems


Production test of assembled boards consists of a sequence of
separate test steps: component tests, bare board test, static test
of assembled board (detecting shorts and opens) and dynamic
functional test (detecting timing faults).
In the case of testing SOC, all the above tests are merged into
one composite test instance.
Furthermore, in most cases direct access to the core terminals
is not provided which makes it difficult to run internal tests of
deeply embedded cores.

IC tester

Towards SOC test problem solution


Core provider and core user must cooperate
Standardized interface for core test knowledge
transfer
IEEE Std. 1500 Standard for Embedded Core Test

Conceptual architecture for testing


embedded-cores

wrapper interface

IEEE Std. 1500 instructions

WS_EXTEST (mandatory) allows test of external interconnections


WS_BYPASS (mandatory)

WS_INTEST_RING (optional)
WS_INTEST_SCAN (optional)
WP_INTEST_RING (optional)
WP_INTEST_SCAN (optional)
WH_INTEST (optional)

WS_PRELOAD (optional)
WP_PRELOAD (optional)
WS_CLAMP (optional)
WS_SAFE (optional)
WP_EXTEST (optional)
WH_EXTEST (optional)

these instructions perform internal test


at least one of them is mandatory

IEEE Std. 1500


More information:
IEEE P1500 Standard for Embedded Core Test (SECT)
http://grouper.ieee.org/groups/1500/
Scaleable Architecture
http://grouper.ieee.org/groups/1500/date03/ctag-date03.pdf

Available test environments


boundary-scan environment (EBS)
sequential diagnosis tool
remote access - Agilent 83000 test system

boundary-scan environment (EBS)

SN74ACT8990 boundary-scan controller

boundary-scan test example

boundary-scan test example 2

IEEE 1149.1 test programming

boundary-scan bus operations described by IEEE state diagram

SN74BCT8245A test programming

EBS software
Linux OS:
device drivers
- SN74ACT8990 boundary-scan controller,
- parallel port (in preparation)
test development tools
- Serial Vector Format (SVF) parser

Serial Vector Format

SVF is the media for exchanging descriptions of high-level IEEE Std.


1149.1 bus operations
SVF description: scan operations and movements between different
stable states of the IEEE state diagram
SVF encourages reuse and portability of serial vectors
(Texas Instruments Inc. 1994, ASSET InterTech Inc.)

Serial Vector Format commands

Serial Vector Format parser

a simple test program example

possible applications
education:
integrity test
interconnection test of a proto board, injected faults (shorts between lines,
open lines)

research projects
experimental verification of new designs including boundary-scan
IEEE Std. 1149.4 test and measurement techniques

EuNICEtest Project

European Network for Initial and Continuing Education in VLSI/SOC


Testing using remote ATE facilities

coordinator: Laboratoire dInformatique, de Robotique et de


Microlectronique de Montpellier (LIRMM)

partners: Universitat Politecnica de Catalunya, Politecnico di Torino,


University of Stuttgart, Jozef Stefan Institute, Agilent Technologies

EuNICEtest Project

Literature
General background:
Franklin P. Prosser, David E. Winkel: The art of digital design, Prenticehall int. editions, ISBN 0-13-046673-5
High-level synthesis:
Daniel Gajski, Nikil Dutt, Allen Wu, Steve Lin: High-level synthesis,
Kluwer Academic Publishers, ISBN 0-7923-9194-2
Giovanni De Micheli: Synthesis and optimization of digital circuits,
McGraw-Hill, ISBN 0-07-016333-2
Electronic test:
Michael L. Bushnell, Vishwani D. Agrawal: Essentials of Electronic
Testing, Kluwer Academic Publishers, ISBN 0-7923-7991-8

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