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Design and Implementation of A High Performance Floating

This document presents the design and implementation of a high performance floating point multiplier. It describes the floating point multiplication algorithm, the hardware blocks used including a significand multiplier, exponent adder, and sign bit calculator. It also discusses pipelining the design to improve performance. The floating point multiplier was implemented in VHDL and verified against a Xilinx core.

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Himanshu Sharma
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50 views

Design and Implementation of A High Performance Floating

This document presents the design and implementation of a high performance floating point multiplier. It describes the floating point multiplication algorithm, the hardware blocks used including a significand multiplier, exponent adder, and sign bit calculator. It also discusses pipelining the design to improve performance. The floating point multiplier was implemented in VHDL and verified against a Xilinx core.

Uploaded by

Himanshu Sharma
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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DESIGN AND IMPLEMENTATION OF A HIGH

PERFORMANCE FLOATING POINT


MULTIPLIER





A PRESENTATION


Submitted by

HIMANSHU SHARMA


In Partial Fulfillment of the Requirements
for the Degree of

MASTERS OF TECHNOLOGY



DEPARTMENT OF ECE FACULTY OF
ENGINEERING AND TECHNOLOGY SRM
UNIVERSITY, MODINAGAR




NOVEMBER 2013

INTRODUCTION
This paper presents an area efficient
implementation of an IEEE 754 single
precision floating point multiplier.
VHDL is used to implement a pipelined design
Multiplier handles the cases of underflow and
over flow.
Multiplier was verified against Xilinx Floating
point multiplier core.


Floating point multiplication
Floating point numbers represent real
numbers in binary format.
normalized floating point numbers have the
form of Z= (-1S) * 2 (E - Bias) * (1.M).
FLOATING POINT MULTIPLICATION
ALGORITHM
Multiplying the significand; i.e. (1.M1*1.M2)
Placing the decimal point in the result
Adding the exponents; i.e. (E1 + E2 Bias)
Obtaining the sign; i.e. s1 xor s2
Normalizing the result; i.e. obtaining 1 at the
MSB of
the results significand
Rounding the result to fit in the available bits
Checking for underflow/overflow occurrence
Process
Consider a floating point representation similar to the IEEE 754 single precision floating point format, but
with a reduced number of mantissa bits (only 4) while still retaining the hidden 1 bit for normalized
numbers A = 0 10000100 0100 = 40, B = 1 10000001 1110 = -7.5.
1 )To multiply A and B
1.0100
1.1110
00000
10100
10100
10100
10100
1001011000

2.)Place the decimal point: 10.01011000
3) Add exponents: 10000100
+ 10000001
100000101
100000101


The exponent representing the two numbers is already
shifted/biased by the bias value (127) and is not the true
exponent; i.e. EA = EA-true + bias and EB = EB-true + bias
And
EA + EB = EA-true + EB-true + 2 bias
So we should subtract the bias from the resultant exponent
otherwise the bias will be added twice.
100000101

Floating point multiplier block diagram
HARDWARE OF FLOATING POINT
MULTIPLIER
A. Sign bit calculation
Multiplying two numbers results in a negative sign
number if one of the multiplied numbers is of a
negative value. By the aid of a truth table we find that
this can be obtained by XORing the sign of two inputs.
B. Unsigned Adder (for exponent addition)
This unsigned adder is responsible for adding the
exponent of the first input to the exponent of the
second input and
subtracting the Bias (127) from the addition result
(i.e.A_exponent + B_exponent - Bias).
Ripple Carry Adder
Ripple Borrow Subtractor
C. Unsigned Multiplier (for significand
multiplication

Carry save multiplier has three main stages:
1- The first stage is an array of half adders.
2- The middle stages are arrays of full adders. The
number of middle stages is equal to the significand
size minus two.
3- The last stage is an array of ripple carry adders. This
stage is called the vector merging stage
V. PIPELINING THE MULTIPLIER
In order to enhance the performance of the multiplier, three
pipelining stages are used to divide the critical path thus
increasing the maximum operating frequency of the multiplier.
The pipelining stages are imbedded at the following locations:
1. In the middle of the significand multiplier, and in the
middle of the exponent adder (before the bias
subtraction).
2. After the significand multiplier, and after the
exponent adder.
3. At the floating point multiplier outputs (sign,
exponent and mantissa bits).
Floating point multiplier with pipelined
stages
REFERENCES
[1] IEEE 754-2008, IEEE Standard for Floating-Point Arithmetic, 2008.
[2] B. Fagin and C. Renard, Field Programmable Gate Arrays and Floating
Point Arithmetic, IEEE Transactions on VLSI, vol. 2, no. 3, pp. 365
367, 1994.
[3] N. Shirazi, A. Walters, and P. Athanas, Quantitative Analysis of
Floating Point Arithmetic on FPGA Based Custom Computing
Machines, Proceedings of the IEEE Symposium on FPGAs for Custom
Computing Machines (FCCM95), pp.155162, 1995.
[4] L. Louca, T. A. Cook, and W. H. Johnson, Implementation of IEEE
Single Precision Floating Point Addition and Multiplication on FPGAs,
Proceedings of 83 the IEEE Symposium on FPGAs for Custom
Computing Machines (FCCM96), pp. 107116, 1996.
[5] A. Jaenicke and W. Luk, "Parameterized Floating-Point
Arithmetic on FPGAs", Proc. of IEEE ICASSP, 2001, vol. 2, pp.
897-900.
*6+ B. Lee and N. Burgess, Parameterisable Floating-point Operations on
FPGA, Conference Record of the Thirty-Sixth Asilomar Conference on
Signals, Systems, and Computers, 2002
*7+ DesignChecker User Guide, HDL Designer Series 2010.2a, Mentor
Graphics, 2010
*8+ PrecisionR Synthesis Users Manual, Precision RTL plus 2010a
update 2, Mentor Graphics, 2010.
[9] Patterson, D. & Hennessy, J. (2005), Computer Organization and
Design: The Hardware/software Interface , Morgan Kaufmann .
[10] John G. Proakis and Dimitris G. Manolakis (1996), Digital Signal
Processing: Principles,. Algorithms and Applications, Third Edition.

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