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Digital Signal Processors

This document summarizes a technical seminar presented by Binay Kumar Mishra on the TMS320C6211 and Micro-50 EB digital signal processors. It provides an outline that introduces the TMS320C6211 DSP, Micro-50 EB, C-50 debugger, and Code Composer Studio V2 software. It then goes into further detail on the architecture and instruction set of the TMS320C6211, the features of the Micro-50 EB and C-50 debugger, and how to use Code Composer Studio V2 to write and run code for the DSP processors. It also provides an example problem solved using Code Composer Studio V2.

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chikulenka
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176 views

Digital Signal Processors

This document summarizes a technical seminar presented by Binay Kumar Mishra on the TMS320C6211 and Micro-50 EB digital signal processors. It provides an outline that introduces the TMS320C6211 DSP, Micro-50 EB, C-50 debugger, and Code Composer Studio V2 software. It then goes into further detail on the architecture and instruction set of the TMS320C6211, the features of the Micro-50 EB and C-50 debugger, and how to use Code Composer Studio V2 to write and run code for the DSP processors. It also provides an example problem solved using Code Composer Studio V2.

Uploaded by

chikulenka
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as PPT, PDF, TXT or read online on Scribd
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TECHNICAL SEMINAR 2004-05

TMS320C6211 AND MICRO-50 EB


DIGITAL SIGNAL PROCESSORS

PRESENTED BY

BINAY KUMAR MISHRA


ROLL # EI200117049

UNDER THE GUIDANCE OF

DR. SAROJ KUMAR MEHER

BINAY KUMAR MISHRA 1


TECHNICAL SEMINAR 2004-05

OUTLINE
TMS320C6211 DIGITAL SIGNAL
PROCESSOR
MICRO-50 EB
C-50 DEBUGGER
CODE COMPOSER STUDIO V2

BINAY KUMAR MISHRA 2


TECHNICAL SEMINAR 2004-05

C6X SYSTEM BLOCK


DIAGRAM
Memory ASIC with
P Programmable
External
Internal Buses E Digital Signal Core
Memory R
I RAM
P
H ROM
CPU E Standard Cells
R
A Codec
L
S Peripherals

BINAY KUMAR MISHRA 3


TECHNICAL SEMINAR 2004-05

TMS320C6211 INSTRUCTION
SET
ARITHMETIC LOGICAL
ADD AND
ADDA NOT
SUB OR
NEG XOR
MPY COMPLT
SUB CLR
SUBA SET

BINAY KUMAR MISHRA 4


TECHNICAL SEMINAR 2004-05

MICRO-50 EB
 DSP processor incorporated by Texas
Instruments.
 Architecture similar to that of the C6x
processors.
 No in-built memory.
 No external peripherals can be connected to
provide external memory.

BINAY KUMAR MISHRA 5


TECHNICAL SEMINAR 2004-05

C-50 DEBUGGER

Software used to program Micro-50 EB,


when the kit is in serial mode.
Supports ASM and ASC file format.
The two modes in which Micro-50 EB
works is Standalone Mode and Serial Mode.

BINAY KUMAR MISHRA 6


TECHNICAL SEMINAR 2004-05

PROGRAM FLOW
C-50 debugger only supports assembly level
language programming.
The biggest demerit of this software is that it is not
code compatible with other middle level languages
like “C”.
This software is analogous to the PSPICE
software which can give only the functional
simulation but not the timing simulation.

BINAY KUMAR MISHRA 7


TECHNICAL SEMINAR 2004-05

PROGRAM FLOW

BINAY KUMAR MISHRA 8


TECHNICAL SEMINAR 2004-05

CODE COMPOSER STUDIO V2


Software used to program the TMS320C6211 DSP
Processor.
Supports C, C++, Assembly Language concept of
programming.
The data stored in the processor is temporary and
the software can be used again and again to re-
program the processor.

BINAY KUMAR MISHRA 9


TECHNICAL SEMINAR 2004-05

PROGRAM FLOW

BINAY KUMAR MISHRA 10


TECHNICAL SEMINAR 2004-05

A PROBLEM AND ITS


SOLUTION USING CCSV2
Let a problem be considered which involves both
multiplication and addition and which is of the form:

How the TIC6x is designed to handle this problem?

BINAY KUMAR MISHRA 11


TECHNICAL SEMINAR 2004-05

CONCEPT BEHIND
DEVELOPING THE CODE FOR
CCSV2
 The concept of pointers is used to develop
the code.
 An & operator is used to create a pointer to
the values.
 An * operator is used to load/store the
values using the LDH and STH commands.

BINAY KUMAR MISHRA 12


TECHNICAL SEMINAR 2004-05

DEVELOPING THE CODE


MVK 40, A2 ; A2 = 40, loop count
loop:
LDH *A5, A0 ; A0 = a(n)
LDH *A6, A1 ; A1 = x(n)
MPY A0, A1, A3 ; A3 = a(n) * x(n)
ADD A3, A4, A4 ; Y = Y + A3
SUB A2, 1, A2 ; decrement loop count
[A2] B loop ; if A2 ≠ 0, branch
STH A4, *A7 ; *A7 = Y

BINAY KUMAR MISHRA 13


TECHNICAL SEMINAR 2004-05

CONCLUSION
 This software tool is not only compatible to
design and simulate TMS320C6211 but
also other VLIW machines with minor
changes in the infrastructure.
 This tool shall make design and simulation
of future mobile devices easier and usher in
a new era of design and simulation.

BINAY KUMAR MISHRA 14

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