MEMORY AND PROGRAMMABLE LOGIC

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UNIT V
RAM and ROM
Memory Decoding
Error Detection and Correction
Programmable Logic Array
Programmable Array Logic
Sequential Programmable Devices
Application Specific Integrated Circuits.
Programmable Logic Device (PLD)
A combinational PLD is an integrated circuit with
programmable gates divided into an AND array
and an OR array to provide an AND-OR sum of
product implementation
PROM: fixed AND array constructed as a decoder
and programmable OR array.
PAL: programmable AND array and fixed OR
array.
PLA: both the AND and OR arrays can be
programmed.
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Programmable Logic Device (PLD)
PROM


PAL


PLA
Fixed
AND array
(Decoder)
Programmable
OR array
Inputs Outputs
Programmable
AND array
Fixed
OR array
Inputs Outputs
Programmable
AND array
Programmable
OR array
Inputs Outputs
Design a combinational circuit using a ROM. The
circuit accepts a three-bit number and outputs a
binary number equal to the square of the input
number.
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4
Programmable Logic Array (PLA)
5
The PLA is similar in concept to the PROM, except that the PLA
does not provide fully decoding of the variables and does not
generate all the minterms.
the decoder in PROM is replaced by an array of AND gates
that can be programmed to generate any product term of
the input variables.
The product terms are then connected to OR gates to
provide the sum of products for the required Boolean
functions.
The output is inverted when the XOR input is connected to
1 (since x1 = x). The output doesnt change and connect
to 0 (since x0 = x).
Programming Table
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1. First: lists the product terms numerically
2. Second: specifies the required paths between
inputs and AND gates
3. Third: specifies the paths between the AND and
OR gates
4. For each output variable, we may have a T(ture)
or C(complement) for programming the XOR gate
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Careful investigation must be undertaken in order
to reduce the number of distinct product terms,
PLA has a finite number of AND gates.
Both the true and complement of each function
should be simplified to see which one can be
expressed with fewer product terms and which one
provides product terms that are common to other
functions.
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Example 1
I
1
I
2
I
3
0
1
F
1
F
2
Example:
F
1
= AB + AC + ABC
F
2
= (AC + BC)
A
B
C
Example 2
9
Implement the following two Boolean functions with a PLA:
F
1
(A, B, C) = (0, 1, 2, 4)
F
2
(A, B, C) = (0, 5, 6, 7)

The two functions are simplified in the maps
1 elements
0 elements
Cont..,
10
Both the true and complement
of the functions are simplified in
sum of products.
We can find the same terms
from the group terms of the
functions of F
1
, F
1
,F
2
and F
2

which will make the minimum
terms.

F1 = (AB + AC + BC)
F2 = AB + AC + ABC
Cont..,
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AB
AC
BC
ABC
Example 3
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Example 4
Design Example
F1 = A B C

F2 = A + B + C

F3 = A B C

F4 = A + B + C

F5 = A B C

F6 = A B C
Multiple functions of A, B, C
ABC
A
B
C
A
B
C
ABC
ABC
ABC
ABC
ABC
ABC
ABC
F1 F2 F3 F4 F5 F6
A B C
Programmable Array Logic (PAL)
The PAL is a programmable logic device with a fixed
OR array and a programmable AND array.
When designing with a PAL, the Boolean functions
must be simplified to fit into each section.
Unlike the PLA, a product term cannot be shared
among two or more OR gates. Therefore, each
function can be simplified by itself without regard to
common product terms.
The output terminals are sometimes driven by three-
state buffers or inverters.


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Example 1
15
Example 2
Sometimes the outputs are fed back internally and can
be used to create product terms.

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Example 3
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w(A, B, C, D) = (2, 12, 13)
x(A, B, C, D) = (7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = (1, 2, 8, 12, 13)

Simplifying the four functions as following Boolean functions:

w = ABC + ABCD
x = A + BCD
y = AB + CD + BD
z = ABC + ABCD + ACD + ABCD = w + ACD + ABCD
Cont..,
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z has four product terms, and we can replace by w with two
product terms, this will reduce the number of terms for z from
four to three.
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Cont..,
Example
w(A,B,C,D) = (2,12,13)
x(A,B,C,D) = (7,8,9,10,11,12,13,14,15)
y(A,B,C,D) = (0,2,3,4,5,6,7,8,10,11,15)
z(A,B,C,D) = (1,2,8,12,13)
Simplify:
w = ABC + ABCD
x = A + BCD
y = AB + CD + BD
z = ABC + ABCD + ACD + ABCD
= w + ACD + ABCD
F
1
I
1
F
2
I
2
F
3
I
3
F
4
I
4
1
2
3
4
5
6
7
8
9
10
11
12
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10
w
x
y
z
A
B
C
D
Example 4
Design Example: BCD to Gray Code Converter
Truth Table
K-maps
Minimized Functions:
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
AB
CD
00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
K-map for W
AB
CD
00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
K-map for X
AB
CD
00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
K-map for Y
AB
CD
00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
K-map for Z
W = A + B D + B C
X = B C
Y = B + C
Z = A B C D + B C D + A D + B C D
Cont..,
Programmed PAL:
4 product terms per each OR gate
Minimized Functions:
W = A + B D + B C
X = B C
Y = B + C
Z = A B C D + B C D + A D + B C D
A B C D
A B C D
A
BD
BC
0
0
0
0
B
C
0
0
BC
BCD
AD
BCD
W X Y Z
PALs and PLAs
Of the two organizations the PLA is the most
flexible
One PLA can implement a huge range of logic functions
BUT many pins; large package, higher cost
PALs are more restricted / you trade number of
OR terms vs number of outputs
Many device variations needed
Each device is cheaper than a PLA

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Homework
1) Draw a PLA circuit to implement the functions
F1=AB+AC+ABC
F2=(AB+BC+AC)
2) List the PLA programming table for the BCD-
excess-3 code converter
3) Derive the PLA programing table for the
combinational circuit that squares a three bit
number . Minimize the number of product terms.
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Homework
4. Tabulate the truth table for an 8 4 ROM that
implements the Boolean functions
A(x,y,z) = (1,2,4,6)
B(x,y,z) = (0,1,6,7)
C(x,y,z) = (2,6)
D(x,y,z) = (1,2,3,5,7)