Bluespec SystemVerilog Training Lecture 01: Introduction

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Lecture 01: Introduction

Prerequisites for this training The Bluespec viewpoint on H !s How will you "enefit "y using Bluespec# $ si%ple e&a%ple' to give you the flavor of the language (&pectations) what you will learn in this training' an* what will require further practice an* $*vance* Training Broa*+"rush co%parison with ,T!' -yste%.erilog' -yste%C
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Prerequisites
Basic *igital *esign (&posure to "asic %icroarchitectures) pipelining' 0-1s' *ata an* control paths' 2 one so%e co*ing in ,T! 3.erilog or .H !4 one so%e verification of ,T! $ware of typical flow) architecture e&ploration' *esign' verification' physical *esign 5ot assu%ing any prior e&posure to -yste%.erilog
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The Bluespec vie point on !"Ls

We each observe the plaza of life from a particular balcony.
3paraphrasing ;%"erto (co fro% a Boston ra*io interview4

$rchitecture e&ploration an* verification are not in*epen*ent of the H !) a "etter H ! will spee* those activities

7The .erification pro"le% is a esign pro"le%8 9ith powerful a"straction %echanis%s' a single H ! can "e use* for "oth arch. e&ploration as well as for *esign

7Change is the only constant8) an H ! %ust acco%%o*ate ro"ust' su"stantial change

(lse' can only *o local twea:s safely 3su"+opti%al4

$"straction is goo*' provi*e* it *oes not negatively i%pact H9 3quality' visi"ility' pre*icta"ility' controlla"ility4
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The Bluespec vie point on !"Ls

escri"e H9 in the %ost natural way possi"le

o not try to force+fit' into an H !' constructs that %ay "e fine for tra*itional -9 co%puting "ut inappropriate for H9 *escription 0reely e&ploit a"straction %echanis%s that %ay have "een *evelope* in the -9 space "ut are perfectly applica"le to H9 *escription

-i%ulation is the servant of natural+an*+intuitive H9 *escription' not the other way aroun*

on<t let si%ulation consi*erations *istort the way an H ! *escri"es H9

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!o

ill you #ene$it #y using Bluespec%

$ 2& i%prove%ent 3often %ore4 in overall pro*uctivity' co%pare* to using ,T!

Particularly in *esigns with co%ple& concurrent control

esign closer to specification Co%pati"le with current %etho*ologies Can :eep up with changing specifications (na"les architectural e&ploration

%ultiple a"straction levels' refine%ent

,e*uces "ugs an* therefore verification ti%e -i%plifies verification an* *e"ugging (ases changes for ti%ing closure (ases changes for physical *esign Pro%otes reuse
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& $e

small e'amples( $or $lavor

)hat $ollo s are a $e small e'amples to illustrate hat is possi#le in BSV Please hold o$$ on detailed technical questions until later* don+t orry i$ these are not $ully understanda#le no

This is ,ust the -overture music.( to #athe you in the leitmoti$s( the idioms( the themes( as you settle com$orta#ly into your seats leaving #ehind the stresses o$ the street The plot o$ the opera ill #e revealed to you as e progress through the tutorial/

Patience: the soprano

ill sing* Baron Scarpia

ill die/
>

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0ultiplier 1'ample
-i%ple "inary %ultiplication)
@00@ AA * B 6<*C 0@0@ AA r B 6<*5 @00@ AA * DD 0 3since rE0F BB @4 0000 AA 0 DD @ 3since rE@F BB 04 @00@ AA * DD 2 3since rE2F BB @4 AA 0 DD / 3since rE/F BB 04 0000 0@0@@0@ AA pro*uct 3su% of a"ove4 B 65 &

9hat *oes it loo: li:e in Bluespec#

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0ultiplier 1'ample
%o*ule %:Test 34H ,egI3int4 state D+ %:,eg304H 1ultGifc % D+ %:1ult@34H rule go 3state BB 04H %.start 3C' 54H state DB @H en*rule rule finish 3state BB @4H J*isplay 37Pro*uct B K*8'%.result344H state DB 2H en*rule en*%o*ule) %:Test interface 1ultGifcH %etho* $ction start 3Tin &' Tin y4H %etho* Tout result 34H en*interface) 1ultGifc %o*ule %:1ult@ 31ultGifc4H ,egI3Tout4 pro*uct D+ %:,eg304H ,egI3Tout4 * D+ %:,eg304H ,egI3Tin4 r D+ %:,eg304H rule cycle 3r LB 04H if 3rE0F BB @4 pro*uct DB pro*uct M *H * DB * DD @H r DB r NN @H en*rule %etho* $ction start 3&'y4 if 3r BB 04H * DB &H r DB yH en*%etho* %etho* result 34 if 3r BB 04H return pro*uctH en*%etho* en*%o*ule) %:1ult@
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2oncurrency and Shared 3esources

cond0 cond2
51 61

1
cond1

51

61

Priority: 2 > 1 > 0

'

Process 0 incre%ents register x un*er so%e con*ition cond0 Process @ transfers a unit fro% register x to register y un*er cond1 Process 2 *ecre%ents register y un*er so%e con*ition cond2 (ach register can only "e up*ate* "y one process on each cloc:.

Priority) 2 N @ N 0

This is an a"straction of so%e real applications) Ban: account) 0B*eposit' @Btransfer to savings' 2 B with*raw fro% savings Pac:et processor) 0 B pac:et arrives' @ B pac:et is processe*' 2 B pac:et *eparts 2

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2oncurrency and Shared 3esources 7Verilog8

cond0 cond2
51 61

1
cond1

51

61

Priority: 2 > 1 > 0

'

y
if ((!cond1 || cond2) && cond0)

always O3pose*ge C!P4 AA process 0 if 3Lcon*@ QQ con*04 & DB & M @H always O3pose*ge C!P4 AA process @ if 3Lcon*2 QQ con*@4 "egin y DB y M @H & DB & R @H &peration'centric en* (not synthesizable) always O3pose*ge C!P4 AA process 2 if 3con*24 y DB y R @H

always O3pose*ge C!P4 "egin if 3Lcon*2 QQ con*@4 & DB & R @H else if 3con*04 & DB & M @H if 3con*24 y DB y R @H else if 3con*@4 y DB y M @H en*

*tate'centric (further from spec$ but synthesizable) Is it o"vious that con*itions for &+@ an* yM@ are i*entical#

Which of these solutions are correct, if any? Whats required to verify that theyre correct What if another priority is required ! cond1 " cond2 " cond0 #nd$ %hat if the processes are in different modules
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@@

2oncurrency and Shared 3esources 7V!"L8

cond0 cond2
51 61

1
cond1

51

61

Priority: 2 > 1 > 0

'

y
if (((not cond1) or cond2) && cond0) then

process3C!P4 "egin AA process 0 if 3C!P B S@< an* C!P<event4 then if 33not con*@4 an* con*04 then & DB & M @H en* ifH en* ifH en*processH process3C!P4 "egin AA process @ if 3C!P B S@< an* C!P<event4 then if 33not con*24 an* con*@4 then & DB & R @H y DB y M @H en* ifH en* ifH en*processH process3C!P4 "egin AA process 2 if 3C!P B S@< an* C!P<event4 then if 3con*24 then y DB y + @H en* ifH en* ifH en*processH

process3C!P4 "egin if 3C!P B S@< an* C!P<event4 then if 3con*2 an* con*@4 & DB & R @H else if 3con*04 then & DB & M @H en* ifH if 3con*24 then y DB y R @H else if 3con*@4 then y DB y M @H en* ifH en* ifH en* processH

@2

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)ith Bluespec SystemVerilogT0 3ules the design is sa$e and direct

cond0 cond2

51

61

51

61

Process priority: 2 > 1 > 0

'

cond1

3T *escen*ingGurgency B 7proc2' proc@' proc08 T4 rule proc0 3con*04H & DB & M @H en*rule rule proc@ 3con*@4H y DB y M @H & DB & R @H en*rule rule proc2 3con*24H y DB y R @H en*rule

+unctional correctness follo%s directly from rule semantics ,elated actions are -rouped naturally %ith their conditions.easy to chan-e /nteractions bet%een rules are mana-ed by the compiler (schedulin-$ muxin-$ control) *ame hard%are as the 0erilo- 1 0234 ,54
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1'ample: a #utter$ly s itch 7cross#ar8

00 0@

@0 @@

Basic "uil*ing "loc:s) ,ecursive construction) @&@ 2&2 6&6 2 5&5

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@6

Butter$ly s itch: inter$ace

interface XBar #(type t); interface List#(P t#(t)) interface List#("et#(t)) endinterface

inp t!ports; o tp t!ports;

Polymorphic 7type parameter t8 Su#6inter$aces 7hierarchical8 &ggregation 7lists( vectors o$ inter$aces8

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@5

Butter$ly s itch: module header

#od $e #%XBar #(&nte'er $o'n( f nction Bit #(*2) destination+f (t ,)( #od $e #(-er'e2,1 #(t)) #%-er'e2,1) (XBar #(t)) . . end#od $e: #%XBar )) )) )) )) para# 1 para# 2 para# * interface

Si9e parameter: logn 2om#: circuit parameter: destinationOf 0odule parameter: mkMerge2x1

1ncapsulates $lo 6control( ar#itration( queueing #ehavior o$ the 4'1 merge

Inter$aces instead o$ port lists: XBar#(t) Polymorphic: type parameter t

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@=

Butter$ly s itch: module #ody

#od $e #%XBar #(&nte'er $o'n( .) if ($o'n // 0) . )) B012 3012 4&4+#(t) f 56 #%4&4+; . e$se . )) 723871&92 3012 XBar#(t) pper 56 #%XBar ($o'n61( .); XBar#(t) $o:er 56 #%XBar ($o'n61( .); . for (&nte'er ; / 0; ; 5 n; ; / ; < 1) . r $e ro te; . if (! f$ip) #er'es =;> ?iport0?p t (,); e$se #er'es =;4$ipped>?iport1?p t (,); endr $e end#od $e: #%XBar

&r#itrary ela#oration

&ll constructs( including #ehavior( can #e ela#orated

7here: conditional( recursion( loop8

7$irst class modules( inter$aces( rules( ;8

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@>

Butter$ly s itch
-u%%ary) + $*vance* para%eteriUation + $*vance* ela"oration + The switch itself) D =0 lines of B-. co*e + 0irst wor:ing 3teste*4 prototype) D @ *ay 3inclu*ing si%ple test"ench4 + 0ully synthesiUa"le) + synthesiUe* to netlist 31ag%a' ts%c0.@?u' 500 1HU4
7 hitepaper availa#le ith $ull code and commentary8
@?

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Bluespec SystemVerilog & one slide overvie

Bluespec -yste%.erilog

Rules and Rule-based Interfaces 0or co%ple& concurrency an* control' across %ultiple share* resources' across %o*ule "oun*aries

High-level abstract types Powerful static checking Powerful parameterization Powerful static elaboration Advanced clock management

6ehavioral

Two dimensions raising the level of abstraction (fully synthesizable)

.H !A.erilogA-yste%.erilogA-yste%C
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*tructural

@C

Broad6#rush di$$erences #et een BSV and 3TL and System2: "escri#ing #ehavior

!o

#ehavior is descri#ed:

3TL and System2 use S)6li<e process notation: Processes are synchroni9ed using S)6li<e events BSV uses 3ules: guarded atomic state transitions: Synchroni9ation is implicit in atomic semantics: Sequential #ehaviors are #uilt #y composing 3ules( ritten manually or generated automatically

BSV: pure digital a#straction: no concept o$ intra6cloc< events( delays( etc:

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Broad6#rush di$$erences #et een BSV and 3TL and System2: =peration6centric vs: State6centric Speci$ications are usually operation6centric 7state transitions8:

->nder condition c1( change s1,s2 in the $ollo ing under c2, change s1,s3 in the $ollo ing ay.

ay*

Synthesi9a#le 3TL transposes this to #e state6centric:

-i$6then6else descri#ing all updates to s1 i$6then6else descri#ing all updates to s2 i$6then6else descri#ing all updates to s3.

BSV: Rules remain operation6centric( remaining closer to the spec and easier to maintain correctly
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Broad6#rush di$$erences #et een BSV and 3TL and System2: BSV is not simulation6centric
3TL and System2 are simulation6centric -Synthesi9a#le su#sets. ere de$ined later 0any concepts?constructs are a consequence o$ this S)6process6 li<e simulation vie : 1:g:(

1'ecution o$ a process has a program6counter6li<e -locus o$ control. Varia#les have the semantics o$ updata#le memory locations( updated hen -e'ecution reaches this statement. Sensitivity lists -I$ e'ecution reaches this statement( the ire is driven ith the value o$ the right6hand side. @unctions?procedures get called( e'ecute( and return 7stac< li<e semantics8

Aone o$ these are particularly meaning$ul $rom a !) point o$ vie : the tail 7simulation8 is agging the dog 7!) description8 BSV is not simulation6centric( and in these respects( BSV is closer to traditional !) vie
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Broad6#rush di$$erences #et een BSV and 3TL and System2: &re sequential processes a good starting point% People o$ten say: -I+m descri#ing the algorithm o$ my !) #loc< using 2?255 or Behavioral 3TL. &ctually( they+re descri#ing the function( not the algorithm & function spec o$ I?= #ehavior( ithout consideration $or implementa#ility( and in particular ithout consideration $or cost in space 7circuitry8 or time 7per$ormance8 &n algorithm a speci$ic implementation !ith a "articular cost model

"i$$erent computation models( ith di$$erent cost models( usually require radically di$$erent algorithms $or implementing the same $unction
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Broad6#rush di$$erences #et een BSV and 3TL and System2: &re sequential processes a good starting point%

Thus( sequential speci$ications 7e:g:( 2?2558( hile $ine $or descri#ing desired $unctionality( are usually not a good starting point $or descri#ing desired microarchitectures? algorithms In BSV( you thin< directly and constantly in parallel (Rules), $rom a#stract models to implementations
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Broad6#rush di$$erences #et een BSV and 3TL and System2: In$luences and inspirations

BSV shares SystemVerilog notation ma<es sense 7the ma,ority o$ BSV8

herever it

Identi$iers( constants( operators( e'pressions( comments( types( modules( inter$aces( instantiation( parameteri9ation( varia#le declaration( assignments( conditionals( loops( $unctions

BSV departs $rom SystemVerilog notation in ,ust those places here it ma<es sense:

1'press #ehavior using Rules and Rule#$ased %nterface Methods 7instead o$ processes?events8 0ore general parameteri9ation
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Broad6#rush di$$erences #et een BSV and 3TL and System2: 0odule hierarchy BSV has e'actly the same notion o$ module hierarchy as 3TL

In $act( more stringently so: e&en registers are modules 7at the leaves o$ the hierarchy8: In BSV( ordinary varia#les ne&er represent registers: Thus( designers e'ercise precise control over microarchitecture -I$ so( ho

can BSV #e a high6level !"L%.

0icroarchitecture is the creative 7and $un8 part o$ !) design* it distinguishes good designs $rom #ad: The designer should remain involved in this: 2omple' concurrency and control is the hard and tedious part o$ !) design* it+s here most errors arise: BSV+s Rules dramatically simpli$y and automate this:
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Broad6#rush di$$erences #et een BSV and 3TL and System2: "atapaths and control paths

)ith BSV you don+t thin< separately a#out datapaths and control 1ach Rule speci$ies the part o$ the datapath relevant $or its #ehavior( and the control conditions under hich the path is traversed The Bluespec compiler com$ines these speci$ications to generate the $inal datapaths and control circuitry

Ao central datapath description Ao central -control @S0.

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Broad6#rush di$$erences #et een BSV and 3TL and System2: Inter$ace #ehavior In 3TL and synthesi9a#le System2( inter$aces are merely port lists

Behavior speci$ied in ad hoc accompanying te't and?or timing diagrams In$le'i#le( tedious( source o$ many errors

In BSV( inter$aces contain -transactions.: Rule#$ased %nterface Methods

Broups o$ ports capturing a complete microprotocol( involving signals in #oth directions BSV also $ormali9es scheduling constraints across inter$ace transactions:

1:g:( -2annot insert and delete $rom ta#le in same cloc<.

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Broad6#rush di$$erences #et een BSV and 3TL and System2: @unctional vs: Per$ormance 2orrectness BSV+s Rule semantics provides a $ollo ing:

ay to separate the

@unctional correctness 7-is the result value correct%.8 Per$ormance correctness 7-is the result produced quic<ly%.8

@actori9es veri$ication into separately managea#le su#6 pro#lems Rule semantics provide a #asis to systematically alter the implementation $or $aster per$ormance ithout #rea<ing $unctional correctness 7re$inement8

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Broad6#rush di$$erences #et een BSV and 3TL and System2: Integrating Behavior and Static 1la#oration &ll !"Ls have some -punning. to descri#e static ela#oration and #ehavior: 1:g:(

& loop can #e used to statically e'press a linear repeated hard are structure 7-generate.8 & loop can #e used to e'press iterative #ehavior

In 3TL( -generate. notation is use

ea< and a < ard to

In BSV( the static ela#oration language is very po er$ul 7Turing complete8( ith assignments( conditionals( loops( $unctions( recursion( etc:( and integrated cleanly and smoothly
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Setting your e'pectations a#out hat you ill learn $rom a $e days o$ training
7arn your 8h.3. from home in 9ust : months; <all toll'free no%;
3spa% 4

1apping an i*ea or specification into B-. har*ware' an* using a"straction well' ta:es training an* practice) one can<t "eco%e an e&pert overnightL However' even after these few *ays of training' you will "e a"le to *esign using B-.' an* still e&pect at least a 2& i%prove%ent in your pro*uctivity

The "asics are easyL (ven easier than .erilogA.H !' we "elieve' "ecause of the *irect' natural way to *escri"e H9 that is H9+centric an* not si%ulation+ centric (&perience in previous training sessions has "orne this out ti%e an* againL 7$haL I get it nowL 9owL 9hy woul* I ever go "ac: to ,T!#8
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/@

Bluespec @lo
Bluespec SystemVerilog source
T0

Bluespec Synthesis Bluevie Verilog CD 3TL Bluesim

2ycle &ccurate

=ther Verilog?V!"L

Verilog sim

3TL synthesis

V2" output
(egend files Blues"ec tools 3rd "art' tools

gates

Visuali9ation 7e:g:( "e#ussy8

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/2

Bluespec is applica#le #roadly across So2 IPs

RI !" processor #IP Itanium PowerP!

I'!#otion compensator '.

Bluespec is the only (-! solution that a**resses Control' Co%ple& atapaths an* $lgorith%s

$% cache ctlr

RA# ctlr

&us converters A#&A '#A ctlr

(etwork proc )ueuing engines orting *ueue Arbiter IP lookup 'ebug controller

Co%ple& Co%ple& atapaths atapaths 3e.g. 3e.g. processorA processorA controller4 controller4

Control Control

$lgorith%s $lgorith%s 3e.g. 3e.g. -PA%ath4 -PA%ath4

I%!

/IR filter

Pi+el processor ,aveform generator Pong

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//

1nd o$ Lecture

Copyright Bluespec Inc. 2005