Verification Plan

Verification Plan

This is the specification for the verification effort. It gives the what am I verifying and how am I going to do it!

Role of the Verification Plan

Specifies the Verification effort Defines 1st time success (ideally)

Specifying the Verification

When are you done? Metrics The specification determines the what has to be done! The specification does NOT determine the following:

How many will it take? How long will it take? Are you are doing needs to be done?

Verification Plans define that!

Specifying the Verification (continued)

The plan starts from the design specification why The reconvergence model!! Must exist in written form

the same thing as before, but at twice the speed, with these additions Not acceptable specification.

The specification is a golden document it is the law. It is the common source for the verification efforts and the implementation efforts.

Defining 1st time success

The plan determines what is to be verified.

If, and only if, it is in the plan will it be verified. The plan provides the forum for the entire design team to determine 1st time success. For 1st time success, every feature must be identified and under what conditions. As well as expected response.

Plan documents these features (as well as optional ones) and prioritized them.

This way, consciously, risk can be mitigated to bring in the schedule or reduce cost.

Defining 1st time success (continued)

Plan creates a well defined line, that when crossed can endanger the whole project and its success in the market. It defines:

How many test scenarios (testbenches/testcases) must be written How complex they need to be Their dependencies Number of resources it will take people, machines, etc Number of tasks that needs to be performed Time it will take with current resources

From the plan, a detailed schedule can be produced:

Verification Plan

Team owns it! Everyone involved in the project has a stake in it.

Anybody who identifies deficiencies should have input so they are fixed.

The process used to write the plan is not new. It has been used in the industry for decades. It is just now finding its way to hardware. Others who use it:

NASA FAA Software

Verification Levels

Verification can be performed at various granularities:

Designer/Unit/sub-subunit ASIC/FPGA/Reusable component System/sub-system/SoC board

Verification Levels (continued)

How to decide what levels? There are tradeoffs:

Smaller ones offer more control and observability but more effort to construct more environments Larger ones, the integration of the smaller partitions are implicitly verified at the cost of lower control and observability but less effort because fewer environments

Whatever level is decided, those pieces should remain stable. Each verifiable piece should have its own specification document

Unit Level

Usually pretty small Interfaces and functionality tend to change often Usually dont have independent specification associated with them Environment (if one) is usually ad hoc

Not intended to gain full coverage, just enough to verify basic operation (no boundary conditions)

High number of units in a design usually means it is not reasonable to do unit level due to high level of effort for environments

Reusable Component Level

Independent of any particular use Intended to be used as is in many different parts of a design. Saves in verification time.

Can code BFMs for these pieces that others who communication with the reusable component can use.

They necessitate a regression suite Components will not be reused if users do not have confidence in them

Gained by well documented and executed process

ASIC/FPGA Level

Physical partition provides a natural boundary for verification

Once specified, very little change due to ramification down stream.

FPGAs used to get debugged at integration. Now they are so dense, that a more ASIC flow is required.

System Level

What is a system?

Everyones definition is a little different.

Verification at this level focuses on interaction, not function buried in one piece. A large ASIC may take this approach. (Assuming that all pieces that make up the ASIC are specified, documented, and fully verified).

Assume that individual components are functionally correct. Testcase defines the system.

Board Level

This can be the same as system.

Think of an adapter for a PC.

Purpose is to confirm that the connectivity that the board design tool is correct. When doing board level verification, one must ensure that what is in the system, is what is to be manufactured. Things to consider

Many board level components dont fit into a digital simulation analog! What are suitable models (3rd party?) How to generate the net list (hand stitch or tool)

Current Practices for Verifying a System

Designer Level Sim

Verification of a macro (or a few small macros)

Unit Level Sim

Chip (Element) Sim

System Level Sim

In an Ideal World.

Every Macro would have perfect verification performed

All permutations would be verified based on legal inputs All outputs checked on the small chunks of the design

Unit, Chip, and System level would then only need to check interconnections

Ensure that macros used correct Input/Output assumptions and protocols

Reality

Macro verification across an entire system is not feasible

May be over 100 macros on a chip would require 200 verification engineers Number of skilled verification engineers does not exist Business cant support the development expense

Verification Leaders must make reasonable trade-offs

Concentrate on Unit level Designer level on riskiest macros

Verification Strategies

Must decide the following:

White Box, Black Box, Grey Box Types of testcases Level of abstraction where majority of verification takes place How to verify the response How random will it be

Verifying the Response

Deciding how to apply stimulus is usually easy part. Deciding response is hard part.

Must plan how to determine the expected response How to determine that design provided response that you expected

Detect errors and stop simulation as early as possible. Why?

Error identified when it takes place easier to debug No wasted simulation cycles

Random Verification

Does not mean randomly apply 0s and 1s to input - Still must produce valid stimulus The sequence of operations and the content of the data transferred is random! This creates conditions that one does not think of.

Hit corner cases Unexpected conditions Reduces bias from the engineer

Random Verification (continued)

Very complex to specify and code Must be a fair representation of what the operating conditions are for the design. Must include distributions and ranges More complicated to determine expected response. With proper constraints, a random environment can produce directed tests, the converse is not true.

Specifications to Features

1st step in planning is to identify features to test

Each feature labeled with short description Ideally the specification and verification plan are cross referenced Describe where the function will be verified

Unit level features bulk of verification System level features

Concentrate on functional errors, not tool induced errors.

Features to testcases

Prioritize the features

Must have features gate tape out Less important receive less attention

This helps project managers make informed decisions when schedule pressures arise. Group features into groups these become the testcases. Testcases should have descriptions and cross-references to features list. If a feature does not have a testcase assigned, it is not being verified. Define dependencies This will help prioritize Specify testcase stimulus (or constraints for random) Also must specify how each feature will be checked Inject errors to ensure that checks are working

Testcases to testbenches

Testcases naturally fall into groups

Similar configuration or same abstraction level

Cross-reference testbenches with testcases Assign testbenches to verification engineers Verifying the testbench

Use a broken model for each feature to be verified Peer reviews Provide logging messages in the testbench

Three Verification Commandments

2.

3.

Thou shalt stress thine logic harder than it will ever be stressed again! Thou shalt place checking upon all things! Thou shalt not move onto a higher platform until the bug rate has dropped off!

Verification Dos and Donts

Do:

Talk to designers about the function Spend time thinking about all the pieces that need to be verified Talk to other designers about the signals that interface to DUV
Rely on the designers word for input/output specification Allow a chip to go out without being properly verified pay now or pay later (with inflation!)

Dont: