Digital switching and networks

Transmission Network
Transport network used to Link different wire centers or exchange nodes. In India, Europe E1 (2 Mbps) and its higher order multiplex used. (PDH, SDH) In US etc. DS1 (1.544 mbps) and its higher order multiplex used. (SONET) Other technologies like Frame Relay, ATM etc also used.

Network Evolution
Earlier Networks (Up to early 70s)
Analog telephone network Frequency-division multiplexing

Present:
Local loop analog Network digital (based on TDM, predominantly Circuit switched)

Network Migration
IP based switching technology Next generation networks (packet switching, Soft switches, VoIP, IP Core networks)

Digital Switching
Methods of switching
Circuit switching, packet switching, and message switching

Circuit Switching

In circuit Switched Network- Path or pipe between two ends in communication is opened and stays open for the duration of the call

 Three switching categories for voice circuits are:

Local (line-to-line) switching Transit (tandem) switching Call distribution

Circuit Switch

Circuit switch is a device with n inputs and m outputs that creates a temporary connection between an input link and an output link.

Crossbar Switch

Crossbar switch connects n inputs to m outputs in a grid, using electronic micro-switches (transistors/Relays) at each cross-point.

Crossbar Switch
2X2 crossbar switch
Cross state Bar state

NXN crossbar switch

Connects N inputs and N outputs

Output blocking
Two inputs request the same output

Characteristics of Crossbar Switches

Crossbar switches are non-blocking
Connection requests to distinct outputs are never blocked

Complexity of the switch is (n2)

For large n, the number of crosspoints becomes very large

Performance Measure

Performance measures for a switch are: (a) connectivity, (b)

delay and call setup time, (d) Capacity, and (f) complexity (g) Call blocking and Packet loss rate - Connectivity is measured by the set of pairs of input and output links that can be simultaneously connected through the switch. The larger this set, the more versatile the switch. As it processes incoming bit streams in order to route them to the proper output ports - the switch introduces delays, and this delay is another measure of performance. For circuit switches, one component of delay is the switch setup time. For packet switches, the equivalent is queuing delay.

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Performance Measure (Contd.)

The capacity of a switch is the maximum rate at which it can move information, assuming all data paths are simultaneously active. The primary requirement of a switch is to maximize capacity for a given cost and a given reliability. - Measures to estimate the complexity of a switch include the number of cross points (circuit switch), and the buffer size (packet switch) - A circuit switch must reject a call if it does not have a path from an input to an output to carry the call, since it cannot buffer data. This is called call blocking. In a packet switch, data can be stored in a buffer, so call blocking is not a concern. Instead, the analog of call blocking is packet loss, that is, the loss of one or more packets because of a buffer overflowing when a burst of packets arrives at the switch.
-

12

Switch Representation
One representation of a switch is a black box shown at the top of the figure in the next page. Here, switch is a advice with M input and N output links. The second representation can be a cross bar where the complexity is measured in terms of number of cross points (M x N). The cross point can either be open or closed. In the figure input-output pairs (1,2), (2,1) , and (M, N) are closed. Rest of the cross points are open. The bottom figure represents a multi-stage switch where the input is not directly connected to output but indirectly connected through some number of middle stages. A generic switch shown below consists of four parts: (1) Input buffers; (2) Port mapper; (3) Switch Fabric; and (4) Output buffers Input Buffer: Input buffers store packets or samples as they arrive on the input lines. Some switches have tiny input buffers that hold data only while it is contending for the switch fabric. Other switches have almost all their buffers at the inputs

13

Switch Representation
The port mapper reads either the destination address or a virtual circuit identifier from an incoming packet's header and uses a table to decide the packet's output port. A circuit switch does not need a port mapper because each time slot is automatically associated with a path from an input to an output. The switch fabric routes data from an input to an output. The simplest switch fabric is a processor that reads data from an input port and writes it to an output port. Switch fabrics can also be complex multiprocessor systems that simultaneously transfer thousands of packets along many parallel data paths. Output buffers store data as they wait for a turn on the output line. At each output port, a scheduler manages the output buffers and arbitrates access to the output line. As with input buffers, these can be small or large. Some switches distribute, combine, or omit one or more of these functions. For an example, a switch may combine the input and output buffers, distribute the port mapper among the input ports, or omit the input buffers.

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1 2

...
Crosspoint

...
N

1 2

1 2

...
M

...
N

1 2

1 2

...
M

...
N

Top: Switch as a Black Box ; Middle: Crossbar switch; Bottom: Multi-stage switch
15

A Generic Switch
16

Single Stage Cross Bar Matrix

As shown above for M = N, the number of cross points required is N x (N-1). This is essentially a non-blocking matrix which implies that so long as the input output ports are free a path can always be completed. However, as N increases the number of required cross points can be excessively high. The number of cross points can be reduced to half i.e. N(N-1)/2 by going through a triangular array (still non-blocking). However, for large value of N the number of cross points can be prohibitively large. Therefore, both the multiple stages of matrix as well as some controlled amount of blocking can be introduced to reduce the number of cross points as discussed below. We will explore the case of multiple stage matrix Multiple stage switching: Following advantages can be obtained by implementing multiple stage of matrix: Reduction of number of cross points Reduction of capacitive loading (now there are not too many cross points from one inlet or one outlet) Specific cross point need not be operated going from one input to one output

17

Space Switch- Single Stage Switches

Similar to cross bar switches. Rectangular array of crosspoints which can be used to connect any one of N inlets to anyone of M outlets. Crosspoints are Semiconductor gates in Digital switches. Single stage switches have property that each individual crosspoint can only be used to interconnect one particular inlet outlet pair.

Single Stage Switches

If inlet/outlets are more i.e if N is large very large nos of crosspoints are required. If a crosspoint fails the associated connection cannot be established. Ineffective utilization of crosspoints- only one crosspoint in each row column of switch is ever in use even if all lines are active.

Multistage Switch

Multistage switch combines switches in several stages. Design of a multistage switch depends on the number of stages and the number of switches required (or desired) in each stage.

Multistage Switches.
Increases utilization of particular cross-point Reduce the number of cross-points More than one path available for connection. Alternate paths reduces blocking and provides protection against failures.

Multiple Switching Path

Multistage Switches
Multiple stages switches has interconnection between the stages Depending on the design it could be blocking or nonblocking

2(N/n)nk + k (N/n)2 crosspoints

Multistage Switches
Let N = number of inlets and outlets. Let n = size of each inlet-outlet group. Let k = number of center-stage arrays. There are N/n arrays in the first and last stages. There are (N/n) (nk) crosspoints in the first and last stages. There are k middle arrays with (N/n)2 crosspoints in each middle array. Total No of crosspoint
Nx = 2Nk+k(N/n)2

Multistage Switching
Nonblocking Switches 1953 Charles Clos Proposition for nonblocking three stage switches. If each individual array was nonblocking, and if the number of center stages k is equal to 2n1, the switch is strictly nonblocking. Number of stages is n-1 +n-1 +1 = 2n-1.

Condition for Internal Blocking

Clos Non Blocking Condition

Request connection from last input in input switch j to last output in output switch m
last input is in competition with remaining n-1 links in its inputstage switch last output is in competition with remaining n-1 links in its output-stage switch

Worst Case: All other inputs have seized top n-1 middle switches and all other outputs have seized next n-1 middle switches K=2n-2 path already occupied If one more path array is there the connection can be established i.e k=2n-1, there is another path left to connect desired input to desired output

Condition for Internal Blocking

If k < n, then the call can be blocked at the input stage For k >=2n 1 the switch non-blocking
(Called Clos Non Blocking Condition)

Three Stage Switch example

Exercise
Diagrammatically make a Clos (8,2,3) Multistage switch. N=8 n=2 k=3 Is it Blocking or non Blocking.

Example
Clos(8,2,3) N=8,n=2,k=3

2n-1= 4-1=3, is equal to k Its a non blocking switch.

Multistage Switching
Recall that the number of cross points in a three-stage switch.
Nx = 2Nk+k(N/n)2

Now let k = 2n-1 for nonblocking operations.

Nx = 2N(2n-1)+(2n-1)(N/n)2

Minimization of Crosspoints
optimum n for large N is (N/2)1/2 Nx(min) = 4N((2N)1/2 - 1)

Blocking
Strictly nonblocking switches are rarely needed in most voice telephone networks.
Switching systems and the number of circuits in interoffice trunk groups are sized to service most requests (not all) as they occur Economics dictates that network implementations have limited capacities that occasionally exceeded during peak traffic situations

Equipment for the public telephone network is designed to provide a certain maximum probability of blocking for the busiest hour of the day. Switch designed with certain grade of service assuming certain traffic generated by subscribers.

Blocking.
Grade of service of the telephone company depends on the blocking probability, availability, transmission quality, and delay Normally residential lines are busy 5-10% of the time during the busy hour. Business lines can be busy even more. Tandem Trunk lines busy 70% of time during busy hour. Network-blocking occurrences on the order of 1% during the busy hour do not represent a significant reduction in the ability to communicate since the called party is much more likely to have been busy anyway.

Blocking Probabilities
Significant Reduction in crosspoints by allowing acceptable blocking probabilities. C.Y.Lee (1955) analyzed the blocking probabilities using probability graphs.

Blocking Probabilities: Lee Graphs

If p - represents the fraction of the time that a particular link is in use (or p is the probability that a link is busy) q=1-p is the probability that the link is idle. When any one of n parallel links can be used to complete a connection, the composite blocking probability B is the probability that all links are busy

B= pn
When a series of n links are all needed to complete a connection, the blocking probability is mostly determined as 1 minus the probability that all links are available/idle

B= 1-qn

Blocking Probabilities: Lee Graphs

Any particular connection can be established with k different paths one through each center-stage array B=probability that all paths are busy =(probability that an arbitrary path is busy)k =(probability that at least one link of path is busy) k 2 =(1- q ) k Where k is the number of central stage array and q = 1- p is the probability that an interstage link is idle.

Blocking Probabilities: Lee Graphs

If the probability p that an inlet is busy is known, the probability p that an interstage link is busy can be determined as
p = p/ where =k/n (p < )

This implies that if input inlets are busy then the first stage outputs (or third stage inputs) are also busy. There are =k/n times as many interstage links as there are inlets and outlets. The percentage of interstage links that are busy is reduced by the factor If is less than 1, then the first stage concentrates the incoming traffic. is also referred to as space expansion factor

Blocking probability

Blocking probability
Number of crosspoints can be further reduced by adding additional stages in multistage switch

Number of crosspoints can be further reduced by adding additional stages in multistage switch

Five Stage Switch

Blocking Probabilities: Jacobaeus

Lee premise was that the composite blocking probability is product of blocking probability of alternate paths. Assuming that individual probabilities are independent. However in actual the probabilities are interdependent. As more & more path in switch are found to be busy the remaining paths are less likely to be in use. C. Jacobaeus (1950)--more accurate (but not exact) analysis of multistage switching matrices. B = [(n!)2/k!(2n-k)!] pk(2-p)2n-k

Comparison Lee/Jacobaeus

Comparison Lee/Jacobaeus

Path-finding
As more than one path in multistage switch the path selection logic is used to select the free path. The call processor must keep track of which potential paths are available. A pathfinding routine processes the state store information and select available path. Whenever a new connection is established or old is released the state store is updated with appropriate information.

Path-finding
The time required to find an available path is dependent on how many potential paths are tested before an idle one is found. Parallel testing can decrease the pathfinding time.

Path-finding
If p be the probability of a complete path through the switch being busy. If k is the number of possible paths, (All k paths are independent and each has an equal probability of being busy.) The number of paths that must be tested before finding an idle path is
Np = (1-pk)/(1-p)

Folded Four-Wire Switches

Folded Four-Wire Switches

Multiple stage switches can be used for 2-wire and 4-wire switching. Two paths must be completed for a 4-wire switched connection. Four stage switch- four wire can be considered foldable as one side of switch is mirror image of other. Here only one path finding operation is required reverse path is automatically selected

Folded Four-Wire Switches

Every crosspoint one side is paired with another crosspoint in the corresponding array on the opposite side of switch. Blocking probability is one half of the probability of two path independently. i.e reverse path is automatically available for any selected path in the forward direction. Path selection logic becomes simpler.

TDM Switching

Multiplexing
Frequency Division Multiplexing Time Division Multiplexing Code Division Multiplexing Space Division Multiplexing Polarisation Division Multiplexing

FDM v/s TDM

Time-division multiplexing (TDM)

Method of putting multiple data streams in a single signal by separating the signal into many segments, each having a very short duration. Each individual data stream is reassembled at the receiving end based on the timing. Multiplexer combines signals at the source (transmitting) end of a communications link. (It accepts the input from each individual end user, breaks each signal into segments, and assigns the segments to the composite signal in a rotating, repeating sequence. The composite signal thus contains data from multiple senders.) At the receiving end, the individual signals are separated out by demultiplexer, and routed to the proper end users.

Time division multiplexing (TDM)

The data are organized in frames where each frame contains a cycle of time slots A sequence of slots dedicated to one source is a channel Data from different sources is inserted into slots or channels in some sequence
Synchronous TDM slots are filled from a predetermined sequence of sources. If there is no data to transmit an idle signal is sent Statistical (Asynchronous)TDM fills slots as data is available. There is not preset sequence. Therefore, data must be associated with the source by address. No empty or idle slots are sent if any source has data ready to transmit. Idle is sent only if all channels have no data to transmit

 Telephone switch digitizes voice call (8000 8bit samples per second) switching method is TDM. switch multiplexes calls, 8-bit slot every 125 s

E1 (PCM) Frame structure

TDM Switching
Each subscriber occupies a time slot during conversation. To connect any two subscribers, it is necessary to interconnect the time-slots which maybe on same or different PCM highways The interconnection of timeslots i.e transferring information from one time slot to other is switching.

TDM switching
Switching Types
Time division switching Space division switching Hybrid

 Mostly all modern circuit switches uses timedivision switches.

Switch digital signals only. It is based on synchronous TDM. Multiple low speed inputs share a high speed line.

Time Division Switching

Time Slot Interchange

TSI consists of random access memory (RAM) with several memory locations. The number of locations is the same as the number of inputs. The size of each location is the same as the size of a single time slot. The RAM fills up with incoming data from time slots in the order received Slots are then sent out in an order based on the decisions of a control unit.

Time-slot Interchange Technique

Time division switch Slots are written and read from memory Each slot requires one write and one read operation The memory cycle time, the size of the sample, and input rate determine the size of the switch

Digital Time switch

Consists of SPEECH BUFFER and CONTROL(address) memory Number of storage locations are equal to number of input time slots. For e.g. for 32 TS I/P PCM, speech memory will have 32 locations Writing/reading of samples in speech memory is controlled by control memory.

Digital Time switch

Speech Memory
It stores the content of the time slots Number of location equal to number of time slots

Control Memory
Provide Read/Write addressing for reading speech memory. It has one location per input timeslot Each location contain address of one of the speech memory locations where the speech sample is either written or read. Addresses are written in the control memory by central control of the exchange

MUX/TSI/DEMUX

Time Switch

Time switch operating mode

Output Associated Control Sequential writing but controlled reading Data for each incoming time slots are stored in sequential location within memory location by incrementing timeslot counter. At output side information retrieved from control store specifies which address to be accessed for that time slot while reading.

Output Associated Control

Example Data of time slot 3 written sequentially at memory location 3. Control memory location 17 has control word corresponding to TS3 indicating that content of data store address 3 is transferred to OP link during O/G TS 17

Time switch operating mode

Input Associated control Controlled writing sequential reading Incoming information is written into memory location as per information in control store. Outgoing data are retrieved sequentially under control of an outgoing time slot.

Input associated control

Example Information received during time slot 3 is directly written in data store address-17. Control memory contains 17 as address at location 3, indicating that data of timeslot 3 is to be stored at address 17. Sequentially read out at output channel 17.

Time switch Characteristics

There is no blocking in a time switch In a time switch, there are as many memory locations as in the control and speech memories Corresponding to free incoming and outgoing time-slots, there is always a free path available to interconnect them

Time Switch V/s Space Switch

Space Switch
Advantage:
Instantaneous.

Disadvantage:
Number of cross points required.

Time Switch
Advantage:

No cross points.
Disadvantage:
Processing delay.

Hybrid Switches

TS Switch

TS Switch
Time stage delays information in arriving time slot. Time slot change can be in same frame or different frame S stage changes the link Control store/memory of S stage decide which link to switch.

TDM Switch Complexity.

In Space Division Switches complexity defined by number of crosspoints. More crosspoints -> more semiconductor gates -> more integrated circuit -> more circuit board requirement. In Time Division Switches data & control memory used. More Memory -> more complexity -> more cost

TDM Switch Complexity.

Historically Memory capacity taken in bits. Cost of number bits vs cost of crosspoints, (we use the ratio as 100) Assumption that 100 bits of memory corresponds to one crosspoint in terms of complexity of circuitry. Complexity = Nx+NB/100 NX= Number of space stage crosspoints NB is number of bits of memory and control

TDM Switch Complexity.

NB = number of bits of memory of space stage control memory NBx + number of bits of Time stage memory NBT NB= (NBx+NBT)/100 Complexity= NX+ (NBx+NBT)/100

STS Switching

Each S stage is assumed to be a single (nonblocking) stage. Path finding is the functional equivalent to a 3- stage spaced division switch an can be modeled using a Lee graph.

STS Switching
Blocking probability is similar to three stage space switch.
B =(1- q 2)k

Where k is the number of central stage time switch arrays and q = 1- p = 1- p/ is the probability that an interstage link is idle =k/N N be the number of inlets and outlets. Let k be the number of middle time stages.

STS Switching
Implementation Complexity N be the number of inlets and outlets & Let k be the number of middle stages. Assume that each TDM link has c message channels Complexity of STS switch= number of space stage crosspoints + (number of space stage control bits + number of time stage memory bits+ number of time stage control bits)/100 Complexity=2kN+(2kclog2N+kc(8)+kclog2 c)/100 There are 2kN crosspoints in the S stages, 2kclog2(N) space stage control bits, kc(8) time stage memory bits, kclog2 (c) time stage control bits.

STS Switching
Example 2048 channel STS Switch N= 16 links. c = 128 channels on each link. p = .1 B = .002. Result: k = 7 and the complexity becomes 430 equivalent crosspoints. Analysis show space switch design with 81,920 crosspoints, therefore there is substantial savings in STS design

TST Switch

TST Switch
There are two time stages separated by a space switch The time switch is a time slot changer Space switches single stage space switch. It is a highway changer. Functionally Space stage is replicated for every internal time slot which is different than TDM Time slots

TST Switching
The TST switch is strictly non-blocking if the S stage is non-blocking and if the number of space stage time slots is l=2c-1. where l is space stage time slots and c is TDM time slots. The time expansion = l/c. Blocking probability for TST is B =(1- q12) k Where q1=1-p1=1-p/

Complexity comparison of TST and STS.

Blocking probability 0.002

STS vs. TST

TST operates with time concentration and STS operates with space concentration. As line utilization increases, the expansion factor increases to keep the blocking probability low.

STS vs. TST

Time expansion can be achieved at less cost than space expansion. TST switching becomes more cost effective at higher utilization rates. Choice of architecture may actually be dependent on modularity, testability, and expandability.

Combination switches
T switch (gives full availability but large switch complex) TT, TTT, types are complex and uneconomical ST switch used for low capacity switch TST switch commonly used switch. STS switch used for PBX exchange TSST & TSSST with multiple space switch used for tandem exchange

Combination TSSST Switch

PSTN Switch (Exchange) Function

PSTN Switch provide a mechanism for connecting four types of calls Call to a subscriber - Originating call - Terminating call Call From/to Trunk - Incoming call - Outgoing call

General Architecture of Exchange

PSTN switch (Exchange)

Subscriber interfacing equipment provides access to the customer Trunk interfacing equipment provide access for incoming calls from other exchanges Switching Network provides path for through connection Control unit, does the call processing control and charging function

Statistical Multiplexing
Many input lines are multiplexed into a few trunks Exploit the fact that not all users are making calls all the time When a new call arrives and all the trunks are busy, the call is blocked (lost) Key design issue Given a demand, determine the number of trunks that will maintain the blocking probability below a certain value

PSTN Numbering Scheme

ITU standard E.164 Numbering format- E.164 uses a country code, area code and phone number International public telecommunication number for geographic areas (maximum 15 digits) Generally international numbers are limited to 12 digits and National Numbers to 10 digits. Country code National Destination code (optional) Subscriber Number In India PSTN follows- SDCA code+Subscriber Number (10 digit)

Call Dialing

Call Dialing
In pulse dialing, make break signal depending of dialed digit sent to exchange. Touch-tone dialing here two small bursts of signals, called dual tone sent. The frequency of the signals sent depends on the row and column of the pressed pad. Also called Dual Tone Multi Frequency (DTMF) dialing

Call Processing
When subscriber lifts handset off-hook is detected as a call event in the exchange. Path is established from subscriber line unit to signaling/tone unit providing dial tone to the subscriber Exchange receives the dialed digits. For receiving the tone dialing digits there are frequency receivers in the exchanges.

Call Processing

Call Processing
For every call processing event, call treatment programs become active Dedicated subsystems of a telephone exchange do the call treatment to find out - Type of call - Path to next node - Charging

Call Processing
Depending on the dialed digits and the customer profile the exchange software decides where to route the call. Dialed digits are mapped to exchange equipment No. (subscriber/trunk) The control unit of the exchange (distributed/centralized) controls the call establishment and facilitates finding of the switched path via the switching network of the exchange.

Call Processing
If the call is for a subscriber, path is found towards the corresponding subscriber line unit If its a call for other exchange the call path is found to a trunk. The control unit also records the call events which facilitates call charging and generation of call data records (CDRs)

Call Processing
For Inter exchange calls the dialed digits and call control information needs to be sent to other exchange Signaling mechanism is used to direct and control the setup and disconnection of inter exchange calls. Two types of signaling normally used
Channel Associated Signaling (CAS) Common Channel Signaling (CCS)

Signaling
In Channel Associated Signaling (CAS), the signaling takes place on the same TS or channel of the speech path. In Common Channel Signaling (CCS), a separate dedicated channel is used to send and receive signaling information for a group of trunks Signaling is facilitated by means of labeled messages. CCS No-7 Signaling is most commonly used signaling mechanism in PSTN network

Signaling

Other Switching Schemes

Circuit Switching Message Switching (Store-and-Forward) Packet Switching (Store-and-Forward)

Switching Schemes

Timing and Network Synchronization

Timing
All digital systems requires frequency source or clock for internal timing and external operations. The clock that quantifies the analog signal must be the same clock that reconstructs the signal at the other end. The only way to assure that the clock is accurate within the entire digital network is to have only one clock - not be practically possible.

Timing
When individual synchronous equipments are interconnected
They synchronize clock to each other If each subsystems uses slightly different clocks, provision to do some sort of adjustments to maintain timing consistencies.

Clock Instability
Wander, Jitter If clock frequency variation gradual its called wander. Rapid variations called Jitter Variation up to 10 Hz- Wander Variation > 10 Hz is taken as jitter.

Sources of Clock Instability

Interference and Noise Length of Transmission Media Speed of Transmission Doppler Shifts Irregular Timing information

Timing/Clock Recovery
Generally stable frequency sources are used on both transmitter and receiver side, but clock on receiving terminal is synchronized to the transmitting terminal by using different techniques. Clock Recovery Asynchronous Clocking Ones Density The Phase Locked Loop (PLL) Digital Data Link

PLL Clock Recovery

Phase detector continuously measures the phase difference between I/C Clk and Local Clk. Measures the difference in zero crossing between two clocks.

PLL Clock Recovery

When zero crossing of line Clk precedes the zero crossing of local Clk +ive voltage is generated otherwise ive This voltage is used for adjusting Voltage Control Oscillator (VCO) to reduce the phase difference. Local Clock maintains the desired average frequency but using PLL produces short term variations of phase & frequency to maintain underlying frequency of the line clock

TDM Switch Interface Timing

When digital transmission link is interfaced to a digital switch then
Digital switch provided timing for outgoing TDM link (Trans (Tx) side) Receive side timing (Rx) will have timing as per received link timing.

Concept of Elastic store is used for Timing adjustments.

Elastic Store
Elastic store is a data buffer that is written by one clock and read by another clock. ES absorbs instability in clock by using recovered clock based on received stream clk.

Elastic Store
If short term instability exists in either clk, ES absorbs the difference in the amount of data transmitted and amount of data received. If there is sustained clock offset the ES will eventually overflow or underflow causing timing inaccuracies.

Timing Inaccuracies
Three types of timing Inaccuracies
Slips Asynchronous Multiplexing Waiting Time Jitter

Slips
Disruption in data stream caused by underflow and overflow is called Slip. Uncontrolled Slip can lead to loss of frame synchronization. Approach to control slip is to repeat or delete entire frame when slip occurs. Can be carried out by using ES that can store at least one frame of data.

Slips

Slips
For simplified ES implementation ES is divided in A frame memory and B frame memory which stores alternative frames. Under normal case the output data is read alternatively from A & B When there is Slip the control logic resets the output channel counter so that A memory is read twice, thus repeating the entire frame. In TST switches the inlet memory normally provided both ES and Time switching function

Timing differences
Even with tightly-controlled timing, there are small timing differences between network elements and segments. The network has design features to make it tolerant to synchronization conditions where all clock elements are at the limit of their allowed tolerances (and, some margin above that).
Steady Timing differences Periodic Timing Differences Random Timing differences.

Steady Timing Differences

Frequency offset between one part of the network and another. The serial transmission schemes used in telecom networks require that the downstream receiver recovers its clock from the incoming serial stream, and thus adapts to variations in frequency. Gross frequency offset will ultimately cause a line signal to fall outside the clock recovery tolerance of the receiver in the downstream network element (for example, the tolerance for a 2 Mb/s PDH signal is 50 ppm). Faults like this are very unusual, however, even modest frequency offset is significant.

Steady Timing Differences

Network elements usually incorporate buffers to allow for timing differences. These buffers have a fixed size (usually around one transport signal frame or 25 Micro sec).

Steady Timing Differences

sustained frequency offset ultimately cause a buffer to overflow or underflow, causing what is known as a frame slip. This is where an entire frame of the signal is deleted or duplicated. Causes clicks on voice traffic & serious disruption to video signals or packetized data.

Periodic Timing Differences

Caused by Jitter High frequency (above 10 Hz). Clock recovery in line receivers can only follow such variations up to specific values, above which errors occur. Clock recovery devices work by continuously adjusting to track the average incoming rate. Theres a trade-off between the amount of jitter that can be tolerated and its frequency. The higher the frequency, the less jitter allowed

Random Timing Differences

Electrical noise, and the intrinsic characteristics of devices like phase locked loops within timing devices and clock recovery circuits result in random timing variations. Random change also occur due to transients caused by clock nodes switching from one clock source to another.

Network Synchronization
Network synchronization involves synchronizing the switches of the network to a reference clock. The transmission links are then synchronized automatically by deriving timing from switching node. If transmission link is connected to both ends to a digital switch it derives timing from only one switch.

Network Synchronization
For perfect synchronization ideally All networks should take clock from same source. The idea of a universal, single master clock for the entire worldwide telecom network is somewhat idealist: for example, where would it be located, what backup provisions would be necessary etc.

Network Synchronization
In practice, individual national or operator networks have their own high stability master timing references (known as stratum 1 or PRC/S primary reference clock/standards). These clocks are elaborate caesium-beam standards and their accuracy, as specified in ITU G.811 and ETS-300 462-6, is 1 part in 1011. The network switches is then synchronized using this reference clock with intermediate Primary reference clocks with lesser stringent timing requirements.

Methods of Network Synchronization

Different approaches are used for synchronizing digital network.
Plesiochronous Pulse Stuffing Mutual Synchronization Network Master Master-slave clocking Packetization

Plesiochronous
No synchronization, independent switching nodes use highly accurate clocks so that slip rates between nodes is low. Simplest to implement. Costly as Accurate Timing generators/oscillators are costly. Higher level switches, International gateways normally use this method of synchronization.

Pulse Stuffing
Pulse stuffing is used to avoid both slips and clock synchronization. Concept of pulse stuffing
use of output channel whose rate is purposely higher than the input rate. Output channel carries all input data plus some null bits or stuff bits. Extraneous null bits are destuffed to recover original data

Pulse stuffing
Each network node can therefore work on its own clock without synchronization. The information is stuffed up to local channel rate. At interface running at different clocks the individual channels are unstuffed at incoming rate and again stuffed at local or outgoing rate further. Telephone multiplexes use pulse stuffing to adjust for the differences arising due to combining of tributaries operating at different rate.

Mutual Synchronization
Mutual synchronization establishes a common network clock frequency, where each node of the network, exchange frequency reference. Each node averages the incoming reference and then uses this for local and transmitted clock. In long term the clock stabilizes to a single stable network frequency.

Mutual Synchronization
Advantage - ability to remain operation even if there is clock failure at any node. Disadvantage - uncertainty of average frequency especially in case there is clock problems at multiple nodes.

Network Master
Common Master Clock is transmitted to all nodes. All Node directly connected to master reference. A separate Timing transmission network required to carry timing info to each node. Advantage- Accuracy Disadvantage- Cost of separate Timing NW.

Master Slave Synchronization

Master Slave Synchronization

High level switches are synchronized to Master clock. Reference clock frequency is passed on to lower level switches by way of existing digital transmission links.(SONET, SDH, PDH) Next Lower level synchronizes, the further networks elements.

Master Slave Synchronization

Upper level switches acts as master to next lower level switch(slave) which in turn is master for next lower level. All switching nodes are synchronized directly or indirectly to same reference clock. Most commonly used method of synchronization world over.

Clock Distribution

Sync Clock Distribution

How many PRC Source (level-1 clocks) exist in a particular telephone company network depends on their basic needs. Earlier VSNL was having a master clock and complete National network in India was further synchronized on Master Slave configuration. Now each company/operator has its own reference clock. Combination of Plesiochronous/Hierarchal design used in majority of networks