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DSD 15

CPLDs consist of multiple programmable logic devices on a single integrated circuit. This allows for more complex logic to be implemented compared to a single PLD. A CPLD uses a programmable interconnect structure to connect the individual PLDs together, similarly to how individual PLDs could be connected externally. Common CPLD manufacturers like Xilinx and Altera produce product families with devices that vary in resources like number of macrocells, I/O pins, and package size. Choosing a suitable CPLD depends on factors like the required gate density and familiarity with the manufacturer's internal architecture.

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78 views

DSD 15

CPLDs consist of multiple programmable logic devices on a single integrated circuit. This allows for more complex logic to be implemented compared to a single PLD. A CPLD uses a programmable interconnect structure to connect the individual PLDs together, similarly to how individual PLDs could be connected externally. Common CPLD manufacturers like Xilinx and Altera produce product families with devices that vary in resources like number of macrocells, I/O pins, and package size. Choosing a suitable CPLD depends on factors like the required gate density and familiarity with the manufacturer's internal architecture.

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nitcvishesh
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CPLDs

CPLDs
CPLDs
• The design of a digital system using PLD often
requires the connection of several devices to
produce the complete specification.
• For these type of applications, Complex
Programmable Logic Devices (CPLD) are more
suitable.
• A CPLD is a collection of individual PLDs on a
single integrated circuit.
• A programmable interconnection structure allows
the PLDs to be connected to each other in the
same way that can be done with the individual
PLD’s.
How to expand PLD architecture?
• Increase # of inputs and outputs in a conventional
PLD?
– E.g., 16V8 --> 20V8 --> 22V10.
– Why not --> 32V16 --> 128V64 ?
• Problems:
– n times the number of inputs and outputs requires n2 as much
chip area -- too costly
– logic gets slower as number of inputs to AND array increases
• Solution: multiple PLDs with a relatively small
programmable interconnect.
– Less general than a single large PLD, but can use software
“fitter” to partition the design into smaller PLD blocks.
CPLDs

I/O Blocks provide the connection to IC pins. Each I/O pin is 
driven by a tri­state buffer and can be programmed to act as 
input or output. 
CPLDs

• The switch matrix receives inputs from the I/O block


and directs it to the individual macrocells.
• Similarly, selected outputs from macrocells are sent
to the outputs as needed.
• Each PLD typically contains from 8 to 16
macrocells.
• The macrocells within each PLD are usually fully
connected. If a macrocell has unused product terms
they can be used by other nearby macrocells.
CPLDs
• Different manufacturers use different approaches
to make individual PLDs, the type of macrocells,
I/O blocks and the programmable interconnection
structure.
• The basic component used in PLD is the gate
array. A gate array consists of pattern of gates
fabricated in an area of silicon that is repeated
thousands of times until the entire chip is covered
with the gates.
CPLD - Structure
General concept: many PLD devices on one IC

I/O block

I/O block
In practice: PLD block PLD block

• more product terms;


• more routing resources;
• more macro cells;
• greater connectivity Interconnection wires

between macro cells


allows implementation of
wider more complex
I/O block

I/O block
PLD block PLD block
functions.
CPLD Manufactures
1) Altera

2) Xilinx

Just like TI and ADI in DSP market


CPLD families
• Identical individual PLD blocks replicated in
different family members.
– Different number of PLD blocks
– Different number of I/O pins
• Many CPLDs have fewer I/O pins than macrocells
– “Buried” Macrocells -- provide needed logic terms
internally but these outputs are not connected externally.
– IC package size dictates # of I/O pins but not the total # of
macrocells.
XC95288-15BG352C
Typical CPLD families have devices with differing resources
in the same IC package.
Xilinx CPLD Product Family
CoolRunner-II 1.8 Volt CPLD
• Low power
• Up to 512 macrocells
• Up to 4 I/O banks
• Advanced security features
• 1.5V interfacing
XC9500XV 2.5 Volt CPLD
•Up to 4 I/O banks
•2.5V, 3.3V I/O tolerance
•Up to 288 macrocells
•More product terms per macrocell
Xilinx CPLD Product Family
XC9500XL 3.3 Volt CPLD
• 5V tolerance
• Up to 288 macrocells
• More product terms per macrocell
• Industry's highest I/O per package

CoolRunner XPLA3 3.3 Volt CPLD


• Low power
• 5V tolerance
• Up to 512 macrocells

XC9500 5 Volt CPLD


• 5V I/O tolerance
• Up to 288 macrocells
• 24 mA I/O drive
Xilinx XC9500 Product Family
9536 9572 95108 95144 95216 95288

Macrocells 36 72 108 144 216 288

Usable Gates 800 1600 2400 3200 4800 6400

tPD (ns) 5 7.5 7.5 7.5 10 10

Registers 36 72 108 144 216 288


Max I/O 34 72 108 133 166 192

Packages VQ44
PC44 PC44
PC84 PC84
TQ100 TQ100
PQ100 PQ100 PQ100
PQ160 PQ160 PQ160
HQ208 HQ208
BG352 BG352
Xilinx 9500-family CPLD architecture

72 ==>
XC9572
9500-family Function Blocks (FBs)

• 18 macrocells per FB
• 36 inputs per FB
• Macrocell outputs can go to I/O cells or back into switch
matrix to be routed to this or other FBs.
Each function block is like a 36V18 !
9500-series macrocell (18 per FB)
Set control
Programmable
inversion or XOR
product term

Up to 5 
product terms
Global clock or 
product­term clock

Reset control

OE control
9500-series product-term allocator
9500-series product-term allocator
programmable
steering Share terms from 
elements above and below
9500-series
I/O block
Altera CPLD Product Family

Max II
MAX 9000
Max 7000
Max 3000
Classic Devices
Altera MAX9000 CPLD Family
Altera MAX9000 CPLD architecture
MAX9000
LAB architecture
Altera MAX9000 CPLD Macrocell
Altera MAX9000 CPLD Sharable Expander
Altera MAX9000 CPLD Product Expander
Choosing a CPLD for particular application
•Unlike the choice of other standard ICs this is often difficult because of
different architectures existing in industry

•The gate density of the CPLD may not always tell you exactly the kind of
logic that can be implemented using it.

•Xilinx used Function Blocks(FBs) and Altera uses Logic Array Blocks
(LABs) in their CPLDs for SOP implementation. The gate density may be

sometimes specified in terms of FBs or LABs

•CPLDs are generally based on EPROM for configuration (no of rewrite


is
limited to 200 to 1000 times)

•The dividing line between a CPLD and FPGA is already vague ( just like
the division between PC and workstation)

•You can design better circuits if you are familiar with internal
architecture

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