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Cache Memory-Direct Mapping

The document discusses cache memory and provides details on its characteristics, including location, capacity, unit of transfer, access methods, performance, physical type, and organization. It specifically covers cache location, capacity measured in word size and number of words, unit of transfer which can be word size internally and larger blocks externally, and access methods including sequential, direct, random, and associative.

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Eswin Angel
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Download as PPT, PDF, TXT or read online on Scribd
775 views

Cache Memory-Direct Mapping

The document discusses cache memory and provides details on its characteristics, including location, capacity, unit of transfer, access methods, performance, physical type, and organization. It specifically covers cache location, capacity measured in word size and number of words, unit of transfer which can be word size internally and larger blocks externally, and access methods including sequential, direct, random, and associative.

Uploaded by

Eswin Angel
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Computer Organization and Architecture

Cache Memory

Characteristics
Location Capacity Unit of transfer Access method Performance Physical type Physical characteristics Organisation

Location
CPU Internal External

Capacity
Word size
The natural unit of organisation

Number of words
or Bytes

Unit of Transfer
Internal
Usually governed by data bus width

External
Usually a block which is much larger than a word

Addressable unit
Smallest location which can be uniquely addressed Word internally Cluster on M$ disks

Access Methods (1)


Sequential
Start at the beginning and read through in order Access time depends on location of data and previous location e.g. tape

Direct
Individual blocks have unique address Access is by jumping to vicinity plus sequential search Access time depends on location and previous location e.g. disk

Access Methods (2)


Random
Individual addresses identify locations exactly Access time is independent of location or previous access e.g. RAM

Associative
Data is located by a comparison with contents of a portion of the store Access time is independent of location or previous access e.g. cache

Memory Hierarchy
Registers
In CPU

Internal or Main memory


May include one or more levels of cache RAM

External memory
Backing store

Memory Hierarchy - Diagram

Performance
Access time
Time between presenting the address and getting the valid data

Memory Cycle time


Time may be required for the memory to recover before next access Cycle time is access + recovery

Transfer Rate
Rate at which data can be moved

Physical Types
Semiconductor
RAM

Magnetic
Disk & Tape

Optical
CD & DVD

Others
Bubble Hologram

Physical Characteristics
Decay Volatility Erasable Power consumption

Organisation
Physical arrangement of bits into words Not always obvious e.g. interleaved

The Bottom Line


How much?
Capacity

How fast?
Time is money

How expensive?

Hierarchy List
Registers L1 Cache L2 Cache Main memory Disk cache Disk Optical Tape

So you want fast?


It is possible to build a computer which uses only static RAM (see later) This would be very fast This would need no cache
How can you cache cache?

This would cost a very large amount

Locality of Reference
During the course of the execution of a program, memory references tend to cluster e.g. loops

Cache
Small amount of fast memory Sits between normal main memory and CPU May be located on CPU chip or module

Cache operation - overview


CPU requests contents of memory location Check cache for this data If present, get from cache (fast) If not present, read required block from main memory to cache Then deliver from cache to CPU Cache includes tags to identify which block of main memory is in each cache slot

Cache Design
Size Mapping Function Replacement Algorithm Write Policy Block Size Number of Caches

Size does matter


Cost
More cache is expensive

Speed
More cache is faster (up to a point) Checking cache for data takes time

Typical Cache Organization

Mapping Function
Cache of 64kByte Cache block of 4 bytes
i.e. cache is 16k (214) lines of 4 bytes

16MBytes main memory 24 bit address


(224=16M)

Direct Mapping
Each block of main memory maps to only one cache line
i.e. if a block is in cache, it must be in one specific place

Address is in two parts Least Significant w bits identify unique word Most Significant s bits specify one memory block The MSBs are split into a cache line field r and a tag of s-r (most significant)

Direct Mapping Address Structure


Tag s-r 8 Line or Slot r 14 Word w 2

24 bit address 2 bit word identifier (4 byte block) 22 bit block identifier
8 bit tag (=22-14) 14 bit slot or line

No two blocks in the same line have the same Tag field Check contents of cache by finding line and checking Tag

Direct Mapping Cache Line Table Cache line 0 1 m-1 Main Memory blocks held 0, m, 2m, 3m2s-m 1,m+1, 2m+12s-m+1 m-1, 2m-1,3m-12s-1

Direct Mapping Cache Organization

Direct Mapping Example

Direct Mapping Summary


Address length = (s + w) bits Number of addressable units = 2s+w words or bytes Block size = line size = 2w words or bytes Number of blocks in main memory = 2s+ w/2w = 2s Number of lines in cache = m = 2r Size of tag = (s r) bits

Direct Mapping pros & cons


Simple Inexpensive Fixed location for given block
If a program accesses 2 blocks that map to the same line repeatedly, cache misses are very high

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