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Lamda

Design rules and layout specifications are used to ensure proper fabrication of integrated circuits. Historically, process technology referred to transistor channel lengths, with other feature sizes derived as ratios. For example, a 90nm process may have a 90nm channel length but 50nm gate width. Design rules specify minimum widths, spacings, and distances using a lambda (λ) parameter, where λ is half the minimum drawn transistor length. This allows rules to scale with technology. Key rules include a 2λ poly-poly spacing, 3λ diffusion-diffusion spacing, and λ diffusion-poly spacing. Metal can overlap other layers without effect, but is spaced λ for electrical isolation. Design rules balance circuit performance needs

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137 views

Lamda

Design rules and layout specifications are used to ensure proper fabrication of integrated circuits. Historically, process technology referred to transistor channel lengths, with other feature sizes derived as ratios. For example, a 90nm process may have a 90nm channel length but 50nm gate width. Design rules specify minimum widths, spacings, and distances using a lambda (λ) parameter, where λ is half the minimum drawn transistor length. This allows rules to scale with technology. Key rules include a 2λ poly-poly spacing, 3λ diffusion-diffusion spacing, and λ diffusion-poly spacing. Metal can overlap other layers without effect, but is spaced λ for electrical isolation. Design rules balance circuit performance needs

Uploaded by

parrotpandu
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Design rules and Layout

Engr. Mudasir Ahmed Memon

Design rules and Layout


Why we use design rules?
Interface between designer and process engineer

Historically, the process technology referred to the length of the silicon channel between the source and drain terminals in field effect transistors (see FET). The sizes of other features are generally derived as a ratio of the channel length, where some may be larger than the channel size and some smaller. For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the gate terminal may be only 50 nm.

Design Rules
Two major approaches: Micron rules: stated at micron resolution. rules: simplified micron rules with limited scaling attributes. Design rules represents a tolerance which insures very high probability of correct fabrication scalable design rules: lambda parameter absolute dimensions (micron rules)

Micron rules
All minimum sizes and spacing specified in microns. Rules don't have to be multiples of . Can result in 50% reduction in area over based rules Standard in industry.

Lambda-based Design Rules


Lambda-based (scalable CMOS) design rules define scalable rules based on (which is half of the minimum channel length) Stick diagram is a draft of real layout, it serves as an abstract view between the schematic and layout.

Circuit designer in general want tighter, smaller layouts for improved performance and decreased silicon area. On the other hand, the process engineer wants design rules that result in a controllable and reproducible process. Generally we find there has to be a compromise for a competitive circuit to be produced at a reasonable cost.

All widths, spacing, and distances are written in the form m = 0.5 X minimum drawn transistor length

Design Rules
Minimum width of PolySi and diffusion line 2 Minimum width of Metal line 3 as metal lines run over a more uneven surface than other conducting layers to ensure their continuity

Metal Diffusion

3 2 2

Polysilicon

Design Rules
PolySi PolySi space 2 Metal - Metal space 2 Diffusion Diffusion 3 To avoid the possibility of their associated regions overlapping and conducting current

Metal 2 Diffusion

Polysilicon

Design Rules
Diffusion PolySi To prevent the lines overlapping to form unwanted capacitor Metal lines can pass over both diffusion and polySi without electrical effect. Where no separation is specified, metal lines can overlap or cross

Metal Diffusion

Polysilicon

Metal Vs PolySi/Diffusion
Metal lines can pass over both diffusion and polySi without electrical effect It is recommended practice to leave between a metal edge and a polySi or diffusion line to which it is not electrically connected
Metal Polysilicon

Review:
poly-poly spacing

diff-diff spacing 3 (depletion regions tend to spread outward) metal-metal spacing 2 diff-poly spacing

Butting Contact
The gate and source of a depletion device can be connected by a method known as butting contact. Here metal makes contact to both the diffusion forming the source of the depletion transistor and to the polySi forming this devices gate.

Advantage:
No buried contact mask required and avoids associated
processing.

Butting Contact
Problem: Metal descending the hole has a tendency to fracture at the polySi corner, causing an open circuit. Metal Insulating Oxide
n+ n+

Gate Oxide

PolySi

Buried Contact
Here gate length is depend upon the alignment of the buried contact mask relative to the polySi and therefore vary by .

PolySi
2 Channel length

Buried contact

Diffusion

Contact Cut
Metal connects to polySi/diffusion by contact cut. Contact area: 2*2 Metal and polySi or diffusion must overlap this contact area by so that the two desired conductors encompass the contact area despite any mis-alignment between conducting layers and the contact hole

Contact Cut
Contact cut any gate: 2 apart Why? No contact to any part of the gate.

4
2

Contact Cut
Contact cut contact cut: 2 apart Why? To prevent holes from merging.

NMOS Inverter

CMOS Inverter

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