Serial Input/Ouptut Interrupts

By: 10545,10546,10547,10548, 10549,10552,10555

Interrupts
Interrupt is a process where an external device can get the attention of the microprocessor.
The process starts from the I/O device The process is asynchronous.

Classification of Interrupts
Interrupts can be classified into two types:
Maskable Interrupts (Can be delayed or Rejected) Non-Maskable Interrupts (Can not be delayed or Rejected)

Interrupts can also be classified into:

Vectored (the address of the service routine is hard-wired) Non-vectored (the address of the service routine needs to be supplied externally by the device)

Interrupts
An interrupt is considered to be an emergency signal that may be serviced.
The Microprocessor may respond to it as soon as possible.

What happens when microprocessor is interrupted ?

When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most probably have its own ISR.

The 8085 Interrupts

When a device interrupts, it actually wants the microprocessor to give a service which is equivalent to asking the microprocessor to call a subroutine. This subroutine is called ISR (Interrupt Service Routine) The EI instruction is a one byte instruction and is used to Enable the non-maskable interrupts. The DI instruction is a one byte instruction and is used to Disable the non-maskable interrupts. The 8085 has a single Non-Maskable interrupt.
The non-maskable interrupt is not affected by the value of the Interrupt Enable flip flop.

The 8085 Interrupts

The 8085 has 5 interrupt inputs.
The INTR input. The INTR input is the only non-vectored interrupt. INTR is maskable using the EI/DI instruction pair. RST 5.5, RST 6.5, RST 7.5 are all automatically vectored. RST 5.5, RST 6.5, and RST 7.5 are all maskable. TRAP is the only non-maskable interrupt in the 8085 TRAP is also automatically vectored

The 8085 Interrupts

Interrupt name INTR RST 5.5 RST 6.5

Maskable Yes Yes Yes

Vectored No Yes Yes

RST 7.5
TRAP

Yes
No

Yes
Yes

8085 Interrupts

TRAP RST7.5 RST6.5 RST 5.5 INTR INTA

8085

The 8085 Non-Vectored Interrupt Process

The interrupt process should be enabled using the EI instruction. The 8085 checks for an interrupt during the execution of every instruction. If INTR is high, microprocessor completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted INTA allows the I/O device to send a RST instruction through data bus. Upon receiving the INTA signal, microprocessor saves the memory location of the next instruction on the stack and the program is transferred to call location (ISR Call) specified by the RST instruction

The 8085 Non-Vectored Interrupt Process

Microprocessor Performs the ISR. ISR must include the EI instruction to enable the further interrupt within the program. RET instruction at the end of the ISR allows the microprocessor to retrieve the return address from the stack and the program is transferred back to where the program was interrupted.

The 8085 Non-Vectored Interrupt Process

The 8085 recognizes 8 RESTART instructions: RST0 RST7.
each of these would send the execution to a predetermined hard-wired memory location:
Restart Instruction RST0 RST1 RST2 RST3 RST4 RST5 RST6 RST7 Equivalent to CALL 0000H CALL 0008H CALL 0010H CALL 0018H CALL 0020H CALL 0028H CALL 0030H CALL 0038H

Restart Sequence
The restart sequence is made up of three machine cycles
In the 1st machine cycle: The microprocessor sends the INTA signal. While INTA is active the microprocessor reads the data lines expecting to receive, from the interrupting device, the opcode for the specific RST instruction. In the 2nd and 3rd machine cycles: the 16-bit address of the next instruction is saved on the stack. Then the microprocessor jumps to the address associated with the specified RST instruction.

Multiple Interrupts & Priorities

How do we allow multiple devices to interrupt using the INTR line?
The microprocessor can only respond to one signal on INTR at a time. Therefore, we must allow the signal from only one of the devices to reach the microprocessor. We must assign some priority to the different devices and allow their signals to reach the microprocessor according to the priority.

The 8085 Maskable/Vectored Interrupts

The 8085 has 4 Masked/Vectored interrupt inputs.
RST 5.5, RST 6.5, RST 7.5
They are all maskable. They are automatically vectored according to the following table:
Interrupt RST 5.5 Vector 002CH

RST 6.5
RST 7.5

0034H
003CH

The vectors for these interrupt fall in between the vectors for the RST instructions. Thats why they have names like RST 5.5 (RST 5 and a half).

Masking RST 5.5, RST 6.5 and RST 7.5

These three interrupts are masked at two levels:
Through the Interrupt Enable flip flop and the EI/DI instructions. The Interrupt Enable flip flop controls the whole maskable interrupt process. Through individual mask flip flops that control the availability of the individual interrupts. These flip flops control the interrupts individually.

The 8085 Maskable/Vectored Interrupt Process

The interrupt process should be enabled using the EI instruction. The 8085 checks for an interrupt during the execution of every instruction. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and reset the interrupt flip flop. The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table.

The 8085 Maskable/Vectored Interrupt Process

When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack. The microprocessor jumps to the specific service routine. The service routine must include the instruction EI to re-enable the interrupt process. At the end of the service routine, the RET instruction returns the execution to where the program was interrupted.

SOD (Serial Output Data) line

It is a data line for serial output. The 7th bit of the accumulator is outputed on SOD line when SIM instruction is executed. This is an output signal which enables the transmission of serial data bit by bit to the external device. The individual masks for maskable interrupts is manipulated by using the SIM instruction. We shall now see how to manipulate the masks using SIM instruction.

Manipulating the Masks

The Interrupt Enable flip flop is manipulated using the EI/DI instructions. The individual masks for RST 5.5, RST 6.5 and RST 7.5 are manipulated using the SIM instruction.
This instruction takes the bit pattern in the Accumulator and applies it to the interrupt mask enabling and disabling the specific interrupts.

SIM and the Interrupt Mask

Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit 2 is the mask for RST 7.5.
If the mask bit is 0, the interrupt is available. If the mask bit is 1, the interrupt is masked.

Bit 3 (Mask Set Enable - MSE) is an enable for setting the mask.
If it is set to 0 the mask is ignored and the old settings remain. If it is set to 1, the new setting are applied. The SIM instruction is used for multiple purposes and not only for setting interrupt masks.
It is also used to control functionality such as Serial Data Transmission. Therefore, bit 3 is necessary to tell the microprocessor whether or not the interrupt masks should be modified

SIM and the Interrupt Mask

The RST 7.5 interrupt is the only 8085 interrupt that has memory.
If a signal on RST7.5 arrives while it is masked, a flip flop will remember the signal. When RST7.5 is unmasked, the microprocessor will be interrupted even if the device has removed the interrupt signal. This flip flop will be automatically reset when the microprocessor responds to an RST 7.5 interrupt.

Bit 4 of the accumulator in the SIM instruction allows explicitly resetting the RST 7.5 memory even if the microprocessor did not respond to it. Bit 5 is not used by the SIM instruction

Using the SIM Instruction to Modify the Interrupt Masks Example: Set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked, and RST7.5 is enabled.
First, determine the contents of the accumulator
- Enable 5.5 - Disable 6.5 - Enable 7.5 - Allow setting the masks - Dont reset the flip flop - Bit 5 is not used - Dont use serial data - Serial data is ignored bit 0 = 0 bit 1 = 1 bit 2 = 0 bit 3 = 1 bit 4 = 0 bit 5 = 0 bit 6 = 0 bit 7 = 0 M5.5 M6.5 M7.5 MSE R7.5 XXX SOE SOD 0 0 0 0 1 0 1 0 Contents of accumulator are: 0AH

EI MVI A, 0A SIM

; Enable interrupts including INTR ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5 ; Apply the settings RST masks

Triggering Levels
RST 7.5 is positive edge sensitive.
When a positive edge appears on the RST7.5 line, a logic 1 is stored in the flip-flop as a pending interrupt. Since the value has been stored in the flip flop, the line does not have to be high when the microprocessor checks for the interrupt to be recognized. The line must go to zero and back to one before a new interrupt is recognized.

RST 6.5 and RST 5.5 are level sensitive.

The interrupting signal must remain present until the microprocessor checks for interrupts.

SID (Serial Input Data) line

It is data line for serial input. The data on this line is loaded into the 7th bit of the accumulator when RIM instruction is executed. This is an input signal which enables the transmission of serial data bit by bit from the external device. The 8085 has an instruction RIM using which the programmer can know the current status of pending interrupts (only maskable interrupts). We will now see how to determine the current mask settings using the RIM instruction.

Determining the Current Mask Settings

RIM instruction: Read Interrupt Mask
Load the accumulator with an 8-bit pattern showing the status of each interrupt pin and mask.

The RIM Instruction and the Masks

Bits 0-2 show the current setting of the mask for each of RST 7.5, RST 6.5 and RST 5.5
They return the contents of the three mask flip flops. They can be used by a program to read the mask settings in order to modify only the right mask.

Bit 3 shows whether the maskable interrupt process is enabled or not.

It returns the contents of the Interrupt Enable Flip Flop. It can be used by a program to determine whether or not interrupts are enabled.

The RIM Instruction and the Masks

Bits 4-6 show whether or not there are pending interrupts on RST 7.5, RST 6.5, and RST 5.5
Bits 4 and 5 return the current value of the RST5.5 and RST6.5 pins. Bit 6 returns the current value of the RST7.5 memory flip flop.

Bit 7 is used for Serial Data Input.

The RIM instruction reads the value of the SID pin on the microprocessor and returns it in this bit.

Pending Interrupts
Since the 8085 has five interrupt lines, interrupts may occur during an ISR and remain pending.
Using the RIM instruction, it is possible to can read the status of the interrupt lines and find if there are any pending interrupts. If an interrupt is pending the processor executes its interrupt service subroutine before it returns to the main program.