Memory Interfacing
Memory Interfacing
The interface process involves designing a circuit that will match the memory requirements with the microprocessor signal.[Memory has certain signal requirements to read from and write into memory. Similarly Microprocessor initiates the set of signals when it wants to read from and write into memory].
EPROM : Chip must be programmed before it can be used as ROM. Figure Shows:
4096 (4K) registers. Register store 8-bits 8 input lines Internal decoder to decode address lines. 12 address lines(A11-A0), 1 chip select, 1 Read control Signal lines to enable output buffer.
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Fig: EPROM
Select the Chip Identify the register Enable the appropriate buffer.
Timing Diagram of 8085 Memory Read/Write Machine Cycle allows to understand microprocessor interfacing concepts.
Remaining
of
8085
Two methods to decoding these lines: by NAND gate: Output of NAND gate is active and select
the chip only when all address lines A15-A12 are at logic1
1 1
0FFFH
Interfacing Circuit
Fig :
Interfacing Circuit
Fig: Interfacing Circuit using 3x8 Decoder to interface 2732 EPROM.
The 8085 address lines A11-A0 are connected to the pins A11-A0 of the memory chip.
Decoder decode A15-A12 and output O0 is connected to CE which is asserted only when A15-A12 is 0000 (A15 low enables decoder and input 000 asserts the output O0). One control signal MEMR is connected to OE to enable output buffer.
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Interfacing Circuit
Examine how 8085 places the address 0FFFH on address bus.
Remaining address lines FFFH goes on address lines of the chip and the internal decoder decodes the address and selects the register FFFH.
When RD is asserted the output buffer is enabled and the contents of register 0FFFH are places on the data bus for the processor to read.
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Interfacing 6116 Memory Chip with 2K Registers 11 Address lines A10-A0 to decode 2048K registers. Address lines A15-A11 are connected to decoder(which is enabled by IO/M signal in addition to the address lines A15 and A14). RD and WR signals are directly connected to memory chip. MEMR and MEMW need not to be generated separately (this technique save two gates). Memory Address Ranges from 8800H to 8FFFH. A13-A11(001) activate output O1 of decoder which is connected to CE of memory chip
and it is asserted only when IO/M is low. A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 8800H Chip Select 1 1 1 1 1 1 1 1 1 1 1 1 8FFFH
8 Address lines. One CE. 5 Control and status signals (IO/M, ALE,
RD, WR and RESET).
Includes 256x8 memory locations Internal latch for de-multiplexing CE, MEMR and MEMW control
signals
8205, a 3x8 Decoder, decodes the address lines A15-A11, O4 enables the memory chip. Control and status signals from 8085 are connected to the respective signals of memory chip.
A7-A0 address any one of the 256 registers. A14-A15 are active low and third line is permanently enable by tying it with +5V. A10-A8 are not connected(dont care lines). O4 is low for following address.
A15 A14 A13 A12 A11 A10 A9 A8 0 0 1 0 0 0 0 0 20H
range is from 2000H to care lines are at logic 0, called primary address back memory or mirror