EE/CSE 324 FPGA based System Design

An Introduction

Dr. Nasir D. Gohar

Professor/HoD CSE Department NUST Institute of Information Technology

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What is this Course all about?

Course Outline Course Calendar

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ASIC vs Standard IC
Standard ICs ICs sold as Standard Parts
SSI/LSI/ MSI IC such as MUX, Encoder, Memory Chips, or Microprocessor IC

Application Specific Integrated Circuits (ASIC) A

Chip for Toy Bear, Auto-Mobile Control Chip, Different Communication Chips [ GRoT: ICs not Found in Data Book]

Concept Started in 1980s

An IC Customized to a Particular System or Application Custom ICs Digital Designs Became a Matter of Placing of Fewer CICs or ASICs plus Some Glue Logic Reduced Cost and Improved Reliability Chip for PC or a Modem

Application Specific Standard Parts (ASSP) Controller

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Types of ASICs
Full-Custom ICs/Fixed ASICs and Programmable ASICs
Wafer : A circular piece of pure silicon (10-15 cm in dia, but
wafers of 30 cm dia are expected soon-IEEE microSep/Oct. 1999, pp 34-43)

Wafer Lot: 5 ~ 30 wafers, each containing hundreds of

chips(dies) depending upon size of the die

Die:

A rectangular piece of silicon that contains one IC design Mask Layers: Each IC is manufactured with successive mask layers(10 15 layers) First half-dozen or so layers define transistors Other half-dozen or so define Interconnect

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Types of ASICs Contd

Full-Custom ASICs: Possibly all logic cells and all mask layers customized
Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all)
mask layers customized
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Types of ASICs Contd

Full-Custom ASICs
Include some (possibly all) customized logic cells
Have all their mask layers customized Full-custom ASIC design makes sense only When no suitable existing libraries exist or
Existing library cells are not fast enough or The available pre-designed/pre-tested cells consume too much power that a design can allow or The available logic cells are not compact enough to fit or ASIC technology is new or/and so special that no cell library exits.

Offer highest performance and lowest cost (smallest die size) but at the
expense of increased design time, complexity, higher design cost and higher risk.

Some Examples: High-Voltage Automobile Control Chips, Ana-Digi

Communication Chips, Sensors and Actuators
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Types of ASICs Contd

Semi-Custom ASICs
Standard-Cell based ASICs
(CBIC- sea-bick) Use logic blocks from
standard cell libraries, other mega-cells, full-custom blocks, system-level macros(SLMs), functional standard blocks (FSBs), cores etc. Get all mask layers customized- transistors and interconnect Manufacturing lead time is around 8 weeks Less efficient in size and performance but lower in design cost

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Types of ASICs Contd

Semi-Custom ASICs Contd Standard-Cell based ASICs
(CBIC- sea-bick) Contd

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Types of ASICs Contd

Semi-Custom ASICs Contd
Gate Array based ASICs

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Types of ASICs Contd

Semi-Custom ASICs Contd
Gate Array based ASICs - Contd

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Types of ASICs Contd

Semi-Custom ASICs Contd
Programmable ASICs PLDs - PLDs are low-density devices
which contain 1k 10 k gates and are available both in bipolar and CMOS technologies [PLA, PAL or GAL]

CPLDs or FPLDs or FPGAs FPGAs combine architecture of gate arrays with programmability of PLDs.

User Configurable Contain Regular Structures circuit elements such as AND, OR, NAND/NOR gates, FFs, Mux, RAMs, Allow Different Programming Technologies Allow both Matrix and Rowbased Architectures

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Types of ASICs Contd

Semi-Custom ASICs Contd
Programmable ASICs - Contd Structure of a CPLD / FPGA

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Why FPGA-based ASIC Design?

Choice is based on Many

Factors ;

Requirement FPGA/FPLD Discrete Logic Custom Logic

Speed Gate Density Development Time Prototyping and Simulation Time Manufacturing Lead Time Future Modifications Inventory Risk Cost

Speed Gate Density Cost

Development Time

Prototyping and Sim.

Manufacturing

Future Modification Inventory Development Tools

Very Effective

Adequate

Poor

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Different Categorizations of FPGAs

Based on Functional Unit/Logic Cell Structure
Transistor Pairs Basic Logic Gates: NAND/NOR MUX Look up Tables (LUT) Wide-Fan-In AND-OR Gates

Programming Technology
Anti-Fuse Technology SRAM Technology EPROM Technology

Gate Density Chip Architecture (Routing Style)

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Different Types of Logic Cells

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Different Types of Logic Cells Contd

Xilinx XC4000 CLB Structure

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Different Types of Logic Cells Contd

Actel Act Logic Module Structure
Use Antifuse Programming Tech. Based on Channeled GA Architecture Logic Cell is MUX which can be configured as multi-input logic gates

The Actel ACT 2 and ACT 3 Logic Modules. (a) The CModule for combinational logic. (b) The ACT 2 S-Module. (c) The ACT 3 S-Module. (d) The equivalent circuit (without buffering) of the SE (sequential element). (e) The sequential element configured as a positive-edgetriggered D flip-flop. (Source: Actel.)

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Different Types of Logic Cells Contd

Altera Flex / Max Logic Element Structure
Flex 8k/10k Devices SRAM Based LUTs, Logic Elements (LEs) are similar to those used in XC5200 FPGA

The Altera MAX architecture. (a) Organization of logic and interconnect. (b) A MAX family LAB (Logic Array Block). (c) A MAX family macrocell. The macrocell details vary between the MAX familiesthe functions shown here are closest to those of the MAX 9000 family

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Different Types of Logic Cells Contd

To SUMMARIZE, FPGAs from various
vendors differ in their

Architecture (Row Based or Matrix

Based Routing Mechanism)

Gate Density (Cap. In Equiv. 2- Input

NAND Gates)

Basic Cell Structure Programming Technology

Vendor/ Product
Actel QuickLogic Xilinx Altera Concurrent Plessy

Architechture Capacity Basic Cell Programming Technology

Gate Array Matrix Matrix Extended PLA Matrix SOG 2-8 k 1.2-1.8 k 2-10 k 1- 5 k 3-5 k 2-40 k MUX MUX RAM Block PLA XOR, AND NAND Antifuse Antifuse SRAM EPROM SRAM SRAM

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Programming Technologies
Three Programming Technologies
The Antifuse Technology Static RAM Technology EPROM and EEPROM Technology

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Programming Technologies Contd

The

Antifuse Technology

Invented at Stanford and developed by Actel Opposite to regular fuse Technology Normally an open circuit until a programming current (about 5 mA) is forced through it Two Types:
Actels PLICE [Programmable Low-Impedance Circuit Element]- A High-Resistance Poly-Diffusion Antifuse QuickLogics Low-Resistance metal-metal antifuse [ViaLink] technology
Direct metal-2-metal connections Higher programming currents reduce antifuse resistance

[a]

[b]

[c]

[d]

Actel Antifuse [b] Actel Antifuse Resistance [c] QuickLogic Antifuse [d] QL Antifuse Resistance

Disadvantages:
Unwanted Long Delay OTP Technology

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Programming Technologies Contd

Static RAM Technology
SRAM cells are used for
As Look-Up Tables (LUT) to implement logic (as Truth Tables) As embedded RAM blocks (for buffer storage etc.) As control to routing and configuration switches

Advantages
Allows In-System Programming (ISP) Suitable for Reconfigurable HW

Disadvantages
Volatile needs power all the time / use PROM to download configuration data CSE 324 FPGA based System Design-Introduction

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Programming Technologies Contd

EPROM and EEPROM Technology-

EPROM Cell is almost as small as Antifuse Floating-Gate Avalanche MOS (FAMOS) Tech.
Under normal voltage, transistor is on With Programming Voltage applied, we can turn it off (configuration) to implement our logic Exposure to UV lamp (one hour) we can erase the programming Use EEPROM for quick reconfiguration, also, ISP possible NDG-L01-2 CSE 324 FPGA based System Design-Introduction 23

Programming Technologies Contd

Summary Sheet

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Chip Architecture or Routing Style

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Chip Architecture or Routing Style Contd

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Chip Architecture or Routing Style Contd

Trade-off between Longer and Shorter Tracks Explained Through Example

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ASIC Design Process

S-1 Design Entry: Schematic entry or HDL description S-2: Logic Synthesis: Using Verilog HDL or VHDL and Synthesis tool, produce a netlistlogic cells and their interconnect detail S-3 System Partitioning: Divide a large system into ASIC sized pieces

S-4 Pre-Layout Simulation: Check design functionality

S-5 Floorplanning: Arrange netlist blocks on the chip S-6 Placement: Fix cell locations in a block S-7 Routing: Make the cell and block interconnections S-8 Extraction: Measure the interconnect R/C cost S-9 Post-Layout Simulation

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ASIC Design Process Contd

Altera FPGA Design Flow A Self-Contained
System that does all from Design Entry, Simulation, Synthesis, and Programming of Altera Devices

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ASIC Design Process Contd

Xilinx FPGA Design Flow Allows Third-Party Design Entry SW,
Accepts their generated netlist file as an input

Use Pin2xnf and wir2xnf SW to

convert the netlist file to .XNF

xnfmap and xnfmerge programs

convert .xnf files to create a unified netlist file (Nand/Nor Gates) .MAP file are generated

map2lca program does fitters job,

produces un-routed .LCA file

apr or ppr SW does the routing

job, post-layout netlist generated

makebits SW generates BIT files

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