Scribd
Upload
2K views

Digital System Design Questions

This document contains questions for a digital system design exam. It asks students to answer one question fully and four other questions partially. The questions cover topics like: - Proving properties of Boolean logic functions - Designing combinational logic circuits like adders and multipliers - Programmable logic devices like PALs, FPGAs, and their components - Modeling circuits using VHDL and simulating behavior - Designing synchronous counters with flip-flops - Algorithmic state machines and designing controllers

Uploaded by

vijay4u4all
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
2K views

Digital System Design Questions

This document contains questions for a digital system design exam. It asks students to answer one question fully and four other questions partially. The questions cover topics like: - Proving properties of Boolean logic functions - Designing combinational logic circuits like adders and multipliers - Programmable logic devices like PALs, FPGAs, and their components - Modeling circuits using VHDL and simulating behavior - Designing synchronous counters with flip-flops - Algorithmic state machines and designing controllers

Uploaded by

vijay4u4all
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

C13-R3: DIGITAL SYSTEM DESIGN NOTE: 1. 2. Answer question 1 and any FOUR questions from 2 to 7.

Parts of the same question should be answered together and in the same sequence. Total Marks: 100

Time: 3 Hours 1. a)

b) c) d) e) f) g)

The following calculation was performed by a particular breed of unusually intelligent chicken. If the radix r used by the chicken corresponds to its total number of toes, how many toes does the chicken have on each foot? ((35)r + (24)r ) x (21)r = (1501)r Prove that the dual of the exclusive-OR is also its complement. Design a combinational circuit that multiplies by 5 an input decimal digit represented in BCD. The output is also in BCD. Show that the outputs can be obtained from the input lines without using any logic gates. Define programmable Array Logic (PALs). How are they characterized? In VHDL, there are two types of delay that can be used for modelling behaviour. Taking a suitable example, explain each of them in brief. Datapaths provide connections between components in the system and are classified according to different features. Explain each feature of the datapath in brief. Which are the programmable elements of FPGA module? Explain the functions of each of them in brief. (7x4) Implement the four Boolean functions listed using three half-adder circuits D=ABC E = ABC + ABC F = ABC + ( A + B ) C G = ABC A combinational circuit is specified by the following three Boolean functions: F1 = X + Y + XYZ F2 = X + Y + XYZ F3 = XYZ + X + Y Design the circuit with a decoder and external OR gates. Design a synchronous mod-6 counter whose counting sequence is 000, 010, 011, 110, 101, 001, 000 etc. Use clocked JK flip-flops. (4+4+10) Find a logic diagram representing minimum 2-level logic needed to implement the VHDL dataflow description give below. Note that complemented inputs are available. -- Combinational Circuit 2: Dataflow VHDL Description - library ieee; use ieee. std_logic_1164. all; entity comb_ckt_2 is port (a, b, c, d, a_n, c_n, d_n: in std_logic; f, g: out std_logic); -- a_n, b_n, .. are complements of a, b, , respectively. end comb_ckt_2;

2. a)

b)

c)

3. a)

C13-R3

Page 1 of 3

July, 2008

architecture dataflow_1 of comb_ckt_2 is begin f <= b and (a or (a_n and c)) or (b_n and c and d_n); g <= b and (c or (a_n and c_n)) or (c_n and d_n); end dataflow_1;

C13-R3

Page 2 of 3

July, 2008

b)

Write a dataflow description for the circuit in Figure given below by using the Boolean equation for the output F.

(9+9) 4. a) b) Simulate the 4 x 1 MUX using Behavioral Style Modeling. For the following expressions: f1 (x, y, z) = m (1, 2, 4, 5, 7) f2 (x, y, z) = m (0, 1, 3, 5, 7) Illustrate the use of PAL to realize combinational logic. (9+9) 5. a) A sequential circuit with two D flip-flops A and B, two inputs X and Y, and one output Z is specified by the following input equations: DA = XY + XA DB = XB + XA Z = XB i) Draw the logic diagram of the circuit. ii) Derive the state table iii) Derive the state diagram A one-digit BCD adder using FPGA module is to be designed. Write high-level specifications of the system. Draw a scheme that uses two binary adders. Show the steps only for FPGA implementation. (9+9) ROM modules can be classified according to the way that their contents (the values of the constant bit-vectors) are set. Explain this classification and discuss the advantages and disadvantages of each of them. Consider sequential system described by the following tabular representation (the combination x1x0 = 00 never appears, so it is considered a dont care case): Input: Output: State: Function: PS y1y0 00 01 10 01 01,0 00,0 11,0 x = (x1, x0), xi {0, 1} z {0, 1} y = (y1, y0), yi {0, 1} The transition and output function are x1x0 10 10,1 11,1 10,0 11 10,0 11,0 00,1

b)

6. a) b)

C13-R3

Page 3 of 3

July, 2008

11

10,0

00,0

11,1

Show a ROM-based implementation of this system, including ROM contents. (8+10)

C13-R3

Page 4 of 3

July, 2008

7. a) b)

ASM (Algorithmic State Machine) is a controller for the logic design of a digital system and is regarded as a hardware algorithm. Show the general model of an ASM and explain the working of each functional block. Consider a design example of a parallel (unsigned) 4-bit binary multiplier. i) Draw a possible system architecture diagram for the binary multiplier, showing different components, which are required for the design. ii) Mention the signals associated with its controller and draw an ASM chart for the same. (6+12)

C13-R3

Page 5 of 3

July, 2008

You might also like