KADUNA STATE UNIVERSITY

FACULTY OF SCIENCE
DEPARTMENT OF MATHEMATICAL SCIENCE

CSC 305: COMPUTER ARCHITECTURE AND ORGANIZATION

QUESTION: Assuming the CPU is performing the operation MOV Addr0002 to Addr0005, and then received an interrupt with higher priority i.e. OUT R5 Dev6 i.e. to a Printer, upon executing the interrupt, a new interrupt with higher priority was received IN R6 Dev5 i.e. a Keyboard. Show how the CPU executes all these instructions with the aid of a stack.

BY

KABIR JAAFAR ABUBAKAR KASU/09/CSC/1004

INTRODUCTION

The temporary stopping of the current program routine, in order to execute some higher priority I/O subroutine, is called an interrupt. The interrupt mechanism in the CPU forces a branch out of the current program routine to one of the several subroutines, depending upon which level of interrupt occurs. It is often necessary to have the normal flow of a program interrupted, for example, to react to abnormal events, such as power failure. An interrupt can also be used to acknowledge the completion of a particular course of action, such as a printer indicating to the computer that it has completed printing the character(s) in its input register and that it is ready to receive other character(s). An interrupt can also be used in time-sharing systems to allocate CPU time among different programs. The instruction sets of modern CPUs often include instruction(s) that mimic the actions of the hardware interrupts. When the CPU is interrupted, it is required to discontinue its current activity, attend to the interrupting condition (serve the interrupt), and then resume its activity from wherever it stopped. Discontinuity of the processors current activity requires finishing executing the current instruction, saving the processor status (mostly in the form of pushing register values onto a stack), and transferring control (jump) to what is called the interrupt service routine (ISR). The service offered to an interrupt will depend on the source of the interrupt. For example, if the interrupt is due to power failure, then the action taken will be to save the values of all processor registers and pointers such that resumption of correct operation can be guaranteed upon power return. In the case of an I/O interrupt, serving an interrupt means to perform the required data transfer. Upon finishing serving an interrupt, the processor should restore the original status by popping the relevant values from the stack. Once the processor returns to the normal state, it can enable sources of interrupt again.

SERVING MULTIPLES INTERRPTS

But for serving multiple interrupts, for example, the occurrence of yet another interrupt while the processor is currently serving an interrupt. Response to the new interrupt will depend upon the priority of the newly arrived interrupt with respect to that of the interrupt being currently served. If the newly arrived interrupt has priority less than or equal to that of the currently served one, then it can wait until the processor finishes serving the current interrupt. If, on the other hand, the newly arrived interrupt has priority higher than that of the currently served interrupt, for example, power failure interrupt occurring while serving an I/O interrupt, then the processor will have to push its status onto the stack and serve the higher priority interrupt.

Instruction cycle with interrupt Correct handling of multiple interrupts in terms of storing and restoring the correct processor status is guaranteed due to the way the push and pop operations are performed. For example, to serve the first interrupt, STATUS 1(the current program) will be pushed onto the stack. Upon receiving the second interrupt, STATUS 2 will be pushed onto the stack. Upon serving the second interrupt, STATUS 2 will be popped out of the stack and upon serving the first interrupt, STATUS 1 will be popped out of the stack. However, when the CPU is performing the operation MOV Addr0002 to Addr0005, and an interrupt with higher priority i.e. OUT R5 Dev6, i.e. to
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a printer arrived, the current execution will have to halt and be push onto the stack and process the interrupt. Upon serving the interrupt, another interrupt with higher priority was received IN R6 Dev5 i.e. a keyboard, in this case since this interrupt has a higher priority, the current interrupt will have to halt and be push onto the stack and then execute the interrupt with higher priority. And upon finished the execution of the interrupt the previous status of the processor will be popped out of the stack and continued from where it stopped, and upon finished the execution of that interrupt, the processor will then restore it normal status.

Simple representation of a stack

CONCLUSION

The entire operation took place within the CPU and it is called CPU execution cycle. A typical CPU has three major components: register set, arithmetic logic unit (ALU), and control unit (CU). The register set differs from one computer architecture to another. It is usually a combination of generalpurpose and special-purpose registers. General-purpose registers are used for any purpose, hence the name general purpose. Special-purpose registers have specific functions within the CPU. For example, the program counter (PC) is a special-purpose register that is used to hold the address of the instruction to be executed next. Another example of specialpurpose registers is the instruction register (IR), which is used to hold the instruction that is currently executed. The ALU provides the circuitry needed to perform the arithmetic, logical and shift operations demanded of the instruction set. The control unit is the entity responsible for fetching the instruction to be executed from the main memory and decoding and then executing it.
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The CPU fetches instructions from memory, reads and writes data from and to memory, and transfers data from and to input/output devices. A typical and simple execution cycle can be summarized as follows: 1. The next instruction to be executed, whose address is obtained from the PC, is fetched from the memory and stored in the IR. 2. The instruction is decoded. 3. Operands are fetched from the memory and stored in CPU registers, if needed. 4. The instruction is executed. 5. Results are transferred from CPU registers to the memory, if needed. The execution cycle is repeated as long as there are more instructions to execute.

Central processing Unit main components and interaction with the memory and I/O.

A check for pending interrupts is usually included in the cycle. Examples of interrupts include I/O device request, arithmetic overflow, or a page fault. When an interrupt request is encountered, a transfer to an interrupt handling routine takes place. Interrupt handling routines are programs that are invoked to collect the state of the currently executing program, correct
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the cause of the interrupt, and restore the state of the program. The actions of the CPU during an execution cycle are defined by micro-orders issued by the control unit. These micro-orders are individual control signals sent over dedicated control lines.

REFERENCE

- Wikipedia (2012) - M. Abd-el-barr and H. El-Rewini, Fundamentals Computer Organization and Architecture, A John Wiley and Sons, Inc Publication (2005).