Dealing with PLL clock jitter in advanced processor designs

Part 1: Defining clock jitter terminology By Boris Lerner and Aaron Lowenberger, Analog Devices
In this first of a three part series published on Embedded.com, engineers at Analog Devices, Inc. examine the sources of clock jitter in designs based on advanced RISC and DSP architectures, how to characterize your system for such problems and then how to resolve them.

With the advance of faster processors that require faster lines of communication, understanding and characterizing clock jitter has become more important. Jitter occurs in many different parts of digital applications. Jitter of data with respect to clock in synchronous protocols is one example; jitter of the signal itself in CDR (clock data recovery) applications is another. While there are infinitely many types of jitter and several ways of measuring it, the choices available and the alternatives that the designer must consider can be narrowed significantly by defining his or her domain a bit more precisely: 1. Modern high-speed processors care about how short a clock pulse may become due to jitter before it violates the processors guard-banded frequency spec. (Note that the processors PLL usually has a jitter frequency transfer function which needs to be taken into account. It is the clock that comes out of the PLL that must abide by the frequency spec). Looking at the definitions of the jitter measurements, it is clear that the processor is concerned about the period jitter. 2. When characterizing the jitter frequency transfer function of the processors PLL, processor manufacturers often use the lab setup described above (i.e., they really measure TIE jitter). 3. Clock driver and oscillator manufacturers do not artificially generate, but rather measure jitter and usually specify it as cycle-to-cycle. The hardware design engineer, who is faced with three seemingly incompatible definitions, throws in a towel, goes back to school, gets an MBA and joins the marketing department instead. Or (and this happens at least as often), the engineer simply designs the board without checking the jitter specs and hopes that it works. The purpose of this article is to make such issues less complex and to remove this uncertainty by examining the jitter issues of the clock from which PLL-based processors derive timing as well as analyze the given clock's jitter with respect to an ideal clock, to the degree that the processors tolerance requires. While the issues relating to jitter are examined using a specific processor, the ADSPTS201S TigerSHARC, much of the discussion also applies to jitter in general and to many PLL-based processor designs. Unfortunately, unlike more traditional data sheet parameters like setup and hold, analyzing acceptable system jitter is not as simple as merely ensuring that specification numbers are met. There are many ways to measure jitter. On top of that, there are

infinitely many different kinds of jitter and the system may behave differently depending on the jitter type. Thus, before doing any analysis whatsoever, it is important to carefully delineate all of the jitter terms and definitions, first intuitively what they mean, and then the correct mathematical definition.

Terminology
An ideal clock that is being jittered is one in which the clocks edges experience movement with respect to ideal locations. The jitter of a particular waveform can be measured/characterized as period, cycle-tocycle, or time interval error (TIE). Period jitter. This measures the maximum deviation of each single period of the jittered clock from that of the ideal clock. In Figure 1 below, if C 0 = Period of Ideal clock, then (1) Period Jitter = max

k =0 ,1, 2 , 3,...

{P

C 0 }.

Cycle-to-cycle jitter. This measures the maximum deviation of each single period of the jittered clock from the previous period of the same clock. In Figure 1, then, (2) Cycle - to - Cycle Jitter = max
k =0 ,1, 2 , 3,...

{P

k +1

Pk }.

Time interval jitter. This measures the maximum deviation of the edge. Figure 1 shows this relating to the rising edge; it can also relate to the falling edge) of the jittered clock from the corresponding edge of the ideal clock. In Figure 1, then, (3) TIE Jitter = max {Tk }
k =0 ,1, 2 , 3,..

Figure 1. Jitter definitions Here we presume that at time t=0 of the measurement, the edge of the jittered clock aligns with the edge of the ideal clock. Note that this is not just a simple aberration of the edge of the jittered clock from the nearest edge of the ideal clock, because the edge of the

jittered clock may have wandered away from the edge of the ideal clock by more than a full cycle period. It is time to put clock and jitter under a more precise mathematical definition. We define the ideal clock of period T and constant amplitude A as the following function of time t:
1 if nT t < n + T A 2 (4) C A,T (t ) = Here, T is measured in units of time 0 if n + 1 T t < (n + 1)T 2 (usually seconds) and A is measured in volts. Amplitude of the ideal clock is irrelevant to the discussion about jitter, so in all that follows we presume that the clocks have unit amplitude and we consider them as parameterized by T, (i.e., their period):
1 CT (t ) = 0 1 if nT t < n + T 2 1 if n + T t < (n + 1)T 2

(5)

We also define C J ,T (t ) , the clock of period T with jitter J(t), as the ideal clock delayed by a function of time J(t) (delay can be positive or negative), mathematically:
(6) C J ,T (t ) = CT (t J (t ))

There are several intuitive reasons for defining jitter this way. The most compelling reason is that jitter is usually generated in a laboratory by applying a function generator signal to a delay input of a pulse generator. This is the way processor manufacturers test susceptibility to jitter. For simplicity we define (7) G (t ) := t J (t ) , so that C J ,T (t ) = CT (G (t )) .

Note that G(t) matters only at points

1 t = rk or f k where G(rk ) = kT andG( f k ) = k + T. 2

since G cannot change the order of the edges, only their locations. Going back to Figure 1, we see that

Tk = J (kT ) .

Thus, these definitions naturally lend themselves to specifying jitter as TIE (simply because the maximum amplitude of J(t) is the TIE jitter, as defined in equation (3)). Unfortunately, clock driver manufacturers do not typically specify jitter as TIE. Thus, it becomes important to relate different types of jitter with mathematical formulas. This is the main reason for this application note.

Jitter Examples
Lets take a pause from this mild mathematical onslaught and examine different examples of jitter as consequences of our definitions.

Example 1
J (t ) = , where

is a small real number. Then

C J ,T (t ) = C T (t ) , which shift of the original

ideal clock.

Example 2
J (t ) = t , where is a small real number. Then C J ,T (t ) = CT ((1 )t ) , which is another ideal clock of lower (if > 0) or higher (if < 0) frequency. In fact, its period is Pk =
Period Jitter = T , the same for all k. 1

T T T = , 1 1

Cycle - to - Cycle Jitter = 0, TIE Jitter = .

Intuitively, function J(t) is slowly increasing (or decreasing, depending on the sign of epsilon), and the edges shift uniformly. Note that infinite TIE jitter implies that this jitter cannot be generated by laboratory setup described above; it would require the function generator to output a signal of infinite amplitude. For the same reason, this type of jitter does not occur in real-life systems, so we will restrict our attention to jitter of finite amplitude.

Example 3
J (t ) = A sin( 2 f 0 t ) This type of jitter is appropriately called the sinusoidal jitter of frequency f 0 . In this case, TIE jitter (which, as noted before, is the maximum amplitude of J) is A. Deriving period and cycle-to-cycle jitter is not as trivial as in Example 1, and derivation of period jitter will be done in a following section.

Example 4
J (t ) = C A,T0 (t ) , another ideal clock of period T0 and amplitude A. It is easy to see that J(t) delays the original clock by A or does not delay it at all. Thus, provided that T0 is reasonably smaller than T, Period Jitter = A Cycle-to-Cycle Jitter = A TIE Jitter = A

Example 5
J(t) = White Gaussian noise. The implications of this jitter type on period, cycle-to-cycle, and TIE jitter are postponed to a later section of this series of articles, when we discuss general case jitter. Boris Lerner is senior DSP applications engineer and Aaron Lowenberger is a product engineer working on DSPs at Analog Devices Inc.
In Part 2 of this series the authors cover Dealing with jitter frequency domain transfer functions through a PLL. The topic of Part 3 is Guidelines for measuring TIE jitter.