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Paro: A Design Tool For Synthesis of Hardware Accelerators For Socs

90% of high performance applications are spent in nested loop programs which offer a tremendous potential of acceleration due to inherent parallelism. The major goal of the PARO tool developed at the University of Erlangen-Nuremberg is automatic generation of (a)hardware accelerators for FPGAs. The methodology is based on the intuitive and efficient parallelization in the polytope model.

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55 views1 page

Paro: A Design Tool For Synthesis of Hardware Accelerators For Socs

90% of high performance applications are spent in nested loop programs which offer a tremendous potential of acceleration due to inherent parallelism. The major goal of the PARO tool developed at the University of Erlangen-Nuremberg is automatic generation of (a)hardware accelerators for FPGAs. The methodology is based on the intuitive and efficient parallelization in the polytope model.

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lovelyswetha_2005
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PARO: A Design Tool for Synthesis of Hardware Accelerators for SoCs


Hritam Dutta, Frank Hannig, and Jrgen Teich

It is a known fact that 90% of the execution time of high performance applications are spent in nested loop programs which offer a tremendous potential of acceleration due to inherent parallelism. Furthermore, streaming applications consisting of multiple communicating loops from elds of signal processing, medical imaging, nancial computing require high performance computing. The FPGAs offer huge amounts of resources for realization of massively parallel hardware accelerators. The major goal of the PARO tool developed at the University of Erlangen-Nuremberg is automatic generation of (a)hardware accelerators for FPGAs from algorithms (especially nested loops) descriptions [3], (b) accelerator pipeline, and (c) interface circuits and drivers for system integration. The methodology is based on the intuitive and efcient parallelization in the polytope model [2]. There exists only a few tools for hardware generation like PICO from Synfora that are also based on the polytope model. The design trajectory of PARO is shown in Fig. 1. The novelty of the tool design ow is summarized as follows:

Algorithm Description (PAULA)

Simulation

High Level Transformation Toolbox Loop Optimizations Expression Splitting Localization Output Normal Form Tiling

Front End

Performance Analysis Architecture Model

Allocation

Space-time mapping Scheduling Resource Binding

Back End

Interface Generation Device Driver Memory Map Hardware Wrapper

Controller

Hardware Synthesis Processor Array I/O Processor Element

WSDF Conversion Multidimensional FIFO Generation

Simulation Testbench Generation

Backend SW and HDL Generation(C, VHDL)

Accelerator Subsystem for MPSoC

Fig. 1.

Design ow for mapping algorithms to hardware accelerators.

For design entry, a new language for dataow-based algorithm description as communicating nested loops is used. The language can be used both for behavioral description as well as architecture description. New multilevel partitioning technologies for balancing memory hierarchies and communication requirements. Several other advanced transformations like localization and standard compiler optimizations like common subexpression elimination, and others [5] are also available in the high level transformation toolbox for obtaining amenable algorithm description in terms of data reuse and resource usage. Scheduling based on Mixed Integer Linear Programming (MILP) with modeling of resource constraints, speculative execution, software and functional pipelining [4]. Functional simulation and Modelsim simulation at different levels of design ow for validation. Automated synthesis of communication subsystem for communication between accelerators in a pipeline based on a novel dataow model of computation. Automated generation of memory map, interface circuits and device driver for integration of accelerators in SoC architectures. Design space exploration The PARO backend produces an intermediate RTL representation which is retargeted to VHDL. Compact and intuitive representation (big operators like

, ) of input algorithm in the language. Optimal hardware generation in terms of performance, leveraging the available parallelism in the algorithm with respect to resource constraints. Automatic generation of an Input/Output interface for the hardware accelerator for integration in System-on-Chip on an FPGA. State-of-the-art medical imaging applications from industry have been successfully synthesized with PARO tool [1].

R EFERENCES
[1] Hritam Dutta, Frank Hannig, Jrgen Teich, Benno Heigl, and Heinz Hornegger. A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. In Proceedings of IEEE 17th International Conference on Application-specic Systems, Architectures, and Processors (ASAP), pages 331337, Steamboat Springs, CO, USA, September 2006. IEEE Computer Society. [2] Paul Feautrier. Automatic Parallelization in the Polytope Model. Technical Report 8, Laboratoire PRiSM, Universit des Versailles St-Quentin en Yvelines, 45, avenue des tats-Unis, F-78035 Versailles Cedex, June 1996. [3] Frank Hannig, Holger Ruckdeschel, Hritam Dutta, and Jrgen Teich. PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataow-Intensive Applications. In Proceedings of the Fourth International Workshop on Applied Recongurable Computing (ARC), volume 4943 of Lecture Notes in Computer Science (LNCS), pages 287293, London, United Kingdom, March 2008. Springer. [4] Frank Hannig and Jrgen Teich. Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. In Proceedings of the 15th IEEE International Conference on Application-specic Systems, Architectures, and Processors (ASAP 2004), pages 1727, Galveston, TX, U.S.A., September 2004. [5] Steven Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 1997.

Advantages of the tool as compared to other tools lies in

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