American International University- Bangladesh (AIUB)
Faculty of Engineering
Course Name: VLSI Circuit Design Course Code: EEE 4217
Semester: Summer 2024-25 Term: Mid
Total Marks: 10 Submission Date: 15-08-2025
Instructor Name: Dr. Shahriyar Masud Rizvi Assignment: 01
Course Outcome Mapping with Questions
Obtained
Item COs POIs K P A Marks
Marks
Q1 CO2 P.a.4.C3 K4 P1, P3, P7 10
Total: 10
Student Information:
Student Name: Student ID:
Section: C Department:
Marking Rubrics (to be filled by Faculty):
Excellent Proficient Good Acceptable Unacceptable No Response
[10] [8-9] [6-7] [4-5] [1-3] [0]
Detailed unique No
response Response with no Response shows Partial problem is Unable to clarify Response/(Copi
Secured
Problem # explaining the apparent errors understanding of solved; response the understanding ed/identical
Marks
concept properly and the answer is the problem, but indicates part of of the problem submissions
and answer is correct, but the final answer the problem was and method of the will be graded
correct with all explanation is not may not be not understood problem solving as 0 for all
works clearly adequate/unique. correct clearly. was not correct parties
shown. concerned)
1
Total marks
Comments (10)
1. Apply the concept of the n-well CMOS process to construct photomask layers for fabricating an inverter
whose architecture is shown below. Show the relevant cross sections. [10]
ID (middle 5 bits) Figure No. Pull-down device Pull-up device
ID <= A Figure 1 NMOS with gate connected to input NMOS with gate connected to Vdd
signal
A < ID <= B Figure 2 NMOS with gate connected to input NMOS with gate and source
signal Shorted
B < ID <= C Figure 3 NMOS with gate connected to input PMOS with gate and drain shorted
signal
C < ID <= D Figure 4 NMOS with gate connected to input PMOS with gate connected to
signal ground
ID > D Figure 5 NMOS with gate and drain shorted PMOS with gate connected to input
signal
A = 46150, B = 47270, C = 47442, D = 47580
Figure 1 Figure 2
Figure 3 Figure 4
Figure 5
ID : 21-45558-3
Middle digits are 45558
A = 46150
Schematic Design
• M1 (PD NMOS): drain → Vout, source → GND, gate → Vin
• M2 (PU NMOS): drain → Vdd, source → Vout, gate → Vdd (always-on load)
• Substrate taps: p+ taps to GND placed near every NMOS active region.
Note: This is not complementary CMOS; both devices are NMOS in a p type substrate. It still follow the n well
CMOS mask set, but it will not place any PMOS or n well for this figure.
So,
• The pull-up device is an NMOS transistor with its gate permanently connected to VDD.
• The pull-down device is an NMOS transistor whose gate is controlled by the input signal.
• Since the pull-up NMOS acts like a weak resistor, it cannot drive strongly.
• The HIGH output level does not reach the full VDD value but instead rises only up to VDD – VTH (the
threshold voltage drop).
• This configuration results in static power dissipation, as current flows simultaneously through both
transistors whenever the input is at logic 0.
VDD
VOUT
Vin
Vss
Stick Diagram (NMOS Inverter) :
VDD
VOut
Vin
GND
Layout (NMOS Inverter) :
NMOS Fabrication Process :
Thick SiO2
1 µm
The figures presented illustrate the complete design flow of an NMOS-based inverter, starting from the schematic to
the fabrication cross-section. The schematic diagram defines the basic circuit configuration, where the pull-down
NMOS transistor is controlled by the input signal while the pull-up NMOS transistor is permanently tied to VDD,
forming an enhancement-load inverter. The stick diagram then provides a simplified layout view, highlighting the
logical connections of diffusion, polysilicon, and metal layers before moving into the actual physical design. This
abstraction helps visualize the relative positioning of components while reducing layout complexity. The layout
diagram represents the physical implementation, showing the placement of active regions, polysilicon gates,
contacts, and interconnects in compliance with design rules, ensuring the circuit is realizable on silicon. Finally, the
fabrication cross-section illustrates the NMOS process steps, including the formation of field oxide, gate oxide,
polysilicon, and metal layers, which demonstrate how the conceptual design is translated into a real semiconductor
structure. Together, these figures provide a comprehensive understanding of the inverter’s design at different
abstraction levels—circuit, symbolic representation, physical layout, and fabrication—highlighting both the
theoretical and practical aspects of VLSI design.
