CHAPTER

Cortex-M3 Basics

IN THIS CHAPTER
Registers ................................................................................................................................................ 2 5
Special Registers ................................................................................................................................... 2 9
Operation Mode ...................................................................................................................................... 3 2
Exceptions and Interrupts ........................................................................................................................ 3 5
Vector Tables ......................................................................................................................................... 3 6
Stack Memory Operations ....................................................................................................................... 3 6
Reset Sequence ...................................................................................................................................... 4 0

3.1 REGISTERS
®

3.1.1 General Purpose Registers R0 through R7

low registers

3.1.2 General Purpose Registers R8 through R12

high registers

25
26 CHAPTER 3 Cortex-M3 Basics

Name Functions (and banked registers)

R0 General purpose register
R1 General purpose register
R2 General purpose register
R3 General purpose register
Low registers
R4 General purpose register
R5 General purpose register
R6 General purpose register
R7 General purpose register
R8 General purpose register
R9 General purpose register
R10 General purpose register High registers
R11 General purpose register
R12 General purpose register
R13 (MSP) R13 (PSP) Main Stack Pointer (MSP), Process Stack Pointer (PSP)
R14 Link Register (LR)
R15 Program Counter (PC)

xPSR Program status registers

PRIMASK
FAULTMASK Interrupt mask Special
registers registers
BASEPRI
CONTROL Control register

FIGURE 3.1
Registers in the Cortex-M3.

3.1.3 Stack Pointer R13

Main Stack Pointer (MSP) or SP_main in ARM documentation

Process Stack Pointer (PSP) or SP_ process in ARM documentation

 3.1 Registers 27

STACK PUSH AND POP

Stack is a memory usage model. It is simply part of the system memory, and a pointer register (inside the
processor) is used to make it work as a first-in/last-out buffer. The common use of a stack is to save register
contents before some data processing and then restore those contents from the stack after the processing task
is done.

Stack PUSH operation to Stack POP operation to

back up register contents restore register contents
Register
Register contents
contents restored
PUSH Data processing POP
(original register
contents destroyed)
SP

Memory Memory

FIGURE 3.2
Basic Concept of Stack Memory.

When doing PUSH and POP operations, the pointer register, commonly called stack pointer, is adjusted
automatically to prevent next stack operations from corrupting previous stacked data. More details on stack
operations are provided on later part of this chapter.

PUSH {R0} ; R13=R13-4, then Memory[R13] = R0

POP {R0} ; R0 = Memory[R13], then R13 = R13 + 4

subroutine_1
PUSH {R0-R7, R12, R14} ; Save registers
... ; Do your processing
POP {R0-R7, R12, R14} ; Restore registers
BX R14 ; Return to calling function
28 CHAPTER 3 Cortex-M3 Basics

R13, SP
R13/SP

SP_main
SP_process

3.1.4 Link Register R14

R14 LR

main ; Main program

...
BL function1 ; Call function1 using Branch with Link instruction.
; PC = function1 and
; LR = the next instruction in main
...
function1
... ; Program code for function 1
BX LR ; Return

3.1.5 Program Counter R15

0x1000 : MOV R0, PC ; R0 = 0x1004

 3.2 Special Registers 29

3.2 SPECIAL REGISTERS

MRS <reg>, <special_reg>; Read special register

MSR <special_reg>, <reg>; write to special register

3.2.1 Program Status Registers

xPSR

MRS r0, APSR ; Read Flag state into R0

MRS r0, IPSR ; Read Exception/Interrupt state
MRS r0, EPSR ; Read Execution state
MSR APSR, r0 ; Write Flag state

31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0

APSR N Z C V Q

IPSR Exception number

EPSR ICI/IT T ICI/IT

FIGURE 3.3
Program Status Registers (PSRs) in the Cortex-M3.

31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0

xPSR N Z C V Q ICI/IT T ICI/IT Exception number

FIGURE 3.4
Combined Program Status Registers (xPSR) in the Cortex-M3.
30 CHAPTER 3 Cortex-M3 Basics

Table 3.1 Bit Fields in Cortex-M3 Program Status Registers

Bit Description

31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0

ARM
N Z C V Q IT J Reserved GE[3:0] IT E A I F T M[4:0]
(general)

ARM7 TDMI N Z C V Reserved I F T M[4:0]

FIGURE 3.5
Current Program Status Registers in Traditional ARM Processors.

PSR
MRS r0, PSR ; Read the combined program status word
MSR PSR, r0 ; Write combined program state word

3.2.2 PRIMASK, FAULTMASK, and BASEPRI Registers

 3.2 Special Registers 31

Table 3.2 Cortex-M3 Interrupt Mask Registers

Register Name Description

x = __get_BASEPRI(); // Read BASEPRI register

x = __get_PRIMARK(); // Read PRIMASK register
x = __get_FAULTMASK(); // Read FAULTMASK register
__set_BASEPRI(x); // Set new value for BASEPRI
__set_PRIMASK(x); // Set new value for PRIMASK
__set_FAULTMASK(x); // Set new value for FAULTMASK
__disable_irq(); // Clear PRIMASK, enable IRQ
__enable_irq(); // Set PRIMASK, disable IRQ

MRS r0, BASEPRI ; Read BASEPRI register into R0

MRS r0, PRIMASK ; Read PRIMASK register into R0
MRS r0, FAULTMASK ; Read FAULTMASK register into R0
MSR BASEPRI, r0 ; Write R0 into BASEPRI register
MSR PRIMASK, r0 ; Write R0 into PRIMASK register
MSR FAULTMASK, r0 ; Write R0 into FAULTMASK register

3.2.3 The Control Register

CONTROL[1]
32 CHAPTER 3 Cortex-M3 Basics

Table 3.3 Cortex-M3 Control Register

Bit Function

CONTROL[0]

x = __get_CONTROL(); // Read the current value of CONTROL

__set_CONTROL(x); // Set the CONTROL value to x

MRS r0, CONTROL ; Read CONTROL register into R0

MSR CONTROL, r0 ; Write R0 into CONTROL register

3.3 OPERATION MODE

 3.3 Operation Mode 33

Privileged User

Handler mode
When running an exception handler (not allowed)
(CONTROL[1] 0)

When not running an exception handler Thread mode Thread mode

(e.g., main program) (CONTROL[0 ] 0) (CONTROL[0 ] 1)

CONTROL [1] can be either 0 or 1

FIGURE 3.6
Operation Modes and Privilege Levels in Cortex-M3.

Reprogram
Switch to user CONTROL
Privileged mode by writing register
handler to CONTROL
Exception Exception
register handler handler

Privileged Starting Privileged

thread code Exception Exception thread

User thread User User

mode mode

FIGURE 3.7
Switching of Operation Mode by Programming the Control Register or by Exceptions.
34 CHAPTER 3 Cortex-M3 Basics

Privileged Exception Exception

handler handler handler

Privileged Starting Privileged Privileged Privileged

thread code thread thread thread
Exception Exception

User thread
FIGURE 3.8
Simple Applications Do Not Require User Access Level in Thread Mode.

Interrupt
exit
Interrupt service
routine (ISR)
Interrupt
event

Main
program Stacking Unstacking

Time
Thread mode Handler mode Thread mode
(privileged) (privileged) (privileged)

FIGURE 3.9
Switching Processor Mode at Interrupt.

Interrupt
exit
Interrupt service
routine (ISR)
Interrupt
event

Main
program Stacking Unstacking

Time
Thread mode Handler mode Thread mode
(user) (privileged) (user)

FIGURE 3.10
Switching Processor Mode and Privilege Level at Interrupt.
 3.4 Exceptions and Interrupts 35

3.4 EXCEPTIONS AND INTERRUPTS

IRQ

Table 3.4 Exception Types in Cortex-M3

Exception
Number Exception Type Priority Function
36 CHAPTER 3 Cortex-M3 Basics

Table 3.5 Vector Table Definition after Reset

Exception Type Address Offset Exception Vector

3.5 VECTOR TABLES

vector table

3.6 STACK MEMORY OPERATIONS

 3.6 Stack Memory Operations 37

3.6.1 Basic Operations of the Stack

3.6.2 Cortex-M3 Stack Implementation

Main program
...
; R0 = X, R1 = Y, R2 = Z
Subroutine
BL function1

function1
PUSH {R0} ; store R0 to stack & adjust SP
PUSH {R1} ; store R1 to stack & adjust SP
PUSH {R2} ; store R2 to stack & adjust SP
... ; Executing task (R0, R1 and R2
; could be changed)
POP {R2} ; restore R2 and SP re-adjusted
POP {R1} ; restore R1 and SP re-adjusted
POP {R0} ; restore R0 and SP re-adjusted
BX LR ; Return
; Back to main program
; R0 = X, R1 = Y, R2 = Z
... ; next instructions
FIGURE 3.11
Stack Operation Basics: One Register in Each Stack Operation.
38 CHAPTER 3 Cortex-M3 Basics

Main program
...
; R0 = X, R1 = Y, R2 = Z Subroutine
BL function 1
function 1
PUSH {R0-R2} ; Store R0, R1, R2 to stack
... ; Executing task (R0, R1 and R2
; could be changed)
POP {R0-R2} ; restore R0, R1, R2
BX LR ; Return

; Back to main program

; R0 = X, R1 = Y, R2 = Z
... ; next instructions

FIGURE 3.12
Stack Operation Basics: Multiple Register Stack Operation.

Main program
...
; R0 = X, R1 = Y, R2 = Z Subroutine
BL function 1
function 1
PUSH {R0-R2, LR} ; Save registers
; including link register
... ; Executing task (R0, R1 and R2
; could be changed)
POP {R0-R2, PC} ; Restore registers and
; return
; Back to main program
; R0 = X, R1 = Y, R2 = Z
... ; next instructions

FIGURE 3.13
Stack Operation Basics: Combining Stack POP and RETURN.

R0 0x12345678

PUSH {R0}
Occupied Occupied
Memory Occupied Occupied
address Last pushed data SP Occupied
- 0x12345678 SP
- - Stack
grow

FIGURE 3.14
Cortex-M3 Stack PUSH Implementation.
 3.6 Stack Memory Operations 39

Occupied POP {R0} Occupied

Memory Occupied Occupied
address Occupied Occupied
0x12345678 SP 0x12345678 SP
- -

R0 - R0 0x12345678

FIGURE 3.15
Cortex-M3 Stack POP Implementation.

3.6.3 The Two-Stack Model in the Cortex-M3

Interrupt
exit
Interrupt service
Interrupt routine (ISR)
event

Main
program Stacking Unstacking

Time
Thread mode Handler mode Thread mode
(use MSP) (use MSP) (use MSP)

FIGURE 3.16
CONTROL[1] 0: Both Thread Level and Handler Use Main Stack.
40 CHAPTER 3 Cortex-M3 Basics

Interrupt
exit
Interrupt service
routine (ISR)
Interrupt
event

Main
program Stacking Unstacking

Time
Thread mode Handler mode Thread mode
(use PSP) (use MSP) (use PSP)

FIGURE 3.17
CONTROL[1]=1: Thread Level Uses Process Stack and Handler Uses Main Stack.

x = __get_MSP(); // Read the value of MSP

__set_MSP(x); // Set the value of MSP
x = __get_PSP(); // Read the value of PSP
__set_PSP(x); // Set the value of PSP

MRS R0, MSP ; Read Main Stack Pointer to R0

MSR MSP, R0 ; Write R0 to Main Stack Pointer
MRS R0, PSP ; Read Process Stack Pointer to R0
MSR PSP, R0 ; Write R0 to Process Stack Pointer

3.7 RESET SEQUENCE