A B C D E

QIQY5
1 1

2
Whisky3.0 (Y400S) 2

NM-A141 Rev0.2 Schematic

Intel IVY Bridge Processor with DDRIII + Panther Point PCH

3
nVIDIA N14P GT + 2nd VGA N14P GT 3

2012-10-25-Rev0.2

WWW.SANDUNTECH.COM

4 4

Security Classification Title

2011/11/01 Deciphered Date 2012/12/31 COVER PAGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 1 of 65
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 A B C D E

PCI-Express 16X Gen3

PEG 8~15 PEG 0~7
Intel CPU
Ivy Bridge Memory BUS (DDRIII) DDR3-SO-DIMM X2
2nd VGA, N14P-GT1 N14P-GT1 Dual Channel
1 BANK 0, 1, 2, 3 1

rPGA-989
VRAM 64*32 VRAM 64*32 1.5V DDRIII 1066/1333/1600 MT/s
37.5mm*37.5mm UP TO 16G
GDDR5* 8 GDDR5* 8
Sub/B Page 32 Page 23,24,25,26,27,28,29,30,31
Page 5,6,7,8,9,10,11

FDI *8 DMI *4
2.7GT/s 5GT/s

HDMI Conn. CRT Conn. LVDS Conn.

Page 36 Page 35 Page 34 USB 2.0 4x USB Left USB Right
USB 2.0 Port 2 USB 2.0 Port 9
HDMI1.4b 5V 480MHz USB 3.0 Port 2 USB 2.0 Port 5, Cha
Page 48 Sub/B Page 49
2
Intel PCH USB 3.0 2x Int. Camera BT
2

Atheros Panther Point 5V 5GT/s USB 3.0 Port 0

Page 34
USB 2.0 Port 13
Page 47
AR8161 1G PCIe Gen1 1x
RJ45 Conn. 1.5V 5GT/s
Page 39 AR8151 1G
PCIe port 1 Page 38
USB 2.0 1x
PCIeMini Card mSATA SSD
FCBGA-989 Balls 5V 480MHz WLAN
PCIe Port 2 SATA Port 0
25mm*25mm PCIe Gen1 1x page 37 page 37
CardReader 5V 480MHz
JMB38C PCIe Gen1 1x PCIeMini Card
1.5V 5GT/s SATA Gen3 Port 0 WLAN
SD/MMC/MS/XD USB Port 10
page 37
5V 6GHz(600MB/s)
PCIe port 4 Page 44

SATA Gen3 Port 1 SATA HDD

5V 6GHz(600MB/s) SATA Port 1
3
SPI ROM SPI BUS page 41 3

(4MB+2MB) 3.3V 33MHz

Page 14 SATA Gen1 Port2 SATA ODD
Page 14,15,16,17,18,19,20,21,22 5V 3GHz(300MB/s) SATA Port 1
page 41

HD Audio
LPC BUS
3.3V 33MHz
3.3V 24MHz

Debug Port EC Codec AMP

Page 45 ITE IT8580E-HX ALC269Q-VC3 MAX98400B SPK Conn.
Page 43
Page 42 Page 43
Page 45
Power Circuit DC/DC
Page 52,53,54,55,56,57,
58,59,60,61,62

4 DC/DC Interface CKT. RTC CKT. Thermal Sensor Int. MIC Conn. 4

Page 51 Page 52 Touch Pad Int.KBD (JCMOS Conn.) Ext. MIC Conn. HP Conn.
EMC 1403
Page 34 Sub/B Page 49 Sub/B Page 49
Page 46 Page 46 Page 40
POWER/B Conn. AUDIO, USB/B Conn.
Page 40 Page 49 Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 BlOCK DIAGRAM

ODD/B Conn. NOVO/B Conn. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
page 41 Page 40 DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y400S-NM-A141 1.0

Date: Monday , January 14 , 2013 Sheet 2 of 65

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 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane +1.5VS
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

1
+V1.5S_VCCP 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+3VALW +CPU_CORE
+VGA_CORE
+1.5V S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +GFX_CORE
+5VALW +1.8VS
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

+1.05VS
State +0.75VS
+3.3VS_VGA
+1.5VS_VGA
USB Port Table BOM Structure Table
+1.05VS_VGA
4 External BOM Structure BTO Item
USB 2.0 USB 3.0 Port USB Port
HDMI@ HDMI part
S0 O O O O 0
Camera
1
XHCI 1 CHG@ USB charger part
2 NOCHG@ No USB charger part
S3 O O O X EHCI1
2 USB Port (Left Side)
CMOS@ CMOS Camera part
3
2 3 8161@ AR8161 LAN part 2

4 8151@ AR8151 LAN part

S5 S4/AC Only O O X X 4
8161S@ AR8161 LAN surge part
5 USB Port (Right Side) 8151S@ AR8151 LAN surge part
6
S5 S4 SURGE@ AR8151&8161 LAN surge part --> Delete (201200627)

Battery only O X X X 7
61@ X76 P/N for AR8161
8 51@
EHCI2 X76 P/N for AR8151
9 USB Port (Right Side) X76@ X76 Level part for VRAM
S5 S4 10 Mini Card(WLAN)
GC6@ NV CG6 support part
AC & Battery X X X X 11
NOGC6@ NV no CG6 support part
don't exist 12 AOAC@ AOAC support part
13 Blue Tooth
KBL@ K/B Light part
ME@ ME part
SMBUS Control Table OPT@ For optimus function part
PCIE PORT LIST SLI@ For SLI function part
Main 2nd WLAN Thermal PCH TP
SOURCE VGA VGA BATT IT8580E SODIMM WiMAX Sensor Module Port Device DS3@ Deep S3 support part
3 S3@ For S3 function part 3

1 LAN GT@ NV chip part

EC_SMB_CK1 IT8580E
X X V X X X X X X 2 WLAN @ Unpop
EC_SMB_DA1 +3VALW
+3VALW 3
4 Card Reader
EC_SMB_CK2 IT8580E
V V X X X X V V X 5
EC_SMB_DA2 +3VS +3VS +3VS +3VS +3V_PCH 6
7
SMB_CLK_S3 PCH
SMB_DATA_S3 X X X X V V X V V 8
+3VS +3VS +3VS +3V_PCH +3VS

Address
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address ZZZ1
4 4

Device Device Address Device Address

Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb DDR DIMM0 1001 000Xb
DAZ00200100
Master VGA 0x9E DDR DIMM2 1001 010Xb
Slave VGA 0x9C
Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 NOTES LIST

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Tuesday , March 12 , 2013 Sheet 3 of 65
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 5 4 3 2 1

Hot plug detect for IFP link E

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
FBVDDQ PCI Express I/O and I/O and Other
VGA and GDDR5 Voltage Rails (N13Px GPIO) GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO I/O ACTIVE Function Description Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

GPIO0 OUT - FB_CLAMP N13X

128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
1GB
D D
GPIO1 OUT - GDDR5

GPIO2 OUT VGA_BL_PWM

- Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO3 OUT - VGA_ENVDD ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO4 OUT - VGA_ENBKL ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO5 OUT -
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO6 OUT - FB_CLAMP_TOGGLE_REQ# STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO7 OUT -
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED

GPIO8 I/O - OVERT# STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V

CHANGE_GEN3
GPIO9 OUT - VGA_ALERT#
Device ID setting I2C Slave addrees ID
GPIO10 OUT - Memory VREF Control N13P-GT SMB_ALT_ADDR
(28nm) 0x0FDB 0 0x9E
(ROM_SO Bit 1)
GPIO11 OUT - NVVDD PWM_VID
C C
1 0x9C
GPIO12 IN VGA_AC_DET_R (10K pull High)

GPIO13 OUT - DPRSLPVR_VGA

GPIO14 OUT -
GPU ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
GPIO15 IN N/A
PU 10K PU 25K PU 45K PD 35K PD 10K PU 5K PD 10K Master
GPIO16 OUT - N13P-GT1
28nm PU 20K PU 25K PU 45K PD 35K PD 10K PD 5K PD 10K Slave
GPIO17 IN N/A

GPIO18 IN - dGPU_HDMI_HPD

GPIO19 IN -
GPU N13P-GT

FB Memory (GDDR5) ROM_SI

Samsung K4G10325FG-HC04
B
+3VS_VGA 2500MHz B

32Mx32 PD 45K
+VGA_CORE
Hynix H5GQ1H24BFR-T2C
tNVVDD >0 2500MHz
+1.5VS_VGA 32Mx32 PD 35K
tFBVDDQ >0
Samsung K4G20325FD-FC04
+1.05VS_VGA 2500MHz
tPEX_VDD >0 64Mx32 PD 30K

Hynix H5GQ2H24MFR-T2C
1. all power rail ramp up time should be larger than 40us
2500MHz
64Mx32 PD 25K

Other Power rail

+3VS_VGA
A A

Tpower-off <10ms

Security Classification LC Future Center Secret Data Title

1.all GPU power rails should be turned off within 10ms

Issued Date 2011/11/01 Deciphered Date 2012/12/31 VGA NOTES LIST
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 4 of 65
 5 4 3 2 1

D D

1. PEG_ICOMPI and RCOMPO signals should be shorted and routed with

a. max length = 500 mils
b. typical impedance = 43 mohms
2. PEG_ICOMPO signals should be routed with
+1.05VS a. max length = 500 mils
JCPU1A ME@ R1 b. typical impedance = 14.5 mohms
J22 PEG _ COMP 2 1
PEG_ICOMPI J21
DMI _ CRX_ PTX_ N0 B27 PEG_ICOMPO H22 24.9_0402_1%
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO
DMI _ CRX_ PTX_ N1 B25
<16> DMI_CRX_PTX_N1 DMI_RX#[1]
DMI_CRX_PTX_N2 A25
<16> DMI_CRX_PTX_N2 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23,32>
DMI _ CRX_ PTX_ N3 B24 K33 PCIE_ CRX_ GTX_ N0
<16> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] M35 PCIE_CRX_GTX_N1
DMI _CRX_ PTX_ P0 B28 PEG_RX#[1] L34 PCIE_ CRX_ GTX_ N2
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
DMI_CRX_PTX_P1 B26 J35 PCIE_CRX_GTX_N3 PEG Static Lane Reversal - CFG2 is for the 16x
<16> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
DMI _CRX_ PTX_ P2 A24 J32 PCIE_ CRX_ GTX_ N4
<16> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4]
DMI _CRX_ PTX_ P3 B23 H34 PCIE_ CRX_ GTX_ N5
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5]
PEG_RX#[6]
H31 PCIE _CRX _ GTX_ N6 1: Normal Operation; Lane # definition matches
<16> DMI_CTX_PRX_N0
DMI _ CTX_ PRX_ N0 G21
DMI_TX#[0] PEG_RX#[7]
G33 PCIE_ CRX_ GTX_ N7 CFG2 socket pin map definition
DMI _ CTX_ PRX_ N1 E22 G30 PCIE_ CRX_ GTX_ N8
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] F35
DMI _ CTX_ PRX_ N2 F21 PCIE_ CRX_ GTX_ N9
<16> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
DMI _ CTX_ PRX_ N3 D21 E34 PCIE_ CRX_ GTX_ N10 0:Lane Reversed
<16>

<16>
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI _CTX_ PRX_ P0 G22
DMI_TX#[3]

DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
PCIE _CRX _ GTX_ N11
PCIE_ CRX_ GTX_ N12 *
DMI _CTX_ PRX_ P1 D22 D31 PCIE_ CRX_ GTX_ N13
<16> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] B33
DMI_CTX_PRX_P2 F20 PCIE_CRX_GTX_N14
<16> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
DMI _CTX_ PRX_ P3 C21 C32 PCIE_ CRX_ GTX_ N15
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
C PCIE_CRX_GTX_P[0..15] <23,32> C
J33 PCIE _CRX _ GTX_ P0
PEG_RX[0] L35 PCIE _CRX _ GTX_ P1
PEG_RX[1] K34 PCIE _CRX _ GTX_ P2
FDI _CTX_ PRX_ N0 A21 PEG_RX[2] H35 PCIE_ CRX_ GTX_ P3
<16> FDI_CTX_PRX_N0 FDI _CTX_ PRX_ N1 H19 FDI0_TX#[0] PEG_RX[3] H32 PCIE_ CRX_ GTX_ P4
<16> FDI_CTX_PRX_N1 FDI _CTX_ PRX_ N2 E19 FDI0_TX#[1] PEG_RX[4] G34 PCIE_ CRX_ GTX_ P5
<16> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] G31
FDI _CTX_ PRX_ N3 F18 PCIE_ CRX_ GTX_ P6
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] F33
FDI _CTX_ PRX_ N4 B21 PCIE_ CRX_ GTX_ P7
<16> FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 C20 FDI1_TX#[0] PEG_RX[7] F30 PCIE_CRX_GTX_P8
<16> FDI_CTX_PRX_N5 FDI _CTX_ PRX_ N6 D18 FDI1_TX#[1] PEG_RX[8] E35 PCIE_ CRX_ GTX_ P9
<16> FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 E17 FDI1_TX#[2] PEG_RX[9] E33 PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32 PCIE _CRX _ GTX_ P11
PEG_RX[11] D34 PCIE_CRX_GTX_P12
FDI _ CTX_ PRX_ P0 A22 PEG_RX[12] E31 PCIE_ CRX_ GTX_ P13
<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 G19 FDI0_TX[0] PEG_RX[13] C33 PCIE_CRX_GTX_P14
<16> FDI_CTX_PRX_P1 FDI _ CTX_ PRX_ P2 E20 FDI0_TX[1] PEG_RX[14] B32 PCIE_ CRX_ GTX_ P15
<16> FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
FDI _ CTX_ PRX_ P3 G18
<16> FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_GRX_N[0..15] <23,32>
FDI _ CTX_ PRX_ P4 B20 M29 PCIE_ CTX_ GRX_ C_ N0 C1 1 2 0. 22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ N0
<16> FDI_CTX_PRX_P4 FDI _ CTX_ PRX_ P5 C19 FDI1_TX[0] PEG_TX#[0] M32 PCIE_ CTX_ GRX_ C_ N1 C2 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ N1
<16> FDI_CTX_PRX_P5 FDI _ CTX_ PRX_ P6 D19 FDI1_TX[1] PEG_TX#[1] M31 PCIE_ CTX_ GRX_ C_ N2 PCIE_ CTX_ GRX_ N2
C3 1 2 0. 22U_ 0402_ 10V6K
<16> FDI_CTX_PRX_P6 FDI _ CTX_ PRX_ P7 F17 FDI1_TX[2] PEG_TX#[2] L32 PCIE_ CTX_ GRX_ C_ N3 C4 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ N3
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29 PCIE _CTX _GRX_ C_ N4 PCIE_ CTX_ GRX_ N4
C5 1 2 0. 22U_ 0402_ 10V6K
FDI _ FSYNC0 J18 PEG_TX#[4] K31 PCIE _CTX_ GRX_ C_ N5 C6 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ N5
<16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_C_N6 C7 1 2 0.22U _0402_ 10V6K PCIE_CTX_GRX_N6
<16> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] J30 PCIE _CTX _GRX_ C_ N7 C8 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ N7
FDI_INT H20 PEG_TX#[7] J28 PCIE_CTX_GRX_C_N8 SLI@ C9 1 2 0.22U _0402_ 10V6K PCIE_CTX_GRX_N8
<16> FDI_INT FDI_INT PEG_TX#[8] H29 PCIE _CTX _GRX_C _ N9 SLI@ C10 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ N9
FDI_LSYNC0 J19 PEG_TX#[9] G27 PCIE_CTX_GRX_C_N10 SLI@ C11 1 2 0.22U _0402_ 10V6K PCIE_CTX_GRX_N10
<16> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
FDI _LSYNC1 H17 E29 PCIE _CTX_ GRX_ C_ N11 SLI@ C12 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ N11
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] F27 PCIE_CTX_GRX_C_N12 SLI@ C13 1 2 0.22U _0402_ 10V6K PCIE_CTX_GRX_N12
PEG_TX#[12] D28 PCIE _CTX _GRX_ C_ N13 SLI@ C14 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ N13
+1.05VS PEG_TX#[13] F26 PCIE _CTX _GRX_ C_ N14 SLI@ C15 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ N14
B R7 PEG_TX#[14] E25 PCIE _CTX _GRX_ C_ N15 PCIE_ CTX_ GRX_ N15 B
SLI@ C16 1 2 0. 22U_ 0402_ 10V6K
1 2 EDP _ COMP A18 PEG_TX#[15]
A17 eDP_COMPIO M28 PCIE _CTX _GRX_C _ P0 PCIE_ CTX_ GRX_ P0 PCIE_CTX_GRX_P[0..15] <23,32>
C20 1 2 0. 22U_ 0402_ 10V6K
B16 eDP_ICOMPO PEG_TX[0] M33 PCIE _CTX _GRX_C _ P1 C23 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P1
24.9_0402_1%
eDP_HPD# PEG_TX[1] M30 PCIE _CTX _GRX_C _ P2 C25 1 2 0. 22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P2
PEG_TX[2] L31
eDP_COMPIO and ICOMPO signals PEG_TX[3]
PCIE _CTX _GRX_ C_ P3 C30 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P3
should be shorted near balls C15 L28 PCIE_CTX_GRX_C_P4 C18 1 2 0.22U _0402_ 10V6K PCIE_CTX_GRX_P4
D15 eDP_AUX PEG_TX[4] K30 PCIE _CTX _GRX_ C_ P5 C22 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P5
and routed with typical eDP_AUX# PEG_TX[5] K27 PCIE_CTX_GRX_C_P6 C28 1 2 0.22U _0402_ 10V6K PCIE_CTX_GRX_P6
impedance <25 mohms PEG_TX[6] J29 PCIE _CTX _GRX_ C_ P7 C32 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P7
C17 PEG_TX[7] J27 PCIE _CTX _GRX_ C_ P8 SLI@ C19 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P8
F16 eDP_TX[0] PEG_TX[8] H28 PCIE _CTX _GRX_C _ P9 SLI@ C24 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P9
C16 eDP_TX[1] PEG_TX[9] G28 PCIE _CTX _GRX_ C_ P10 SLI@ C29 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P10
G15 eDP_TX[2] PEG_TX[10] E28 PCIE _CTX _GRX_ C_ P11 SLI@ C17 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P11
eDP_TX[3] PEG_TX[11] F28 PCIE _CTX _GRX_ C_ P12 SLI@ C21 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P12
C18 PEG_TX[12] D27 PCIE _CTX _GRX_ C_ P13 SLI@ C27 1 2 0. 22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P13
E16 eDP_TX#[0] PEG_TX[13] E26 PCIE _CTX_GRX_ C_ P14 SLI@ C26 1 2 0.22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P14
D16 eDP_TX#[1] PEG_TX[14] D25 PCIE _CTX _GRX_ C_ P15 SLI@ C31 1 2 0. 22U_ 0402_ 10V6K PCIE_ CTX_ GRX_ P15
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(1/7) DMI,FDI,PEG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 5 of 65
5 4 3 2 1
 5 4 3 2 1

JCPU1B ME@
D D

A28 CLK_CPU_DMI
BCLK CLK_CPU_DMI <15>
H _SNB_ IVB# C26 A27 CLK_ CPU_ DMI#
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
H : Sandy Bridge
PROC_SEL AN34
SKTOCC# A16 R12 2 1 1K _0402_ 5% +1.05VS
DPLL_REF_CLK
L : IVY Bridge DPLL_REF_CLK#
A15 R13 2 1 1K _0402_ 5%

T14 PAD H _ CATERR# AL33

CATERR#

H_PECI AN33 R8 H_DRAMRST#

+1.05VS <45> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>

1 R9 2 H _ PROCHOT# H_ PROCHOT# 1 R15 2 H _PROCHOT# _R AL32 AK1 R16 2 1 140_ 0402_ 1%

<45,53> H_PROCHOT# SM_ RCOMP0
PROCHOT# SM_RCOMP[0] A5 SM _ RCOMP1 R17 2 1 25.5_ 0402_ 1%
62_0402_5% 56_0402_5% SM_RCOMP[1] A4 SM _ RCOMP2 R18 2 1 200 _ 0402_ 1%
SM_RCOMP[2]
H _ THRMTRIP# AN32
<19> H_THRMTRIP# THERMTRIP#
DDR3 Compensation Signals

AP29 +1.05V S
PRDY# AP27
PREQ#
C AR26 XDP _TCK XDP _ TMS R20 2 1 51_ 0402_ 5% C
TCK AR27 XDP _TMS XDP _ TDI R21 2 1 51_ 0402_ 5%
1 R22 2 TMS
H _ PM_ SYNC H_ PM_ SYNC_ R AM34 AP30 XDP_ TRST# XDP_ TDO R23 2 1 51_ 0402_ 5%
<16> H_PM_SYNC PM_SYNC TRST# @
R_short 0_0402_5% AR28 XDP _TDI XDP _ TCK 2 1
R24 51_ 0402_ 5%
TDI AP26 XDP _TDO XDP _ TRST# R25 2 1 51_ 0402_ 5%
H _ CPUPW RGD 1 R26 2 H _ CPUPW RGD _ R AP33 TDO
<19> H_CPUPW RGD UNCOREPW RGOOD
R_short 0_0402_5%
AL35
1
PM_SYS_PW RGD_BUF 1 R29 2 PM_DRAM_PW RGD_R V8 DBR# PU/PD for JTAG signals
C550 R27 SM_DRAMPW ROK
100P_0402_50V8J 130_0402_5% AT28
10K_0402_5%
2 BPM#[0] AR29
BPM#[1] AR30
9/23 ESD Request BPM#[2]
BUF _CPU _ RST# AR33 AT30
RESET# BPM#[3] AP32
BPM#[4] AR31
BPM#[5] AT31
BPM#[6] AR32
BPM#[7]

TYCO_2013620-2_IVY BRIDGE

B B

Buffered Reset to CPU

+1.05VS +3VS
+3VS +3VALW +1.5V_CPU_VDDQ

1 1
R338 C33 R30 R32 C34
10K_0402_5% 0.1U_0402_16V4Z 200_0402_5% 75_0402_5% 0.1U_0402_16V4Z
2 2

1 1
1.05V 1 This is NC pin
<16> SYS_PWROK R65 @ 2 0_0402_5%
B 4 PM_SYS_PWRGD_BUF BUF_CPU_RST# 1 R34 2 BUFO_CPU_RST# 4 NC
2 O Y 2 PLT _ RST#
3V
<16> PM_DRAM_PW RGD A 43_0402_1% A PLT_RST# <18,23,32,37,38,44,45>
U1
74AHC1G09GW _TSSOP5 U2
R35 @ SN74LVC1G07DCKR_SC70-5
0_0402_5%

A A

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(2/7) PM,XDP,CLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 6 of 65
5 4 3 2 1
 5 4 3 2 1

JCPU1C ME@ JCPU1D ME@

AB6 AE2
<12> DDR_A_D[0..63] SA_CK[0] AA6 M_CLK_DDR0 <12> <13> DDR_B_D[0..63] SB_CK[0] AD2 M_CLK_DDR2 <13>
DDR _A_ D0 C5 SA_CLK#[0] V9 M_CLK_DDR#0 <12> DDR _ B_ D0 C9 SB_CLK#[0] R9 M_CLK_DDR#2 <13>
DDR _A_ D1 D5 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR _ B_ D1 A7 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR _A_ D2 D3 SA_DQ[1] DDR _ B_ D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
D DDR _A_ D4 D6 SA_DQ[3] AA5 DDR _ B_ D4 A9 SB_DQ[3] AE1 D
DDR_A_D5 C6 SA_DQ[4] SA_CK[1] AB5 M_CLK_DDR1 <12> DDR_B_D5 A8 SB_DQ[4] SB_CK[1] AD1 M_CLK_DDR3 <13>
DDR _A_ D6 C2 SA_DQ[5] SA_CLK#[1] V10 M_CLK_DDR#1 <12> DDR _ B_ D6 D9 SB_DQ[5] SB_CLK#[1] R10 M_CLK_DDR#3 <13>
C3 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> D8 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
DDR_A_D7 DDR_B_D7
DDR _A_ D8 F10 SA_DQ[7] DDR _ B_ D8 G4 SB_DQ[7]
DDR _A_ D9 F8 SA_DQ[8] DDR _ B_ D9 F4 SB_DQ[8]
DDR _A_ D10 G10 SA_DQ[9] AB4 DDR _ B_ D10 F1 SB_DQ[9] AB2
DDR _A_ D11 G9 SA_DQ[10] SA_CK[2] AA4 DDR _ B_ D11 G1 SB_DQ[10] SB_CK[2] AA2
DDR _A_ D12 F9 SA_DQ[11] SA_CLK#[2] W9 DDR _ B_ D12 G5 SB_DQ[11] SB_CLK#[2] T9
DDR _A_ D13 F7 SA_DQ[12] SA_CKE[2] DDR _ B_ D13 F5 SB_DQ[12] SB_CKE[2]
DDR _A_ D14 G8 SA_DQ[13] DDR _ B_ D14 F2 SB_DQ[13]
DDR _A_ D15 G7 SA_DQ[14] DDR _ B_ D15 G2 SB_DQ[14]
DDR _A_ D16 K4 SA_DQ[15] AB3 DDR _ B_ D16 J7 SB_DQ[15] AA1
DDR _A_ D17 K5 SA_DQ[16] SA_CK[3] AA3 DDR _ B_ D17 J8 SB_DQ[16] SB_CK[3] AB1
DDR_A_D18 K1 SA_DQ[17] SA_CLK#[3] W 10 DDR_B_D18 K10 SB_DQ[17] SB_CLK#[3] T10
DDR _A_ D19 J1 SA_DQ[18] SA_CKE[3] DDR _ B_ D19 K9 SB_DQ[18] SB_CKE[3]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR _A_ D21 J4 SA_DQ[20] DDR _ B_ D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
K2 SA_DQ[22] SA_CS#[0] AL3 DDR_CS0_DIMMA# <12> K7 SB_DQ[22] SB_CS#[0] AE3 DDR_CS2_DIMMB# <13>
DDR _A_ D23 DDR _ B_ D23
M8 SA_DQ[23] SA_CS#[1] AG1 DDR_CS1_DIMMA# <12> M5 SB_DQ[23] SB_CS#[1] AD6 DDR_CS3_DIMMB# <13>
DDR _A_ D24 DDR _ B_ D24
DDR _A_ D25 N10 SA_DQ[24] SA_CS#[2] AH1 DDR _ B_ D25 N4 SB_DQ[24] SB_CS#[2] AE6
DDR _A_ D26 N8 SA_DQ[25] SA_CS#[3] DDR _ B_ D26 N2 SB_DQ[25] SB_CS#[3]
DDR _A_ D27 N7 SA_DQ[26] DDR _ B_ D27 N1 SB_DQ[26]
DDR _A_ D28 M10 SA_DQ[27] DDR _ B_ D28 M4 SB_DQ[27]
DDR _A_ D29 M9 SA_DQ[28] AH3 DDR _ B_ D29 N5 SB_DQ[28] AE4
DDR _A_ D30 N9 SA_DQ[29] SA_ODT[0] AG3 M_ODT0 <12> DDR _ B_ D30 M2 SB_DQ[29] SB_ODT[0] AD4 M_ODT2 <13>
DDR _A_ D31 M7 SA_DQ[30] SA_ODT[1] AG2 M_ODT1 <12> DDR _ B_ D31 M1 SB_DQ[30] SB_ODT[1] AD5 M_ODT3 <13>
DDR _A_ D32 AG6 SA_DQ[31] SA_ODT[2] AH2 DDR _ B_ D32 AM5 SB_DQ[31] SB_ODT[2] AE5
DDR_A_D33 AG5 SA_DQ[32] SA_ODT[3] DDR_B_D33 AM6 SB_DQ[32] SB_ODT[3]
DDR _A_ D34 AK6 SA_DQ[33] DDR _ B_ D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
C DDR _A_ D36 AH5 SA_DQ[35] DDR _ B_ D36 AN3 SB_DQ[35] C
AH6 SA_DQ[36] C4 DDR_A_DQS#[0..7] <12> AN2 SB_DQ[36] D7 DDR_B_DQS#[0..7] <13>
DDR _A_ D37 DDR _ A_ DQS#0 DDR_ B_ D37 DDR_ B_ DQS#0
DDR _A_ D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR _ A_ DQS#1 DDR_ B_ D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_ B_ DQS#1
DDR _A_ D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR _ A_ DQS#2 DDR_ B_ D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_ B_ DQS#2
DDR _A_ D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR _ A_ DQS#3 DDR_ B_ D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_ B_ DQS#3
DDR _A_ D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR _ A_ DQS#4 DDR_ B_ D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_ B_ DQS#4
DDR _A_ D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR _A_ DQS#5 DDR_ B_ D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_ B_ DQS#5
DDR _A_ D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR _A_ DQS#6 DDR_ B_ D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_ B_ DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR _A_ D45 AH9 SA_DQ[44] SA_DQS#[7] DDR _ B_ D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR _A_ D47 AL8 SA_DQ[46] DDR _ B_ D47 AR5 SB_DQ[46]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
AN11 SA_DQ[48] D4 DDR_A_DQS[0..7] <12> AJ11 SB_DQ[48] C7 DDR_B_DQS[0..7] <13>
DDR _A_ D49 DDR _ A_ DQS0 DDR_ B_ D49 DDR_ B_ DQS0
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR _A_ D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR _ A_ DQS2 DDR_ B_ D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_ B_ DQS2
DDR _A_ D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR _ A_ DQS3 DDR_ B_ D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_ B_ DQS3
DDR _A_ D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR _ A_ DQS4 DDR_ B_ D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_ B_ DQS4
DDR _A_ D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR _A_ DQS5 DDR_ B_ D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_ B_ DQS5
DDR _A_ D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR _A_ DQS6 DDR_ B_ D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_ B_ DQS6
DDR _A_ D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR _A_ DQS7 DDR_ B_ D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_ B_ DQS7
DDR _A_ D57 AH14 SA_DQ[56] SA_DQS[7] DDR _ B_ D57 AN14 SB_DQ[56] SB_DQS[7]
DDR _A_ D58 AL15 SA_DQ[57] DDR _ B_ D58 AR14 SB_DQ[57]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR _A_ D60 AL14 SA_DQ[59] DDR _ B_ D60 AT12 SB_DQ[59]
DDR_A_D61 AK14 SA_DQ[60] DDR_A_MA[0..15] <12> DDR_B_D61 AN15 SB_DQ[60] DDR_B_MA[0..15] <13>
AD10 DDR_A_MA0 AA8 DDR_B_MA0
DDR _A_ D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR _ A_ MA1 DDR_ B_ D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_ B_ MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR _A_ MA3 SB_DQ[63] SB_MA[2] T6 DDR _B_ MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR _A_ MA5 SB_MA[4] T4 DDR _B_ MA5
SA_MA[5] W3 DDR _A_ MA6 SB_MA[5] T3 DDR _B_ MA6
B AE10 SA_MA[6] W6 DDR _A_ MA7 AA9 SB_MA[6] R2 DDR _B_ MA7 B
<12> DDR_A_BS0 SA_BS[0] SA_MA[7] <13> DDR_B_BS0 SB_BS[0] SB_MA[7]
AF10 V1 DDR _A_ MA8 AA7 T5 DDR _B_ MA8
<12> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 <13> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3
DDR _A_ MA9 DDR _B_ MA9
<12> DDR_A_BS2 SA_BS[2] SA_MA[9] <13> DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR _A _ MA10 AB7 DDR _B _MA10
SA_MA[10] V4 DDR _A_ MA11 SB_MA[10] R1 DDR _B_ MA11
SA_MA[11] W4 DDR _A_ MA12 SB_MA[11] T1 DDR _B_ MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<12> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 <13> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5
DDR _A_ MA14 DDR _B_ MA14
<12> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 DDR_A_MA15 <13> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4 DDR_B_MA15
<12> DDR_A_W E# SA_W E# SA_MA[15] <13> DDR_B_W E# SB_W E# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

+1.5V

R37
1K_0402_5%

3 1 DDR3 _ DRAMRST#_ R 1 R38 2

H _ DRAMRST#
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
1K_0402_5%
Q2
R39 BSS138_NL_SOT23-3
4.99K_0402_1%
A A

1 @ 2 DRAMRST_CNTRL
<15> DRAMRST_CNTRL_PCH
R40 0_0402_5% 1
<10> DRAMRST_CNTRL
C35 Title
1 DS3@2 0.047U_0402_16V4Z Security Classification LC Future Center Secret Data
<45> DRAMRST_CNTRL_EC 2
R64 0 _0402_ 5%
Reserve for Deep S3
Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(3/7) DDRIII
Module design used 0.047u THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 7 of 65
5 4 3 2 1
 5 4 3 2 1

D D

JCPU1E ME@
CFG Straps for Processor
AH27
AK28 VCC_DIE_SENSE AH26
AK29 CFG[0] VSS
CFG2 AL26 CFG[1] CFG2
AL27 CFG[2]
CFG[3] PEG Static Lane Reversal - CFG2 is for the 16x
AK26 L7
CFG5 AL29 CFG[4] RSVD28 AG7
CFG[5] RSVD29
1: Normal Operation; Lane # definition matches
CFG6
CFG7
AL30
AM31
AM32
CFG[6]
CFG[7]
RSVD30
RSVD31
AE7
AK2 @
R41
1K_0402_1% CFG2 * socket pin map definition
AM30 CFG[8] W8
CFG[9] RSVD32
AM28
CFG[10] 0:Lane Reversed
AM26
AN28 CFG[11] AT26
AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
AM27 CFG[14] RSVD35
AK31 CFG[15]
AN29 CFG[16]
CFG[17]
Display Port Presence Strap
T8
RSVD37 J16 1 : Disabled; No Physical Display Port
C T56
T57
PAD
PAD
AJ31
AH31 VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
RSVD38
RSVD39
RSVD40
H16
G16
CFG4 * attached to Embedded Display Port C
AJ33
T58 PAD VCC_VAL_SENSE
T59 PAD
AH33
VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
11/24 --> Intel recommend
to reserve test point AJ26 AR35
RSVD5 RSVD_NCTF1 AT34
RSVD_NCTF2 AT33
RSVD_NCTF3 AP35
RSVD_NCTF4 AR34
RSVD_NCTF5
CFG6
F25 PCIE Port Bifurcation Straps
F24 RSVD8 CFG5
F23 RSVD9
RSVD10
D24
RSVD11 RSVD_NCTF6
B34 11: (Default) x16 - Device 1 functions 1 and 2 disabled
G25 A33
RSVD12 RSVD_NCTF7 R43 R44
G24
E23
D23
RSVD13
RSVD14
RSVD_NCTF8
RSVD_NCTF9
A34
B35
C35
1K_0402_1%
@
1K_0402_1% CFG[6:5]
*10: x8, x8 -
disabled
Device 1 function 1 enabled ; function 2
RSVD15 RSVD_NCTF10
C30
RSVD16 01: Reserved - (Device 1 function 1 disabled ; function
A31
B30 RSVD17 2 enabled)
RSVD18
B29
RSVD19 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
D30 AJ32
B31 RSVD20 RSVD51 AK32
A30 RSVD21 RSVD52
C29 RSVD22
RSVD23
AN35
J20 BCLK_ITP AM35 CFG7
B18 RSVD24 BCLK_ITP#
B RSVD25 PEG DEFER TRAINING B

R45
@
1K_0402_1% 1: (Default) PEG Train immediately following xxRESETB
J15
RSVD27 RSVD_NCTF11
AT2 CFG7 de assertion
AT1
RSVD_NCTF12 AR1
RSVD_NCTF13
0: PEG Wait for BIOS for training

B1
KEY

TYCO_2013620-2_IVY BRIDGE

A A

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(4/7) RSVD,CFG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 8 of 65
5 4 3 2 1
 5 4 3 2 1

JCPU1F ME@ POWER

+VCC_CORE +1.05VS
QC=94A
DC=53A
8.5A
D AG35 D
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
AG31 VCC4 VCCIO3 AC10
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF34 VCC11 VCCIO10 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
AF28 VCC17 VCCIO16 G13
AF27 VCC18 VCCIO17 G12
AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
AD33 VCC22 VCCIO21 F11
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AD27 VCC28 VCCIO26 D13
AD26 VCC29 VCCIO27 D12
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
C AC33 VCC32 VCCIO30 C13 C
AC32 VCC33 VCCIO31 C12
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
AC29 VCC36 VCCIO34 B12
AC28 VCC37 VCCIO35 A14
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44
AA30 VCC45
AA29 VCC46 +1.05VS
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
Y34 VCC51
VCC52 1
Y33
Y32 VCC53 C36 @ R46
Y31 VCC54 0.1U_0402_10V7K 75_0402_5%
Y30 VCC55 2
Y29 VCC56
Y28 VCC57
VCC58 Reserve 0.1u to avoid noise Place the PU resistor close to CPU
Y27
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# R47 1 2 43 _0402_ 5%
V33 VCC62 VIDALERT# AJ30 H _ CPU_ SVIDCLK R48 1 2 R_ short 0_ 0402_ 5% VR_SVID_ALRT# <59>
V32 VCC63 VIDSCLK AJ28 VR_SVID_CLK <59>
H _ CPU_ SVIDDAT R49 1 2 R_ short 0_ 0402_ 5%
B V31 VCC64 VIDSOUT VR_SVID_DAT <59> B
V30 VCC65 R50 2 1 130 _0402_ 5%
VCC66 +1.05VS
V29
V28 VCC67
VCC68 Place the PU resistor close to CPU
V27
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77
U27 VCC78
U26 VCC79 +VCC_CORE
R35 VCC80
R34 VCC81
R33 VCC82
R32 VCC83
R31 VCC84 R51
R30 VCC85
VCC86 100_0402_1%
R29 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
R28 VCC87
R27 VCC88 AJ35 VCCSENSE _R 1 2 R _short 0_ 0402_ 5% VCCSENSE
R52
R26 VCC89 VCC_SENSE AJ34 VCCSENSE <59>
VSSSENSE _R R53 1 2 R _short 0_ 0402_ 5% VSSSENSE
VCC90 VSS_SENSE VSSSENSE <59>
P35
P34 VCC91 +1.05VS
P33 VCC92 R1294 2 1 10 _0402 _1%
P32 VCC93 B10 VCCIO _ SENSE R54
P31 VCC94 VCCIO_SENSE VCCIO_SENSE <57>
A10 VSSIO _ SENSE R1297 2 1 10_ 0402_ 1% 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO
VCC96 VSS_SENCE 100ohm +-1% pull-down to GND near processor
A P29 A
P28 VCC97
P27 VCC98
P26 VCC99
VCC100

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(5/7) PWR,BYPASS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
TYCO_2013620-2_IVY BRIDGE Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 9 of 65
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V_CPU_VDDQ
+1.5V_CPU_VDDQ C287 1 2 0.1U _0402_ 10V6K

C286 1 2 0. 1U _ 0402_ 10V6K DRAMRST _ CNTRL

<7> DRAMRST_CNTRL
C96 1 2 0. 1U_ 0402_ 10V6K Q8 BSS138_SOT23
For Deep S3 1
C95 2 0.1U _0402_ 10V6K 1 3

+3VALW +VSB U3
8 1
D 7 2 R74 1 @ 2 0_0402_5% +V _DDR_ REFA_ R D
R56 need to check on SDV +VREF_DQ_DIMMA
6 3 R75 1 @ 2 0_0402_5% +V_DDR_REFB_R
+VREF_DQ_DIMMB
5
R1537 @ R56
100K_0402_5% 100K_0402_5% AO4304L_SO8
AO4304L @ R1487 1 3
Vgs=10V,Id=18A, 470_0603_5% R139 @ @ R132
1 R1349 2
RUN _ ON_ CPU1.5VS3 Rds<6.7m ohm Q7 BSS138_SOT23 1K_0402_1% 1K_0402_1%
470K_0402_5% P/N: SB00000RV00
DRAMRST _ CNTRL
D D
1 R1538 2 2 5 SUSP
1
<37,51,55,57> SUSP G G
R_short 0_0402_5% D R57 C97
2 S Q4A 470K_0402_5% 0.01U 50V K X7R 0603 S
<45> CPU1.5V_S3_GATE @ 2
G
Q156 2N7002KDW H_SOT363-6
Q4B 6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
S 2N7002KDW H_SOT363-6
2N7002_ SOT23

+VCC_GFXCORE_AXG
2 OPT@

POWER
VCC _ AXG_ SENSE R66 1 100_ 0402_ 1%

VSS _ AXG_ SENSE R90 2 OPT@ 1 100_ 0402_ 1%

+VCC_GFXCORE_AXG JCPU1G

C 46A AT24 AK35 VCC _AXG _ SENSE _ R R1488 1 OPT@ 2 0_0402_5% C

AT23 VAXG1 VAXG_SENSE VCC_AXG_SENSE <59>
AK34 VSS _AXG _ SENSE _ R R1489 1 2 0_ 0402_ 5%
AT21 VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <59>
OPT@
AT20 VAXG3 +1.5V_CPU_VDDQ
RV174 AT18 VAXG4
SLI@ AT17 VAXG5
0_0402_5%
AR24 VAXG6 R77
AR23 VAXG7
1K_0402_1%
AR21 VAXG8
AR20 VAXG9
AR18 VAXG10 AL1 +V_SM_VREF_CNT
AR17 VAXG11 SM_VREF
VAXG12 1
AP24
AP23 VAXG13 C114 R88
AP21 VAXG14 0.1U_0402_16V4Z 1K_0402_1%
AP20 VAXG15 B4 +V _DDR _ REFA_ R 2
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V _DDR _ REFB_ R
VAXG17 SB_DIMM_VREFDQ
AP17
VAXG18 Place the PU/PD resistor close to CPU within 2 inch
AN24
AN23 VAXG19 (Reserve power side)
AN21 VAXG20
AN20 VAXG21
VAXG22 +1.5V_CPU_VDDQ
AN18
AN17 VAXG23 5A
AM24 VAXG24 AF7
AM23 VAXG25 VDDQ1 AF4
AM21 VAXG26 VDDQ2 AF1
VAXG27 VDDQ3 1
AM20 AC7 1 1 1 1 1 1
VAXG28 VDDQ4
AM18 AC4 @ +
AM17 VAXG29 VDDQ5 AC1
AL24 VAXG30 VDDQ6 Y7
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2 2 2
B AL21 VAXG32 VDDQ8 Y1 B
AL20 VAXG33 VDDQ9 U7
AL18 VAXG34 VDDQ10 U4
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4
AK21 VAXG38 VDDQ14 P1
AK20 VAXG39 VDDQ15
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
VAXG45 +VCCSA
AJ20
AJ18 VAXG46 6A
AJ17 VAXG47 M27 +VCCSA
AH24 VAXG48 VCCSA1 M26
AH23 VAXG49 VCCSA2 L26
VAXG50 VCCSA3 1
AH21 J26 1 1 1 1
AH20 VAXG51 VCCSA4 J25 @ @ +
AH18 VAXG52 VCCSA5 J24
AH17 VAXG53 VCCSA6 H26
VAXG54 VCCSA7 H25 2 2 2 2 2
VCCSA8

H23 +VCCSA_SENSE R68 1 @ 2 0_0402_5%

+1.8VS VCCSA_SENSE +VCCSA_SENSE <56>

1 R67 2 +1.8VS_ VCCPLL B6

10U _ 0805_ 6.3V6M 1U _ 0402_ 6.3V6K
A A6 VCCPLL1 C22 A
R_short 0_0805_5% 1 VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <56>
1 1 1 A2 C24
VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <56>
C279 + @ C130 C131 C132
6/3 modify for VCCSA 4-Level voltage
2 2 2 2 A19
VCCIO_SEL
330U_B2_2.5 V M_R15M 1U_0402_6.3V6 K Title
TYCO_2013620-2_IVY BRIDGE LC Future Center Secret Data
11/24 change 22U X2 to 330U B2 size Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(6/7) PWR
ME@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 10 of 65
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I

D AT35 AJ22 D
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6
AR16 VSS16 VSS96 AH25 P3 VSS174 VSS247 E5
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR7 VSS19 VSS100 AH16 N34 VSS177 VSS250 E2
AR4 VSS20 VSS101 AH7 N33 VSS178 VSS251 E1
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP31 VSS23 VSS104 AG8 N30 VSS181 VSS254 D29
AP28 VSS24 VSS105 AG4 N29 VSS182 VSS255 D26
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
AP10 VSS30 VSS111 AE34 L30 VSS188 VSS261 C27
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25
C AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23 C
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AN7 VSS42 VSS123 AC8 K29 VSS200 VSS273 B8
AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM16 VSS48 VSS129 AB34 H27 VSS206 VSS279 A32
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
AL28 VSS58 VSS139 Y8 H6 VSS216
AL25 VSS59 VSS140 Y6 H5 VSS217
AL22 VSS60 VSS141 Y5 H4 VSS218
AL19 VSS61 VSS142 Y3 H3 VSS219
AL16 VSS62 VSS143 Y2 H2 VSS220
AL13 VSS63 VSS144 W 35 H1 VSS221
B AL10 VSS64 VSS145 W 34 G35 VSS222 B
AL7 VSS65 VSS146 W 33 G32 VSS223
AL4 VSS66 VSS147 W 32 G29 VSS224
AL2 VSS67 VSS148 W 31 G26 VSS225
AK33 VSS68 VSS149 W 30 G23 VSS226
AK30 VSS69 VSS150 W 29 G20 VSS227
AK27 VSS70 VSS151 W 28 G17 VSS228
AK25 VSS71 VSS152 W 27 G11 VSS229
AK22 VSS72 VSS153 W 26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

ME@ ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PROCESSOR(7/7) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 11 of 65
5 4 3 2 1
 5 4 3 2 1

DDR3 SO-DIMM A
+1.5V +1.5V +1.5V

R78
+VREF_DQ_DIMMA
1K_0402_1% [email protected]
For RF request
JDIMM1 ME@
+VREF _DQ_DIMMA 1 2
VREF_DQ VSS1 DDR_A_D[0..63] <7>
3 4 DDR_A_D4
DDR_A_D0 5 VSS2 DQ4 6 DDR_ A_ D5
D DQ0 DQ5 DDR_A_DQS[0..7] <7> D
1 1 DDR_A_D1 7 8 1 1 1
R79 9 DQ1 VSS3 10 DDR_A_DQS#0
C141 C140 C51 C52 C53
VSS4 DQS#0 DDR_A_DQS#[0..7] <7>
1K_0402_1% 11 12 DDR_A_DQS0 @ @ @
13 DM0 DQS0 14
2 2 VSS5 VSS6 2 2 2 DDR_A_MA[0..15] <7>
DDR_A_D2 15 16 DDR_ A_ D6
17 DQ2 DQ6 18
DDR_A_D3 DDR_ A_ D7
19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_ A_ D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_ A_ D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_ DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <13,7>
31 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_ A_ D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_ A_ D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_ A_ D20
41 DQ16 DQ20 42 DDR_A_D21
DDR_A_D17
43 DQ17 DQ21 44
45 VSS15 VSS16 46
DDR_A_DQS#2
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_ A_ D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_ A_ D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
67 VSS23 VSS24 68
DDR_A_D26 DDR_ A_ D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_ A_ D31
C 71 DQ27 DQ31 72 C
VSS25 VSS26

DDR_CKE0_ DIMMA 73 74 DDR_ CKE1_ DIMMA

<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_ A_ MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR _ A_ MA11
85 A12/BC# A11 86
DDR_A_MA9 DDR_ A_ MA7
87 A9 A7 88
VDD5 VDD6
DDR _A _ MA8
DDR_A_MA5
89
91 A8 A6
90
92
DDR _ A_ MA6
DDR_A_MA4 Layout Note:
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
A5 A4
DDR_A_MA3
93
95 VDD7 VDD8
94
96 DDR_ A_ MA2 Place near DIMM (10uF_0603_6.3V)*8
A3 A2
DDR_A_MA1 97
99 A1 A0
98
100
DDR_ A_ MA0
(0.1uF_402_10V)*4
M_CLK_ DDR0 101 VDD9 VDD10 102 M_ CLK_ DDR1
<7> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <7>
M_CLK_ DDR#0 103 104 M_ CLK_ DDR#1
<7> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <7>
105 106
107 VDD11 VDD12 108
DDR_A_MA10 DDR_ A_ BS1
A10/AP BA1 DDR_A_BS1 <7>
DDR_A_BS0 109 110 DDR_ A_ RAS# +1.5V +1.5V
<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_ CS0_ DIMMA#
<7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
DDR_A_CAS# 115 116 M_ODT0
<7> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
117 118 1
VDD15 VDD16 R80
DDR_A_MA13 119 120 M_ ODT1
A13 ODT1 M_ODT1 <7> 1K_0402_1% C151 1 C142 1 C143 1 C152 1 C144 1 C145 1 C153 1 C146 1 C154 1 C155 1 C147 1 C156 1
DDR_CS1_ DIMMA# 121 122 + C148
<7> DDR_CS1_DIMMA# S1# NC2
123 124 @ @ 220U_6.3V_M
125 VDD17 VDD18 126 +VREF _CA
127 NCTEST VREF_CA 128 2 2 2 2 2 2 2 2 2 2 2 2 2
B DDR_A_D32 129 VSS27 VSS28 130 DDR_ A_ D36 B
DDR_A_D33 131 DQ32 DQ36 132 DDR_ A_ D37
DQ33 DQ37 1 1
133 134 C149 C150
DDR_A_DQS#4 135 VSS29 VSS30 136 R81
DDR_A_DQS4 137 DQS#4 DM4 138 1K_0402_1%
139 DQS4 VSS31 140 DDR_A_D38 2 2
DDR_A_D34 141 VSS32 DQ38 142 DDR_ A_ D39
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_ A_ D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
VSS36 DQS#5
153
155 DM5 DQS5
154
156
DDR_A_DQS5 Layout Note: Layout Note:
DDR_A_D42 157 VSS37 VSS38 158 DDR_ A_ D46 Place near DIMM Place near DIMM
159 DQ42 DQ46 160
DDR_A_D43 DDR_ A_ D47
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_ A_ D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_ A_ D53
167 DQ49 DQ53 168
VSS41 VSS42 +0.75VS
DDR_A_DQS#6
DDR_A_DQS6
169
171 DQS#6 DM6
170
172
DDR_A_DM[0:7] connect to GND
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_ A_ D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_ A_ D61
DQ56 DQ61 1 1 1 1
DDR_A_D57 183 184 C288 C158 C159 C160
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190 2 2 2 2
DDR_A_D58 191 VSS49 VSS50 192 DDR_ A_ D62
A DDR_A_D59 193 DQ58 DQ62 194 DDR_ A_ D63 A
195 DQ59 DQ63 196
R82 VSS51 VSS52
1 2 197 198
10K_0402_ 5% 199 SA0 EVENT# 200 SMB_ DATA_ S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,37,46>
201 202 SMB _CLK_ S3
SA1 SCL SMB_CLK_S3 <13,15,37,46>
1 1 203 204
VTT1 VTT2 +0.75VS
C290 C162 R83 205 206 Title
2.2U_0603_6.3V6K 0.1U_0402_10V6K 10K_0402_5%
G1 G2 Security Classification LC Future Center Secret Data
2 2 LCN_DAN06-K4806-0103
Issued Date 2011/11/01 Deciphered Date 2012/12/31 DDRIII-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 12 of 65
 5 4 3 2 1

DDR3 SO-DIMM B
+1.5V
+1.5V +1.5V

R84
+VREF_DQ_DIMMB
1K_0402_1% [email protected]
For RF request
JDIMM2 ME@
DDR_B_D[0..63] <7>
+VREF _DQ_ DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4 DDR_B_DQS[0..7] <7>
DDR_B_D0 5 6 DDR_ B_ D5
DDR_B_D1 7 DQ0 DQ5 8
1 1 DQ1 VSS3 1 1 1 DDR_B_DQS#[0..7] <7>
R85 C289 C157 9 10 DDR_B_DQS#0 C54 C55 C56
D 1K_0402_1% 11 VSS4 DQS#0 12 DDR_B_DQS0 @ @ @ D
DM0 DQS0 DDR_B_MA[0..15] <7>
13 14
2 2 15 VSS5 VSS6 16 2 2 2
DDR_B_D2 DDR_ B_ D6
17 DQ2 DQ6 18
DDR_B_D3 DDR_ B_ D7
19 DQ3 DQ7 20
21 VSS7 VSS8 22
DDR_B_D8 DDR_ B_ D12
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_ DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <12,7>
31 32
DDR_B_D10 33 VSS11 VSS12 34 DDR_ B_ D14
DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
37 DQ11 DQ15 38
DDR_B_D16 39 VSS13 VSS14 40 DDR_ B_ D20
DDR_B_D17 41 DQ16 DQ20 42 DDR_ B_ D21
43 DQ17 DQ21 44
45 VSS15 VSS16 46
DDR_B_DQS#2
47 DQS#2 DM2 48
DDR_B_DQS2
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_ B_ D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
67 VSS23 VSS24 68
DDR_B_D26 DDR_ B_ D30
69 DQ26 DQ30 70
DDR_B_D27 DDR_ B_ D31
71 DQ27 DQ31 72
VSS25 VSS26
C C

DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_ B_ MA14
<7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR _ B_ MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
89 VDD5 VDD6 90
DDR _B _ MA8 DDR _B _ MA6
A8 A6
DDR_B_MA5 91
93 A5 A4
92
94
DDR_ B_ MA4
Layout Note:
(10uF_0603_6.3V)*8
VDD7 VDD8
DDR_B_MA3
DDR_B_MA1
95
97 A3 A2
96
98
DDR_B_MA2
DDR_B_MA0 Place near DIMM (0.1uF_402_10V)*4
99 A1 A0 100
M_CLK_ DDR2 101 VDD9 VDD10 102 M_ CLK_ DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
M_CLK_ DDR#2 103 104 M_ CLK_ DDR#3
<7> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <7>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_ B_ BS1
A10/AP BA1 DDR_B_BS1 <7>
DDR_B_BS0 109 110 DDR_ B_ RAS# +1.5V
<7> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7>
111 112 +1.5V
113 VDD13 VDD14 114
<7> DDR_B_WE# DDR_B_WE# DDR_ CS2_ DIMMB#
WE# S0# DDR_CS2_DIMMB# <7>
DDR_B_CAS# 115 116 M_ ODT2
<7> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
117 118
VDD15 VDD16 R86
DDR_B_MA13 119 120 M_ODT3
A13 ODT1 M_ODT3 <7> 1K_0402_1%
DDR_CS3_ DIMMB# 121 122
<7> DDR_CS3_DIMMB# S1# NC2 C161 1 C282 1 C163 1 C164 1 C165 1 C166 1 C167 1 C168 1 C169 1 C170 1 C171 1 C172 1
123 124
125 VDD17 VDD18 126 +VREF _CB @ @
127 NCTEST VREF_CA 128
DDR_B_D32 129 VSS27 VSS28 130 DDR_ B_ D36 2 2 2 2 2 2 2 2 2 2 2 2
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37
DQ33 DQ37 1 1
B 133 134 C280 C281 B
DDR_B_DQS#4 135 VSS29 VSS30 136 R87
DDR_B_DQS4 137 DQS#4 DM4 138 1K_0402_1%
139 DQS4 VSS31 140 DDR_B_D38 2 2
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_ B_ D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
DM5 DQS5
155
157 VSS37 VSS38
156
158
Layout Note: Layout Note:
DDR_B_D42 DDR_ B_ D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_ B_ D47 Place near DIMM Place near DIMM
161 DQ43 DQ47 162
163 VSS39 VSS40 164
DDR_B_D48 DDR_ B_ D52
165 DQ48 DQ52 166
DDR_B_D49 DDR_ B_ D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
DQS#6 DM6 +0.75VS
DDR_B_DQS6 171
173 DQS6 VSS43
172
174
DDR_B_DM[0:7] connect to GND
DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
DDR_B_D56 181 VSS46 DQ60 182 DDR_ B_ D61
DDR_B_D57 183 DQ56 DQ61 184
DQ57 VSS47 1 1 1 1
185 186 DDR_B_DQS#7 C173 C174 C175 C176
187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_ B_ D62 2 2 2 2
DDR_B_D59 193 DQ58 DQ62 194 DDR_ B_ D63
195 DQ59 DQ63 196
A 1 R95 2 197 VSS51 VSS52 198 A
10K_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
VDDSPD SDA SMB_DATA_S3 <12,15,37,46>
1 2 201 202 SMB _CLK_ S3
+3VS SA1 SCL SMB_CLK_S3 <12,15,37,46>
R97 10K_0402_5% 203 204 +0.75VS
VTT1 VTT2
1 1
205 206
G1 G2
C177 C178
2.2U_0603_6.3V6K 0.1U_0402_10V6K TYCO_2-2013287-1 Title
2 2 Security Classification LC Future Center Secret Data
Issued Date 2011/11/01 Deciphered Date 2012/12/31 DDRIII-SODIMM SLOT2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 13 of 65
5 4 3 2 1
 5 4 3 2 1

W=20mils W=20mils
+RTCBATT +RTCVCC CMOS U4A
EC and Mini card debug port
2 R99 1 +RTCVCC PCH _ RTCX1 A20 C38 LPC _AD0
1 RTCX1 FW H0 / LAD0 LPC_AD0 <37,45>
1 C183 JCMOS A38 LPC _AD1
1K_0402_5% FW H1 / LAD1 LPC_AD1 <37,45>
1U_0603_10V4Z @ SHORT PADS PCH _ RTCX2 C20 B37 LPC _AD2
C179 RTCX2 FW H2 / LAD2 LPC_AD2 <37,45>
C37 LPC _AD3
1U_0603_10V4Z 2 FW H3 / LAD3 LPC_AD3 <37,45>
R103 1 2 20K _0402 _5% PCH_RTCRST# D20
2 RTCRST# D36 LPC _ FRAME#
PCH_SRTCRST# G22 FW H4 / LFRAME# LPC_FRAME# <37,45>
R100 1 2 20K _0402 _5%
SRTCRST# E36
1 LDRQ0#
D C182 SM_INTRUDER# K22 K36 R104 2 1 10K _0402 _5% D
INTRUDER# LDRQ1# / GPIO23 +3VS
1U_0603_10V4Z @ JME
SHORT PADS PCH _ INTVRMEN C17 V5 SERIRQ
2 INTVRMEN SERIRQ SERIRQ <45>
+RTCVCC
AM3 SATA _DTX _C _IRX_ N0 SSD
SATA0RXN SATA_DTX_C_IRX_N0 <37>
R101 1 2 1M _0402 _5% SM_ INTRUDER# HDA_ BIT_ CLK N34 AM1 SATA_ DTX_ C_ IRX_ P0
HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 <37>
AP7 SATA _ITX _C _ DRX_ N0 C184 2 1 0.01U_ 0402_ 16V7K SATA_ ITX_ DRX_ N0 SATA_ITX_DRX_N0 <37>
R102 1 2 330K _0402 _5% PCH _ INTVRMEN HDA_ SYNC L34 SATA0TXN
AP5 SATA_ ITX_ C_ DRX_ P0 C185 2 1 0. 01U_ 0402_ 16V7K SATA_ ITX_ DRX_ P0 SATA_ITX_DRX_P0 <37>
HDA_SYNC SATA0TXP
HDA _ SPKR T10 AM10 SATA _DTX_ C_ IRX_ N1 HDD
<42> HDA_SPKR SPKR SATA1RXN SATA_DTX_C_IRX_N1 <41>
INTVRMEN HDA _ RST# K34 SATA1RXP
AM8
AP11
SATA _DTX _C _IRX_ P1
SATA _ITX_ C_ DRX_ N1 C273 2 1 0. 01U_ 0402_ 16V7K SATA_ ITX_ DRX_ N1
SATA_DTX_C_IRX_P1 <41>
HDA_RST# SATA1TXN SATA_ITX_DRX_N1 <41>
* H
L
Integrated VRM enable (Default)
Integrated VRM disable
SATA1TXP
AP10 SATA _ITX _C _ DRX_ P1 C272 2 1 0.01U_ 0402_ 16V7K SATA_ ITX_ DRX_ P1
SATA_ITX_DRX_P1 <41>
HDA _ SDIN0 E34 AD7 SATA _DTX _ C_ IRX_ N2 ODD
<42> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <41>
(INTVRMEN should always be pull high.) AD5 SATA_DTX_C_IRX_P2
SATA2RXP SATA_DTX_C_IRX_P2 <41>
G34 AH5 SATA _ITX _C _ DRX_ N2 C186 2 1 0.01U_ 0402_ 16V7K SATA_ ITX_ DRX_ N2_ CONN
HDA_SDIN1 SATA2TXN SATA_ITX_DRX_N2_CONN <41>
AH4 SATA_ITX_C_DRX_P2 C187 2 1 0.01U _0402_ 16V7K SATA_ITX_DRX_P2_CONN
SATA2TXP SATA_ITX_DRX_P2_CONN <41>
C34
HDA_SDIN2 AB8
A34 SATA3RXN AB10
HDA_SDIN3 SATA3RXP AF3
+3VS SATA3TXN AF1
ME _ FLASH R109 1 2 R_ short 0_ 0402_ 5%HDA_ SDOUT A36 SATA3TXP
<45> ME_FLASH HDA_SDO
R105 1 @ 2 1K_0402_5% HDA _ SPKR Y7
SATA4RXN Y5
SATA4RXP
HIGH= Enable ( No Reboot ) R107 1 @ 2 1K_0402_1% PCH _GPIO33 C36
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD3

* LOW= Disable (Default)

+3V_PCH R317 2 @ 1 10K_0402_5% PCH_GPIO13 N32
HDA_DOCK_RST# / GPIO13
SATA4TXP
AD1

Y3
SATA5RXN Y1
C SATA5RXP AB3 C
R110 2 1 51 _0402 _5% PCH_ JTAG_ TCK J3 SATA5TXN AB1
JTAG_TCK SATA5TXP
+3V_PCH PCH _JTAG_ TMS H7 Y11 +1.05VS_VCC_SATA
JTAG_TMS SATAICOMPO
R106 2 @ 1 1K_0402_5% HDA _ SDOUT PCH _ JTAG_ TDI K5 Y10 SATA_ COMP R111 1 2 37.4_ 0402_ 1%
JTAG_TDI SATAICOMPI

* Low = Disabled (Default)

High = Enabled
PCH _ JTAG_ TDO H1
JTAG_TDO
SATA3RCOMPO
AB12 +1.05VS_SATA3
[Flash Descriptor Security Overide]
AB13 SATA3_COMP R113 1 2 49.9 _0402 _ 1%
SATA3COMPI
SPI_CLK_PCH_0 R298 1 2 33 _0402 _5%
SPI _CLK _ PCH _ 1 R299 1 2 33_ 0402_ 5% SPI_ CLK_ PCH T3 AH1 RBIAS_ SATA3 R115 1 2 750_ 0402_ 1%
SPI_CLK SATA3RBIAS
+3V_PCH SPI _SB_ CS0#_ R R130 2 1 R_ short 0_ 0402_ 5% SPI_ SB_ CS0# Y14
SPI_CS0#
T1 HDD_LED# <47>
R108 2 1 1K _0402 _5% HDA_ SYNC SPI_ CS1#_ R R303 2 1 R_ short 0_ 0402_ 5% SPI_ CS1#
SPI_CS1# P3 HDD _ LED# R120 2 1 10K_0402_5%
SATALED# +3VS
This signal has a weak internal pull-down SPI _SI_ R R133 1 2 33_ 0402_ 5%
SPI _SI_ R1 R204 1 2 33_ 0402_ 5% SPI_ SI V4 V14 PCH_ GPIO21 R119 2 1 10K_ 0402_ 5%
SPI_MOSI SATA0GP / GPIO21 +3VS
On Die PLL VR Select is supplied by
SPI _SO_ L R131 2 1 33_ 0402_ 5% SPI_ SO_ R U3 P1 SATA_ DET# R316 2 1 10K_ 0402_ 5%
1.5V when smapled high (Default) SPI_MISO SATA1GP / GPIO19 +3VS
* 1.8V when sampled low
Needs to be pulled High for Chief River platfrom
SPI_SO_L1 R294 2 1 33 _0402 _5%
SATA_DET# <37>
PANTHER-POINT_FCBGA989

B PCH _ RTCX1 B
For EMI
HDA AUDIO 1 R98 2 PCH _ RTCX2
+5VS SPI _CLK_ PCH
10M_0402_5%
R112 1 2 HDA_BIT_CLK Y1
<42> HDA_BITCLK_AUDIO
33_0402_5% 1 2
R124 @
R114 1 2 HDA _SYNC_ R 3 1 HDA_ SYNC 32.768KHZ_12.5PF_CM31532768DZFT 33_0402_5%
<42> HDA_SYNC_AUDIO
33_0402_5% 1 1
Q10
2 HDA _ RST# C180 C181
<42> HDA_RST_AUDIO# R116 1 BSS138_NL_SOT23-3 C190 @
18P_0402_50V8J 18P_0402_50V8J
33_0402_5% R1353 22P_0402_50V8J
1M_0402_5% 2 2
R118 1 2 HDA _ SDOUT
<42> HDA_SDOUT_AUDIO
33_0402_5%

4MB P/N : SA00005P500 2MB P/N : SA00003FO10

+3VS +3VS
+3V_PCH +3V_PCH +3V_PCH

R127 1 2 3.3K _0402_ 5% SPI_ W P# R292 1 2 3.3K_ 0402_ 5% SPI_ W P#_ 1

R129 1 2 3 .3K _ 0402_ 5% SPI_ HOLD# R246 1 2 3. 3K_ 0402_ 5% SPI_ HOLD#_ 1
R121 R122 R123
@ 200_0402_5% @ 200_0402_5% @ 200_0402_5% +3VS +3VS
U5 U9
A SPI _SB_ CS0#_ R 1 8 SPI_ CS1#_ R 1 8 A
CS# VCC 1 CS# VCC 1
PCH _JTAG_ TDO PCH _ JTAG_ TMS PCH_ JTAG_ TDI SPI_ SO_ L 2 7 SPI_ HOLD# SPI_ SO_ L1 2 7 SPI_ HOLD#_ 1
SPI_W P# 3 DO HOLD# 6 SPI_CLK_PCH_0 C191 SPI_WP#_1 3 DO(IO1) HOLD#(IO3) 6 SPI_CLK_PCH_1 C275
4 W P# CLK 5 SPI _SI_ R 0.1U_0402_16V4Z 4 WP#(IO2) CLK 5 SPI_ SI_ R1 0.1U_0402_16V4Z
R125 R128 GND DI 2 GND DI(IO0) 2
R126
@ 100_0402_1% @ 100_0402_1% @ 100_0402_1% W 25Q32BVSSIG_SO8 W 25Q16BVSSIG_SO8

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (1/9) SATA,HDA,SPI, LPC, XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 14 of 65
5 4 3 2 1
 5 4 3 2 1

DIMM1, DIMM2, Mini CARD, TP

+3VS
U4B
R136 2N7002KDWH R137
+3V_PCH 1 2 2.2K _0402 _5% 2 1 2.2K _ 0402_ 5%
PCIE _PRX_ DTX_ N1 BG34 Vth= min 1V, max 2.5V
<38> PCIE_PRX_DTX_N1 PERN1 R135 ESD 2KV R138
PCIE _PRX_ DTX_ P1 BJ34 E12 PCH_ GPIO11 1 2 2.2K_ 0402_ 5% 2 1 2.2K_ 0402_ 5%
<38> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11
LAN <38> PCIE_PTX_C_DRX_N1
C192 1 2 0.1U _0402_ 10V7K PCIE _PTX_ DRX_ N1 AV32
PETN1 H14
<38> PCIE_PTX_C_DRX_P1
C193 1 2 0.1U _0402_ 10V7K PCIE _PTX_ DRX_ P1 AU32
PETP1 SMBCLK
PCH_ SMBCLK 20120731 --> change to +3VS
PCH _ SMBCLK 6 1 SMB _ CLK_ S3
C9 PCH_SMBDATA SMB_CLK_S3 <12,13,37,46>
PCIE _PRX_ DTX_ N2 BE34
<37> PCIE_PRX_DTX_N2 PERN2 SMBDATA
PCIE _PRX_ DTX_ P2 BF34 Q60A
<37> PCIE_PRX_DTX_P2 PERP2
WLAN <37> PCIE_PTX_C_DRX_N2
C194 1 2 0.1U _0402_ 10V7K PCIE _PTX_ DRX_ N2 BB32
PETN2
2N7002KDW H_SOT363-6
C195 1 2 0.1U _0402_ 10V7K PCIE_PTX_DRX_P2 AY32
D <37> PCIE_PTX_C_DRX_P2 PETP2 A12 D
PCH _ SMBDATA 3 4 SMB _ DATA_ S3
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_ P CH <7> SMB_DATA_S3 <12,13,37,46>
Q60B
BJ36 PERN3 C8 SML0CLK 2N7002KDW H_SOT363-6
AV34 PERP3 SML0CLK
AU34 PETN3 G12 SML0DATA
PETP3 SML0DATA
PCIE _PRX_ DTX_ N4 BF36
<44> PCIE_PRX_DTX_N4 PERN4
PCIE _PRX_ DTX_ P4 BE36
<44> PCIE_PRX_DTX_P4 PERP4 C13 PCH_ HOT#
Card Reader <44> PCIE_PTX_C_DRX_N4
C277 1 2 0 .1U _ 0402_ 10V7K PCIE _ PTX_ DRX_ N4 AY34
PETN4 SML1ALERT# / PCHHOT# / GPIO74 VGA, EC, Thermal Sensor
C276 1 2 0.1U _0402_ 10V7K PCIE _PTX_ DRX_ P4 BB34
<44> PCIE_PTX_C_DRX_P4 PETP4 E14 SML1CLK
BG37 SML1CLK / GPIO58 R141
+3V_PCH 1 2 2.2K _0402 _5% +3VS
BH37 PERN5 M16 SML1DATA
AY36 PERP5 SML1DATA / GPIO75 R142
BB36 PETN5
1 2 2.2K _0402 _5% 20120731 --> change to +3VS
PETP5
BJ38 SML1CLK 6 1 EC_SMB_CK2
BG38 PERN6 EC_SMB_CK2 <23,32,40,45>
AU36 PERP6 M7 Q61A
AV36 PETN6 CL_CLK1 2N7002KDW H_SOT363-6
PETP6
BG40 T11 SML1DATA 3 4 EC _ SMB_ DA2
BJ40 PERN7 CL_DATA1 EC_SMB_DA2 <23,32,40,45>
Q61B
AY40 PERP7 2N7002KDW H_SOT363-6
BB40 PETN7 P10
PETP7 CL_RST1#
BE38
BC38 PERN8
AW 38 PERP8
AY38 PETN8
PETP8
M10 CLK_REQ_GPU#_R +3V_PCH
C PEG_A_CLKRQ# / GPIO47 CLK_REQ_GPU#_R <23> C
CLK _PCIE_ LAN# Y40
<38> CLK_PCIE_LAN# Y39 CLKOUT_PCIE0N
CLK _PCIE_ LAN
<38> CLK_PCIE_LAN CLKOUT_PCIE0P R134
LAN AB37 CLK _PCIE _ VGA# PCH _ GPIO11 2 1 10K _ 0402_ 5%
J2 CLKOUT_PEG_A_N CLK_PCIE_VGA# <23>
CLKREQ _ LAN# AB38 CLK _PCIE_ VGA
<38> CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <23> R329
DRAMRST _CNTRL _ PCH 2 1 1K _0402_ 5%

AB49 R335
CLK _ PCIE_ W LAN1# AV22 CLK_ CPU_ DMI# SML0CLK 1 2 2. 2K_ 0402_ 5%
<37> CLK_PCIE_W LAN1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <6>
CLK _ PCIE_ W LAN1 AB47 AU22 CLK _ CPU_ DMI
<37> CLK_PCIE_W LAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6> R336
WLAN W LAN _ CLKREQ1# M1
SML0DATA 1 2 2.2K _0402 _5%
<37> W LAN_CLKREQ1# PCIECLKRQ1# / GPIO18 R140
AM12 PCH_HOT# 2 1 10K _0402 _5%
CLKOUT_DP_N AM13
AA48 CLKOUT_DP_P R202
CLK_REQ_GPU#_R 1 2 10K _0402 _5%
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R155 1 2 10K _0402 _5%
V10 CLKIN_DMI_N
Only for 15" TV function PCH _GPIO20
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
BE18 CLK _BUF_ CPU_ DMI R157 1 2 10K_ 0402_ 5%

CLK _ PCIE_ CARD_ PCH# Y37 BJ30 CLKIN_ DMI2# R159 1 2 10K_ 0402_ 5%
<44> CLK_PCIE_CARD_PCH# CLK _PCIE_ CARD_ PCH Y36 CLKOUT_PCIE3N CLKIN_GND1_N
Card Reader BG30 CLKIN _ DMI2 R160 1 2 10K_ 0402_ 5%
<44> CLK_PCIE_CARD_PCH CLKOUT_PCIE3P CLKIN_GND1_P XTAL25 _IN
PCH _GPIO25 A8
PCIECLKRQ3# / GPIO25 G24 XTAL25_ OUT 1 R169 2
CLK _BUF_ DREF_ 96M# R162 1 2 10K_ 0402_ 5%
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R163 1 2 10K _0402 _5%
Y43 CLKIN_DOT_96P 1M_0402_5%
Y45 CLKOUT_PCIE4N
CLKOUT_PCIE4P AK7 CLK _BUF_ PCIE_ SATA# R164 1 2 10K_ 0402_ 5% Y2
PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R166 1 2 10K _0402 _5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P 1 3
1 3
V45 K45 CLK _BUF_ ICH_ 14M R167 1 2 10K_ 0402_ 5% GND GND
V46 CLKOUT_PCIE5N REFCLK14IN
B CLKOUT_PCIE5P 2 4 B
PCH _GPIO44 L14 H45 CLK _ PCI_ LPBACK 1 25MHZ_10PF_7V25000014 1
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
C196 C197
CLK _ PCIE_ 2VGA# AB42 V47 XTAL25 _ IN 10P_0402_50V8J 10P_0402_50V8J
<32> CLK_PCIE_2VGA# CLKOUT_PEG_B_N XTAL25_IN V49 2 2
2nd VGA CLK _PCIE_ 2VGA AB40 XTAL25 _ OUT
<32> CLK_PCIE_2VGA CLKOUT_PEG_B_P XTAL25_OUT
<32> CLK2_REQ_GPU#_R CLK2 _REQ _ GPU#_ R E6 +1.05VS_VCCDIFFCLKN
PEG_B_CLKRQ# / GPIO56 20120816 --->
Y47 XCLK _ RCOMP R171 1 2 90.9 _ 0402_ 1% 1. change P/N to 7V2500014(10pf), SJ10000E80J
+3V_PCH V40 XCLK_RCOMP 2. C196, C197 change to 10pf
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P
R152 2 1 10K _0402 _ 5% CLKREQ _ LAN# PCH_ GPIO45 T13
PCIECLKRQ6# / GPIO45
R168 2 1 10K _0402 _ 5% PCH _GPIO25 V38 K43 +3VS
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
R165 2 1 10K _0402 _ 5% PCH _GPIO26 CLKOUT_PCIE7P F47 R182 2 1 10K_ 0402_ 5%
PCH _GPIO46 K12 CLKOUTFLEX1 / GPIO65
R147 2 1 10K _0402 _ 5% PCH_GPIO44 PCIECLKRQ7# / GPIO46 H47 S_DGPU_RST_R R1504 1 2 0_ 0402_ 5%
CLKOUTFLEX2 / GPIO66 S_DGPU_RST <18,32>
AK14
R170 2 1 10K_0402_5% CLK2_REQ_GPU#_R AK13 CLKOUT_ITPXDP_N K49 PCH_GPIO67
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 <19>
R172 2 1 10K _0402 _ 5% PCH_GPIO45
BIOS Request SKU ID Reserve for EMI please close to
PANTHER-POINT_FCBGA989 PCH
R174 2 1 10K _0402 _ 5% PCH _GPIO46

@ R175 @ C198

+3VS
GPIO64, 65 that only for GC6 33_0402_5%
2 1
22P_0402_50V8J
1 2
CLK _BUF_ ICH_ 14M
1. GPIO64 : S_DGPU_GC6_EN
2. GPIO65 : S_DGPU_PWROK
A R158 2 1 10K _0402 _ 5% W LAN _ CLKREQ1# A
@ R176 @ C199
R308 2 1 10K _0402 _ 5% PCH_GPIO20 33_0402_5% 22P_0402_50V8J
CLK _ PCI_ LPBACK 2 1 1 2

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (2/9) PCIE, SMBUS, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 15 of 65
5 4 3 2 1
 5 4 3 2 1

D D

U4C

DMI _CTX_ PRX_ N0 BC24 BJ14 FDI_ CTX_ PRX_ N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
DMI _CTX_ PRX_ N1 BE20 AY14 FDI_ CTX_ PRX_ N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
DMI _CTX_ PRX_ N2 BG18 BE14 FDI_ CTX_ PRX_ N2
<5> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <5>
DMI _CTX_ PRX_ N3 BG20 BH13 FDI_ CTX_ PRX_ N3
<5> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <5>
BC12 FDI _CTX_ PRX_ N4
FDI_RXN4 FDI_CTX_PRX_N4 <5>
DMI _CTX_ PRX_ P0 BE24 BJ12 FDI_ CTX_ PRX_ N5
<5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
DMI _CTX_ PRX_ P1 BC20 BG10 FDI_ CTX_ PRX_ N6
<5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
DMI _CTX_ PRX_ P2 BJ18 BG9 FDI_ CTX_ PRX_ N7
<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5>
DMI _CTX_ PRX_ P3 BJ20
<5> DMI_CTX_PRX_P3 DMI3RXP BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 <5>
DMI _CRX_ PTX_ N0 AW 24 BB14 FDI_ CTX_ PRX_ P1
<5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5> +RTCVCC
DMI_CRX_PTX_N1 AW 20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
+3VS DMI _CRX_ PTX_ N2 BB18 BG13 FDI_ CTX_ PRX_ P3
<5> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <5>
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <5>
BG12 FDI _CTX_ PRX_ P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
1 DMI _CRX_ PTX_ P0 AY24 BJ10 FDI_ CTX_ PRX_ P6 R179
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
C1060 DMI _CRX_ PTX_ P1 AY20 BH9 FDI_ CTX_ PRX_ P7 330K_0402_5%
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
0.1U_0402_16V4Z DMI _CRX_ PTX_ P2 AY18
<5> DMI_CRX_PTX_P2 DMI2TXP
DMI _CRX_ PTX_ P3 AU18
2 <5> DMI_CRX_PTX_P3 DMI3TXP AW 16 FDI _INT
FDI_INT FDI_INT <5>
DSW ODVREN
1 R177 2 BJ24 AV12 FDI_ FSYNC0
DMI _ IRCOMP
+1.05VS DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
VGATE 2
<59> VGATE B 4 49.9_0402_1% BG25 BC10 FDI _FSYNC1
Y SYS_PWROK <6> DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
PCH_PW ROK 1
A 1 R178 2 RBIAS _CPY BH21
DMI2RBIAS FDI_LSYNC0
AV14 FDI_ LSYNC0
FDI_LSYNC0 <5>
* DSWODVREN - On Die DSW VR Enable
H Enable @
R183
330K_0402_5%
C 750_0402_1% L Disable C
U6 @ R180 BB10 FDI _ LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <5>
MC74VHC1G08DFT2G SC70 5P 100K_0402_1% 4mil width and place
within 500mil of the PCH
A18 DSW ODVREN
DSW VRMEN

For Deep S3 R1457 2 1 R _short 0_ 0402_ 5% SUSACK# _ R C12 E22 PCH_ DPW ROK_ R R181 1 2 R_ short 0_ 0402_ 5% DPW ROK_ EC For Deep S3
<45> SUSACK# SUSACK# DPW ROK DPW ROK_EC <45>

R184 2 1 10K _0402 _5% SYS_RST# K3 B9 W AKE# R185 1 2 R_ short 0_ 0402_ 5% PCIE_W AKE#
+3VS SYS_RESET# W AKE# PCIE_W AKE# <19,37,38>

SYS_ PW ROK P12 N3 PM _ CLKRUN# R253 1 2 10K_ 0402_ 5%

SYS_PWROK CLKRUN# / GPIO32
+3V_PCH
2 R190 1 PW ROK L22 G8 SUS _ STAT#
<45> PCH_PW ROK PW ROK SUS_STAT# / GPIO61 PAD T60
W AKE# R186 1 2 10K _0402 _ 5%
R_short 0_0402_5%
APWROK can be connect to R191
PWROK if iAMT disable 2 1 APW ROK L10 N14 SUSCLK
APW ROK SUSCLK / GPIO62 PAD T61
R_short 0_0402_5%
PM _ DRAM_ PW RGD B13 D10 PM_ SLP_ S5#
<6> PM_DRAM_PW RGD DRAMPW ROK SLP_S5# / GPIO63 PAD T62

R193 1 2 R _short 0_ 0402_ 5% PCH_RSMRST#_R C21 H4 PM_SLP_S4#

<45> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <45>

For Deep S3 R1455 2 1 R _short 0_ 0402_ 5% SUSW ARN# _ R K16 F4 PM_ SLP_ S3#
<45> SUSW ARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <45>

R198 1 2 R _short 0_ 0402_ 5% PBTN _ OUT#_ R E20 G10 Can be left NC when IAMT is not support on the platfrom
B
<45> PBTN_OUT# PW RBTN# SLP_A# B

R208 1 2 R _short 0_ 0402_ 5% AC _ PRESENT _ R H20 G16 PM_ SLP_ SUS#_ R R1447 2 1 R_ short 0_ 0402_ 5% For Deep S3
<45> AC_PRESENT ACPRESENT / GPIO31 SLP_SUS# PM_SLP_SUS# <45,51>

R200 1 2 8.2K _0402_ 5% PCH_ GPIO72 E10 AP14 H_ PM_ SYNC

BATLOW # / GPIO72 PMSYNCH H_PM_SYNC <6>

R201 2 1 10K _0402 _5% RI# A10 K14 PCH_GPIO29

+3V_PCH RI# SLP_LAN# / GPIO29 PAD T74
Can be left NC if no use integrated LAN.
PANTHER-POINT_FCBGA989 10/06 Test point request

+3V_PCH
+3VS

R192 2 1 200 _0402 _ 5% PM _ DRAM_ PW RGD R1290 2 @ 1 200_0402_5% PM_DRAM_PW RGD

R194 2 1 10K _ 0402_ 5% SUSW ARN# 7/28 Modify follow Module Design.

+3VALW

R195 2 1 200K _0402 _ 5% AC _ PRESENT _ R R197 2 1 10K_ 0402_ 5% PCH_ RSMRST#_ R

A A

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (3/9) DMI,FDI,PM,

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 16 of 65
5 4 3 2 1
 5 4 3 2 1

D D

+3VS

U4D
OPT@
R836 2.2K_ 0402_ 5% EDID_ CLK PCH_ ENBKL J47 AP43
<34> PCH_ENBKL PCH _ ENVDD M45 L_BKLTEN SDVO_TVCLKINN AP45
OPT@ EDID_ DATA <34> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
R835 2.2K_ 0402_ 5%
PCH _ PW M P45 AM42
<34> PCH_PW M L_BKLTCTL SDVO_STALLN AM40
EDID _ CLK T40 SDVO_STALLP
OPT@ <34> EDID_CLK L_DDC_CLK +3VS
R205 1 2 2.2K _0402_ 5% CTRL_CLK EDID_DATA K47 AP39
<34> EDID_DATA L_DDC_DATA SDVO_INTN AP40
OPT@ SDVO_INTP
R261 1 2 2.2K _0402_ 5% CTRL_DATA CTRL_CLK T45
L_CTRL_CLK OPT@
CTRL _ DATA P39 HDMICLK R203 2 1 2.2K _0402 _5%
L_CTRL_DATA
LVDS _IBG AF37 P38 HDMICLK
LVD_IBG SDVO_CTRLCLK HDMICLK <36> OPT@
AF36 M39 HDMIDAT HDMIDAT R267 2 1 2.2K _0402 _5%
OPT@ LVD_VBG SDVO_CTRLDATA HDMIDAT <36>
R257 2 1 2 .37K _ 0402_ 1% LVDS _ IBG
AE48
AE47 LVD_VREFH
Remove netname LVD_REF LVD_VREFL DDPB_AUXN
AT49
AT47
DDPB_AUXP AT40 TMDS _B _HPD
AK39 DDPB_HPD TMDS_B_HPD <36>
LVDS _ ACLK#
<34> LVDS_ACLK# LVDSA_CLK# AV42
LVDS_ACLK AK40 TMDS_B_DATA2#_PCH
<34> LVDS_ACLK LVDSA_CLK DDPB_0N TMDS_B_DATA2#_PCH <36>
AV40 TMDS _B _ DATA2_ PCH
LVDS_A0# AN48 DDPB_0P AV45 TMDS_B_DATA1#_PCH TMDS_B_DATA2_PCH <36>
C <34> LVDS_A0# LVDS _A1# AM47 LVDSA_DATA#0 DDPB_1N AV46 TMDS _B_ DATA1_ PCH TMDS_B_DATA1#_PCH <36> C
<34> LVDS_A1# AK47 LVDSA_DATA#1 DDPB_1P AU48 TMDS_B_DATA1_PCH <36>
LVDS _A2# TMDS _ B_ DATA0#_ PCH
<34> LVDS_A2# LVDSA_DATA#2 DDPB_2N AU47 TMDS_B_DATA0#_PCH <36>
AJ48 TMDS _B _ DATA0_ PCH
LVDSA_DATA#3 DDPB_2P TMDS_B_DATA0_PCH <36>
AV47 TMDS _B _ CLK#_ PCH
LVDS _A0 AN47 DDPB_3N AV49 TMDS _B_ CLK_ PCH TMDS_B_CLK#_PCH <36>
<34> LVDS_A0 LVDS _A1 AM49 LVDSA_DATA0 DDPB_3P TMDS_B_CLK_PCH <36>
<34> LVDS_A1 AK49 LVDSA_DATA1
LVDS _A2
<34> LVDS_A2 AJ47 LVDSA_DATA2 P46
LVDSA_DATA3 DDPC_CTRLCLK P42
DDPC_CTRLDATA
AF40
AF39 LVDSB_CLK# AP47
LVDSB_CLK DDPC_AUXN AP49
AH45 DDPC_AUXP AT38
AH47 LVDSB_DATA#0 DDPC_HPD
AF49 LVDSB_DATA#1 AY47
AF45 LVDSB_DATA#2 DDPC_0N AY49
LVDSB_DATA#3 DDPC_0P AY43
AH43 DDPC_1N AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
OPT@ LVDSB_DATA1 DDPC_2N
R266 2 1 150 _0402 _ 1% DAC_ BLU AF47 BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
LVDSB_DATA3 DDPC_3N BB49
OPT@ DDPC_3P
R264 2 1 150 _0402 _ 1% DAC_GRN

DAC_BLU N48 M43

OPT@ <35> DAC_BLU CRT_BLUE DDPD_CTRLCLK
R262 2 1 150 _0402 _ 1% DAC_ RED DAC_ GRN P49 M36
<35> DAC_GRN T49 CRT_GREEN DDPD_CTRLDATA
DAC_RED
<35> DAC_RED CRT_RED
AT45
CRT _DDC_ CLK T39 DDPD_AUXN AT43
<35> CRT_DDC_CLK M40 CRT_DDC_CLK DDPD_AUXP BH41
CRT _DDC_ DATA
B <35> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD B
+3VS BB43
CRT _HSYNC M47 DDPD_0N BB45
<35> CRT_HSYNC CRT _VSYNC M49 CRT_HSYNC DDPD_0P BF44
OPT@ <35> CRT_VSYNC CRT_VSYNC DDPD_1N
R848 1 2 2 .2K _0402_ 5% CRT_ DDC_ CLK BE44
DDPD_1P BF42
CRT_IREF T43 DDPD_2N BE42
OPT@ DAC_IREF DDPD_2P BJ42
R849 1 2 2.2K _0402_ 5% CRT_DDC_DATA T42
CRT_IRTN DDPD_3N BG42
R211 DDPD_3P
1K_0402_1% PANTHER-POINT_FCBGA989

A A

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (4/9) LVDS,CRT,DP,HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 17 of 65
5 4 3 2 1
 5 4 3 2 1

+3VS
RP2
8 1 PCI _ PIRQA#
7 2 PCI _ PIRQD#
6 3 PCI _ PIRQC#
5 4 PCI _PIRQB# U4E
AY7
RSVD1 AV7
8.2K_0804_8P4R_5%
BG26 RSVD2 AU3
RP1 BJ26 TP1 RSVD3 BG4
8 1 PCH _GPIO2 BH25 TP2 RSVD4
7 2 DGPU_PW R_EN BJ16 TP3 AT10
D 6 3 PCH _GPIO4 BG16 TP4 RSVD5 BC8 D
5 4 ODD_DA#_R AH38 TP5 RSVD6
AH37 TP6 AU2
8.2K_0804_8P4R_5% AK43 TP7 RSVD7 AT4
AK45 TP8 RSVD8 AT3
C18 TP9 RSVD9 AT1
+3VS N30 TP10 RSVD10 AY3
PPT EDS DOC#474146 H3 TP11 RSVD11 AT5
R305 1 @ 2 8.2K_0402_5% PCH _GPIO51 AH12 TP12 RSVD12 AV3
AM4 TP13 RSVD13 AV1
R297 1 @ 2 8.2K_0402_5% DGPU _GC6_ EN USB3.0 AM5
Y13
TP14
TP15
RSVD14
RSVD15
BB1
BA3
R213 1 2 8 .2K _ 0402_ 5% PCH_ GPIO5 K24 TP16 RSVD16 BB5
L24 TP17 RSVD17 BB3
Port1 AB46 TP18 RSVD18 BB7
R225 1 2 8.2K _0402_ 5% PCH_WL_OFF#
AB45 TP19 RSVD19 BE8
NVDD_PW R_EN TP20 RSVD20 BD4
R212 1 2 8.2K _0402_ 5% Port2 RSVD21 BF6
R252 1 2 8.2K _0402_ 5% DGPU_HOLD_RST# RSVD22

Port3 LEFT USB B21 AV5

M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
1 2 DGPU _GC6_ EN BG46 TP23 AT8
R306 @ 8.2K_0402_5% Port4 TP24 RSVD25
R214 1 @ 2 8.2K_0402_5% DGPU _ HOLD_ RST# AY5
RSVD26 BA2
BE28 RSVD27
BC30 USB3Rn1 AT12
USB30 _RX_ N3 BE32 USB3Rn2 RSVD28 BF3
<48> USB30_RX_N3 BJ32 USB3Rn3 RSVD29
BC28 USB3Rn4
2 PCH_WL_OFF# BE30 USB3Rp1 USB DEBUG = PORT1 AND PORT9
R215 @ 1 1K_0402_5%
C USB30 _RX_ P3 BF32 USB3Rp2 C
<48> USB30_RX_P3 BG32 USB3Rp3 C24 USB20 _ N0
AV26 USB3Rp4
USB3Tn1
USBP0N
USBP0P
A24 USB20 _ P0
USB20_N0
USB20_P0
<34>
<34>
Camera
BB26 C25
USB30 _TX_ N3 AU28 USB3Tn2 USBP1N B25
A16 swap overide Strap/Top-Block <48> USB30_TX_N3 AY30 USB3Tn3 USBP1P C26 USB20 _ N2
Swap Override jumper AU26 USB3Tn4 USBP2N A26 USB20 _ P2
USB20_N2 <48>
LEFT USB
AY26 USB3Tp1 USBP2P K28 USB20_P2 <48>
USB30_TX_P3 AV28 USB3Tp2 USBP3N H28
<48> USB30_TX_P3 AW 30 USB3Tp3 USBP3P E28
Low = A16 swap USB3Tp4 USBP4N D28
override/Top-Block USBP4P C28 USB20 _ N5
PCI_GNT3# Swap Override enabled USBP5N
USBP5P
A28 USB20_P5
USB20_N5
USB20_P5
<49>
<49>
RIGHT USB 1 (CHARGER PORT, SUB/B)
C29
USBP6N B29
**High=Default USBP6P
* PCI _ PIRQA#
PCI _ PIRQB#
K40
K38 PIRQA#
PIRQB#
USBP7N
USBP7P
N28
M28 Some PCH config not support USB port 6 & 7.
PCI _ PIRQC# H38 L30
PCI _ PIRQD# G38 PIRQC# USBP8N K30
<23> DGPU_HOLD_RST# PIRQD# USBP8P G30 USB20 _N9
<15,32> S_DGPU_RST
R1505 1 @ 2 0_0402_5% DGPU _HOLD_ RST# C46
REQ1# / GPIO50
USBP9N
USBP9P
E30 USB20 _ P9 USB20_N9 <49>
USB20_P9 <49>
RIGHT USB 2 (SUB/B)
NVDD _PW R_ EN C44 C30 USB20 _ N10
<58>
<23,51>
NVDD_PW R_EN
DGPU_PW R_EN
DGPU _PW R_ EN E40 REQ2# / GPIO52
REQ3# / GPIO54
USBP10N
USBP10P
A30 USB20 _ P10
USB20_N10 <37>
USB20_P10 <37>
WLAN
L32
PCH _GPIO51 D47 USBP11N K32
E42 GNT1# / GPIO51 USBP11P G32
GPIO53 => This Signal has a weak internal pull-up. <27> DGPU_GC6_EN
DGPU_GC6_EN
F46 GNT2# / GPIO53 USBP12N E32
PCH _W L_ OFF#
NOTE: The internal pull-up is disabled after <37> PCH_W L_OFF# GNT3# / GPIO55 USBP12P C32 USB20_N13
PLTRST# deasserts. USBP13N
USBP13P
A32 USB20 _P13
USB20_N13
USB20_P13
<47>
<47>
BT
PCH_GPIO2 G42
ODD _DA#_R G40 PIRQE# / GPIO2
<41> ODD_DA#_R PCH _GPIO4 C42 PIRQF# / GPIO3 C33 USBRBIAS 1 R218 2 +3V_PCH
B D44 PIRQG# / GPIO4 USBRBIAS# B
PCH _GPIO5
PIRQH# / GPIO5 Within 500 mils 22.6_0402_1%
RP3
B33 USB _OC5# 4 5
K10 USBRBIAS USB _OC2# 3 6
20111024 Del PCI_PME# PME# USB _OC7# 2 7
PLT _ RST# C6 A14 USB _OC0# USB_ OC0# 1 8
<23,32,37,38,44,45,6> PLT_RST# PLTRST# OC0# / GPIO59 K20 USB_OC1#
OC1# / GPIO40 B17 USB _OC2# USB_OC1# <48> USB3 Port3, USB2 Port2 10K_1206_8P4R_5%
R219 1 2 22 _0402_ 5% CLK_PCI_LPBACK_R H49 OC2# / GPIO41 C16 USB_OC3# USB_OC2# <49> USB2 Port5, Charger Port
<15> CLK_PCI_LPBACK 2 H43 CLKOUT_PCI0 OC3# / GPIO42 L16
R220 1 22 _0402_ 5% CLK_ PCI_ EC_ R USB_ OC4#
<45> CLK_PCI_EC
R173 2 1 22 _0402_ 5% CLK_ PCI_ DB_ R J48 CLKOUT_PCI1 OC4# / GPIO43 A16 USB_ OC5# USB_OC4# <49> USB2 Port9, Right USB (Sub/B)
<37> CLK_PCI_DB CLKOUT_PCI2 OC5# / GPIO9
@ K42 D14 USB _OC6# RP4
H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB _OC7# USB _ OC6# 4 5
CLKOUT_PCI4 OC7# / GPIO14 USB _OC1# 3 6
USB _OC4# 2 7
PANTHER-POINT_FCBGA989 USB _OC3# 1 8

10K_1206_8P4R_5%

PCH _GPIO51 R221 1 @ 2 1K_0402_5%

PLT _ RST#

Boot BIOS Strap bit1 BBS1

R223
Boot BIOS 100K_0402_5%
Destination
Bit11 Bit10
0 1 Reserved
A
GNT1#/ A

GPIO51 1 0 Reserved
1 1 * SPI (Default)
0 0 LPC
Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (5/9) PCI, USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 18 of 65
5 4 3 2 1
 5 4 3 2 1

+3VS
SKU ID

Function PCH_GPIO38 PCH_GPIO67 PCH_GPIO70

R711 R708 R704

Optimus 0 0 X
Reserve 0 1 X @ @

DIS PCH _GPIO38

(SLI) 1 0 X
PCH _GPIO67
<15> PCH_GPIO67
D Reserve 1 1 X PCH _GPIO70 D

14" X X 0
+3VS
@
15" X X 1 R712 R709 R706
R1493 2 1 10K _0402 _ 5% EC _ SCI# 0_04 02_ 5% 2 1 R234 GC6_EVENT#_R
<23,32,45> GC6_EVENT#

+3V_PCH R233 1 2 10K _0402 _ 5%

+3VS
R235 2 1 10K _0402 _ 5% EC _ SMI# U4F

T7 C40 S_DGPU_PWROK
BMBUSY# / GPIO0 TACH4 / GPIO68 S_DGPU_PWROK <32>
R227 1 2 10K _0402 _ 5% PCH_GPIO1 A42 B41 S_DGPU_PWR_EN
TACH1 / GPIO1 TACH5 / GPIO69 S_DGPU_PWR_EN <32,51> +3VS
R228 1 2 10K _0402 _ 5% PCH_GPIO6 H36 C41 PCH_GPIO70 9/18 Reseve for SKU ID
+3VS TACH2 / GPIO6 TACH6 / GPIO70 S _DGPU _ PW R_ EN R268 1 2 10K_ 0402_ 5%
EC _ SCI# E38 A40 S _NVDD _ PW R_ EN
<45> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71 S_NVDD_PW R_EN <32>
GPIO28 S _ NVDD _ PW R_ EN R237 1 2 10K_ 0402_ 5%
On-Die PLL Voltage Regulator <45> EC_SMI#
EC _ SMI# C10
GPIO8
This signal has a weak internal pull up
R229 1 @ 2 10K_0402_5% PCH _GPIO12 C4
+3V_PCH LAN_PHY_PW R_CTRL / GPIO12
* H
L
On-Die voltage regulator enable
On-Die PLL Voltage Regulator disable R230 1 2 10K _0402 _ 5% EC_ LID_ OUT# G2
GPIO15 A20GATE
P4
R236 1 2 10K _0402 _ 5%
+3VS
GATEA20 <45>
<45> EC_LID_OUT# AU16
R240 1 @ 2 1K_0402_5% PCH_GPIO28
R231 1 2 10K _0402 _ 5% PCH_GPIO16 U2 PECI
+3VS SATA4GP / GPIO16
R232 1 2 10K _0402 _ 1% P5 KBRST#
RCIN# KBRST# <45>
@
C DGPU _ PW ROK D40 AY11 C
<27,55,58> DGPU_PW ROK TACH0 / GPIO17 PROCPW RGD H_CPUPW RGD <6>
R238 1 2 10K _0402 _ 5% PCH_ BT_ DISABLE# T5 AY10 PCH_ THRMTRIP#_ R 1 2 H_ THRMTRIP#
+3VS SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# <6>
R239 390_0402_5%
<37> PCH_BT_DISABLE#
* PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable @
<41> ODD_EN
ODD _EN E8
GPIO24 INIT3_3V#
T14
PCH_THRMTRIP#_R <23,32>
0_ 0402_ 5% 2 1 R224 DS3_ W AKE#_ R E16 AY1 NV_ CLE
<16,37,38> PCIE_W AKE#
Low: VCCVRM VR Disable GPIO27 DF_TVS
R241 1 <BOM 2Structure>
10K_0402_5% PCH_GPIO28 P8
+3V_PCH GPIO28 AH8 INIT3_3V
<37,47> PCH_BT_ON# TS_VSS1 +3VS
1 2 10K _0402 _ 5% PCH_BT_ON# K1
+3VS STP_PCI# / GPIO34
R242
TS_VSS2
AK11 This signal has weak internal
+3VALW R243 1 2 10K _0402 _ 5% PCH_GPIO35 K4 S_DGPU_PWROK R255 1 2 10K _ 0402_ 5%
GPIO35 PU, can't pull low
AH10
ODD_DETECT# V8 TS_VSS3 KBRST# R226 1 2 10K _0402 _ 5%
<41> ODD_DETECT# SATA2GP / GPIO36 AK10
DS3@
R207 2 1 10K _0402 _5% PCH_ GPIO37 M5 TS_VSS4 PCH_ THRMTRIP#_ R R244 1 2 10K_ 0402_ 5%
SATA3GP / GPIO37
Intel schematic reviwe recommand.
PCH _GPIO38 N2 P37
R245 1 @ 2 10K_0402_5% DS3_W AKE#_R SLOAD / GPIO38 NC_1
R247 1 2 10K _0402 _ 5% PCH_ GPIO39 M3
+3VS SDATAOUT0 / GPIO39
R248 1 2 10K _0402 _ 5% PCH_ GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
R249 1 2 10K _0402 _ 5% PCH_ GPIO49 V3 BG48
+3VS SATA5GP / GPIO49 / TEMP_ALER T# VSS_NCTF_16
SLAVE _ PRESENT# D6 BH3
<32> SLAVE_PRESENT# GPIO57 VSS_NCTF_17
R250 1 2 200K _0402_ 5% ODD _ DETECT# BH47
+3VS VSS_NCTF_18
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
B R251 A44
VSS_NCTF_2 VSS_NCTF_20
BJ44 H : Sandy Bridge B

+3V_PCH
1 2 10K _0402 _ 5% SLAVE _ PRESENT# PROC_SEL
A45 BJ45 L : IVY Bridge
VSS_NCTF_3 VSS_NCTF_21
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22 +1.8VS
R259 1 2 10K _0402 _ 5% PCH_GPIO37 A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
A6 BJ6
VSS_NCTF_6 VSS_NCTF_24 R216
B3 C2 2.2K_0402_5%
VSS_NCTF_7 VSS_NCTF_25
B47 C48
VSS_NCTF_8 VSS_NCTF_26 NV _ CLE 1 2
H_SNB_IVB# <6>
BD1 D1 R217 1K_0402 _5%
VSS_NCTF_9 VSS_NCTF_27
BD49
VSS_NCTF_10 VSS_NCTF_28
D49 CLOSE TO THE BRANCHING POINT
BE1 E1
VSS_NCTF_11 VSS_NCTF_29
BE49 E49
VSS_NCTF_12 VSS_NCTF_30
BF1 F1
VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32

PANTHER-POINT_FCBGA989

A A

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (6/9) GPIO, CPU, MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 19 of 65
5 4 3 2 1
 5 4 3 2 1

U4G POWER L1 change to 1 ohm P/N

S RES 1/10W 1 +-1% 0603 +3VS PCH Power Rail Table
+1.05VS
1700mA L1
Refer to CPU EDS R1.5
+1.05VS AA23 U48 +VCCADAC 2 1
AC23 VCCCORE[1] 63mA VCCADAC
VCCCORE[2] 1 1 1 1_0603_1% S0 Iccmax
1 1 1 1 AD21 Voltage Rail Voltage Current (A)
AD23 VCCCORE[3] U47 C213 C214 C215
AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K 0.1U_0402_10V7K 10U_0603_6.3V6M
AF23 VCCCORE[5] 2 2 2
VCCCORE[6] V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 +3VS D
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36 +VCCA _ LVDS 2 R295 1
VCCCORE[9] 1mA VCCALVDS
V5REF 5 0.001
AG26
AG27 VCCCORE[10] AK37 R_short 0_0603_5%
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
AJ26 VCCCORE[13] AM37 L2
AJ27 VCCCORE[14] VCCTX_LVDS[1] 0.1UH_MLF1608DR10KT_10%_1608
VCCCORE[15] Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX _ LVDS 2 1
AJ31 VCCCORE[16] VCCTX_LVDS[2]
VCCCORE[17] 1 1 1 0.1uH inductor, 200mA
AP36 VccADAC 3.3 0.063
+1.05VS 40mA VCCTX_LVDS[3] C216 C217 C218
AP37 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_0805_6.3V6M
+1.05VS_VCCDPLLEXP AN19 VCCTX_LVDS[4] 2 2 2
R254 2 1 R _short 0_ 0603_ 5%
VCCIO[28] VccADPLLA 1.05 0.08

+VCCAPLLEXP BJ22 +3VS VccADPLLB 1.05 0.08

PAD T47 @ VCCAPLLEXP
V33 2 R256 1
This pin can be left as no connect in +3VS _VCC3 _3_ 6
AN16 VCC3_3[6]
1 VccCore 1.05 1.7
On-Die VR enabled mode (default). VCCIO[15] R_short 0_0603_5%
AN17 C219
VCCIO[16] V34 0.1U_0402_10V7K
VCC3_3[7] VccDMI 1.05 0.047
2
AN21
VCCIO[17]
VccIO 1.05 3.711
AN26
VCCIO[18]
3711mA
AN27 AT16 +VCCAFDI_VRM VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+1.05VS AP21 +VCCP_VCCDMI +1.05VS
C VCCIO[20] C
R258 VccSPI 3.3 0.01
+1.05VS AP23 AT20 +VCCP _ VCCDMI 2 1
VCCIO[21] VCCDMI[1]
1 R_short 0_0603_5%
Del R296 for 14' AP24 +1.05VS VccDSW 3.3 0.001
1 1 1 1 1 VCCIO[22]
layout C220
AP26 AB36 +1.05VS _VCC _ DMI_ CCI 2 R300 1 1U_0402_6.3V6K
VCCIO[23] 70mA VCCCLKDMI 2
1 R_short 0_0603_5% VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34 AG16 VccSus3_3 3.3 0.095
+3VS VCCIO[26] VCCDFTERM[1]

1 R260 2 +3VS _ VCCA3GBG BH29 AG17 +1.8VS

VCC3_3[3] 190mA VCCDFTERM[2]
VccSusHDA 3.3 / 1.5 0.01
R_short 0_0603_5% 1
C227
AJ16 2 R293 1
0.1U_0402_10V7K
VCCDFTERM[3]
+VCCPNAND VccVRM 1.8 / 1.5 0.167
2 1 R_short 0_0603_5%
+VCCAFDI _ VRM AP16
VCCVRM[2] AJ17
VCCDFTERM[4]
C228 VccCLKDMI 1.05 0.07
0.1U_0402_10V7K
+1.05VS_VCCAPLL_FDI BG6 2
+1.05VS PAD T48 @ VccAFDIPLL +3VS VccSSC 1.05 0.095
1 R263 2 +1.05VS _VCCDPLL _ FDI AP17
VCCIO[27] 2 R399 1
V1 +3V_VCCPSPI VccDIFFCLKN 1.05 0.055
R_short 0_0603_5% 10mA VCCSPI
1 R_short 0_0603_5%
AU20
+VCCP_VCCDMI VCCDMI[2] C230 VccALVDS 3.3 0.001
1U_0402_6.3V6K
B PANTHER-POINT_FCBGA989 2 B

VccTX_LVDS 1.8 0.04

+1.5VS +VCCAFDI_VRM

2 R265 1 +VCCAFDI _ VRM

R_short 0_0603_5%

Intel recommand VCCVRM==>1.5V FOR MOBILE

stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP

VCCVRM = 160mA detal waiting for newest spec

A A

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (7/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 20 of 65
5 4 3 2 1
 5 4 3 2 1

Have internal VRM

+3VS
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec

R280
POWER
2 1 +3VS _ VCC_ CLKF33
U4J +1.05VS
R_short 0_0603_5% 1 1
AD49 N26 +1.05VS _ VCCUSBCORE 2 R270 1
+3VALW VCCACLK VCCIO[29]
2 2 1 R_short 0_0603_5%
P26
2 R269 1 T16 VCCIO[30]
1 +VCCPDSW C233
D VCCDSW 3_3 1mA P28 1U_0402_6.3V6K D
R_short 0_0603_5% VCCIO[31] 2
C234
0.1U_0402_10V7K V12 T27
2 DCPSUSBYP VCCIO[32]
T29
+3VS _VCC_ CLKF33 T38 VCCIO[33] +3V_PCH
VCC3_3[5]
R272
On-Die PLL Voltage Regulator 228mA VCCSUS3_3[7]
T23 +3V _ VCCPUSB 2 1
H On-Die PLL voltage regulator enable +1.05VS BH23
VCCAPLLDMI2 R_short 0_0603_5%
T24 1
R271 VCCSUS3_3[8] +3V_PCH +5V_PCH +3V_PCH
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 2 1 +VCCDPLL _ CPY AL29
VCCIO[14] V23 2 R273 1
+3V _ VCCAUBG
,VCCAPLLSATA R_short 0_0603_5% VCCSUS3_3[9]
2 1 R_short 0_0603_5%
+VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] C238 D1
1
P24 0.1U_0402_10V7K R275 CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 +1.05VS 10_0402_5%
1U_0402_6.3V6K AA19
2 VCCASW [1] T26 2 R276 1
+1.05VS_VCCAUPLL +PCH_V5REF_SUS
+1.05VS AA21 VCCIO[34]
VCCASW [2] 903mA R_short 0_0603_5% 1
1 R277 2 +1.05VM _ VCCASW AA24 M26 +PCH _ V5REF_ SUS C240
VCCASW [3] 1mA V5REF_SUS 0.1U_0603_25V7K
R_short 0_0805_5% 1 1 2
AA26
VCCASW [4] AN23 +VCCA _ USBSUS C243 @1 2 1U _ 0402_ 6.3V6K
AA27 DCPSUS[4]
2 2 VCCASW [5] AN24 +3V _ VCCPSUS
AA29 VCCSUS3_3[1]
VCCASW [6]
+1.05VS AA31 +5VS +3VS
VCCASW [7]
AC26 P34 +PCH_V5REF_RUN +3V_PCH
C VCCASW [8] 1mA V5REF C
1 1 1 R278
L5 AC27 2 1 R279 D2
1 2 +1.05VS _VCCA _A_ DPL VCCASW [9] N20 +3V_ VCCPSUS CH751H-40PT_SOD323-2
VCCSUS3_3[2] 1 R_short 0_0603_5% 10_0402_5%
BLM18PG181SN1D_0603 AC29
2 2 2 VCCASW [10] N22 C247
AC31 VCCSUS3_3[3] 1U_0402_6.3V +PCH_V5REF_RUN
VCCASW [11] P20 2 +3VS
VCCSUS3_3[4] 1
L6 AD29
VCCASW [12] P22 2 R281 1
1 2 +1 . 05VS_VCCA_B_DPL C248
BLM18PG181SN1D_0603 AD31 VCCSUS3_3[5] 1U_0603_10V6K
VCCASW [13] 1 R_short 0_0603_5%
C249 2
W 21 AA16 +3VS _ VCCPCORE 0.1U_0402_10V7K
VCCASW [14] VCC3_3[1]
1
1 W 23 W 16 2 +3VS
VCCASW [15] VCC3_3[8]
1 1 R282
W 24 T34 +3VS _ VCCPPCI 2 1
2 VCCASW [16] VCC3_3[4]
2 1 R_short 0_0603_5%
W 26
2 2 VCCASW [17] C254
W 29 +3VS 0.1U_0402_10V7K
VCCASW [18] 2
W 31 AJ2 2 R283 1
+VCC3 _3_ 2
VCCASW [19] VCC3_3[2] +1.05VS_SATA3 +1.05VS
Before gerber out change to 22u_0805 W 33
1 R_short 0_0603_5%
VCCASW [20] AF13 2 R285 1
VCCIO[5] C255
2 0.1U_0402_10V7K 1 R_short 0_0603_5%
+VCCRTCEXT N16
DCPRTC AH13 C257
1 VCCIO[12]
C258 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
VCCVRM[4] VCCIO[13]
2
B AF14 B
2 R274 1 VCCIO[6]
+1.05VS _VCCA _ A_ DPL BD47
+1.05VS VCCADPLLA 80mA
R_short 0_0603_5% VCCAPLLSATA
AK1 On-Die PLL Voltage Regulator
1 +1.05VS _VCCA _ B_ DPL BF47 H On-Die PLL voltage regulator enable
C256 VCCADPLLB 80mA +VCCAFDI_VRM
1U_0402_6.3V6K
+1.05VS_VCCDIFFCLKN VCCVRM[1]
AF11 +VCCAFDI_VRM
+1.05VS_VCC_SATA +1.05VS
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
+VCCDIFFCLK AF17
2 AF33 VCCIO[7] ,VCCAPLLSATA
AF34 VCCDIFFCLKN[1] AC16 2 R288 1
R304 55mA
VCCDIFFCLKN[2] VCCIO[2]
+1.05VS_VCC_SATA
2 1 +1.05VS _ VCCDIFFCLKN AG34
+1.05VS VCCDIFFCLKN[3] R_short 0_0603_5%
1 AC17 1
R_short 0_0603_5% VCCIO[3] C261
C259 +1.05VS _ SSCVCC AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +1.05VS
DCPSST
R284 1
2 1 C263
+1.05VS
1 0.1U_0402_10V7K T17 T21
R_short 0_0603_5% V19 DCPSUS[1] VCCASW [22]
C262 2 DCPSUS[2]
1U_0402_6.3V6K +1.05VS V21
2 VCCASW [23]
2 R286 1 +V_CPU_IO BJ8
V_PROC_IO 1mA T19
R_short 0_0603_5% VCCASW [21]
1 1 1
+RTCVCC +3V_PCH

A22 P32 +VCCSUSHDA 2 R287 1

2 2 2 @
VCCRTC 10mA VCCSUSHDA
R_short 0_0603_5%
1 1 1 1
PANTHER-POINT_FCBGA989 C271
A 0.1U_0402_16V4Z A
@
2 2 2 2


LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (8/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 21 of 65
5 4 3 2 1
 5 4 3 2 1

U4H U4I
H5
VSS[0] AY4 H46
AA17 AK38 AY42 VSS[159] VSS[259] K18
AA2 VSS[1] VSS[80] AK4 AY46 VSS[160] VSS[260] K26
AA3 VSS[2] VSS[81] AK42 AY8 VSS[161] VSS[261] K39
AA33 VSS[3] VSS[82] AK46 B11 VSS[162] VSS[262] K46
D AA34 VSS[4] VSS[83] AK8 B15 VSS[163] VSS[263] K7 D
AB11 VSS[5] VSS[84] AL16 B19 VSS[164] VSS[264] L18
AB14 VSS[6] VSS[85] AL17 B23 VSS[165] VSS[265] L2
AB39 VSS[7] VSS[86] AL19 B27 VSS[166] VSS[266] L20
AB4 VSS[8] VSS[87] AL2 B31 VSS[167] VSS[267] L26
AB43 VSS[9] VSS[88] AL21 B35 VSS[168] VSS[268] L28
AB5 VSS[10] VSS[89] AL23 B39 VSS[169] VSS[269] L36
AB7 VSS[11] VSS[90] AL26 B7 VSS[170] VSS[270] L48
AC19 VSS[12] VSS[91] AL27 F45 VSS[171] VSS[271] M12
AC2 VSS[13] VSS[92] AL31 BB12 VSS[172] VSS[272] P16
AC21 VSS[14] VSS[93] AL33 BB16 VSS[173] VSS[273] M18
AC24 VSS[15] VSS[94] AL34 BB20 VSS[174] VSS[274] M22
AC33 VSS[16] VSS[95] AL48 BB22 VSS[175] VSS[275] M24
AC34 VSS[17] VSS[96] AM11 BB24 VSS[176] VSS[276] M30
AC48 VSS[18] VSS[97] AM14 BB28 VSS[177] VSS[277] M32
AD10 VSS[19] VSS[98] AM36 BB30 VSS[178] VSS[278] M34
AD11 VSS[20] VSS[99] AM39 BB38 VSS[179] VSS[279] M38
AD12 VSS[21] VSS[100] AM43 BB4 VSS[180] VSS[280] M4
AD13 VSS[22] VSS[101] AM45 BB46 VSS[181] VSS[281] M42
AD19 VSS[23] VSS[102] AM46 BC14 VSS[182] VSS[282] M46
AD24 VSS[24] VSS[103] AM7 BC18 VSS[183] VSS[283] M8
AD26 VSS[25] VSS[104] AN2 BC2 VSS[184] VSS[284] N18
AD27 VSS[26] VSS[105] AN29 BC22 VSS[185] VSS[285] P30
AD33 VSS[27] VSS[106] AN3 BC26 VSS[186] VSS[286] N47
AD34 VSS[28] VSS[107] AN31 BC32 VSS[187] VSS[287] P11
AD36 VSS[29] VSS[108] AP12 BC34 VSS[188] VSS[288] P18
AD37 VSS[30] VSS[109] AP19 BC36 VSS[189] VSS[289] T33
AD38 VSS[31] VSS[110] AP28 BC40 VSS[190] VSS[290] P40
AD39 VSS[32] VSS[111] AP30 BC42 VSS[191] VSS[291] P43
AD4 VSS[33] VSS[112] AP32 BC48 VSS[192] VSS[292] P47
AD40 VSS[34] VSS[113] AP38 BD46 VSS[193] VSS[293] P7
AD42 VSS[35] VSS[114] AP4 BD5 VSS[194] VSS[294] R2
C AD43 VSS[36] VSS[115] AP42 BE22 VSS[195] VSS[295] R48 C
AD45 VSS[37] VSS[116] AP46 BE26 VSS[196] VSS[296] T12
AD46 VSS[38] VSS[117] AP8 BE40 VSS[197] VSS[297] T31
AD8 VSS[39] VSS[118] AR2 BF10 VSS[198] VSS[298] T37
AE2 VSS[40] VSS[119] AR48 BF12 VSS[199] VSS[299] T4
AE3 VSS[41] VSS[120] AT11 BF16 VSS[200] VSS[300] W 34
AF10 VSS[42] VSS[121] AT13 BF20 VSS[201] VSS[301] T46
AF12 VSS[43] VSS[122] AT18 BF22 VSS[202] VSS[302] T47
AD14 VSS[44] VSS[123] AT22 BF24 VSS[203] VSS[303] T8
AD16 VSS[45] VSS[124] AT26 BF26 VSS[204] VSS[304] V11
AF16 VSS[46] VSS[125] AT28 BF28 VSS[205] VSS[305] V17
AF19 VSS[47] VSS[126] AT30 BD3 VSS[206] VSS[306] V26
AF24 VSS[48] VSS[127] AT32 BF30 VSS[207] VSS[307] V27
AF26 VSS[49] VSS[128] AT34 BF38 VSS[208] VSS[308] V29
AF27 VSS[50] VSS[129] AT39 BF40 VSS[209] VSS[309] V31
AF29 VSS[51] VSS[130] AT42 BF8 VSS[210] VSS[310] V36
AF31 VSS[52] VSS[131] AT46 BG17 VSS[211] VSS[311] V39
AF38 VSS[53] VSS[132] AT7 BG21 VSS[212] VSS[312] V43
AF4 VSS[54] VSS[133] AU24 BG33 VSS[213] VSS[313] V7
AF42 VSS[55] VSS[134] AU30 BG44 VSS[214] VSS[314] W 17
AF46 VSS[56] VSS[135] AV16 BG8 VSS[215] VSS[315] W 19
AF5 VSS[57] VSS[136] AV20 BH11 VSS[216] VSS[316] W2
AF7 VSS[58] VSS[137] AV24 BH15 VSS[217] VSS[317] W 27
AF8 VSS[59] VSS[138] AV30 BH17 VSS[218] VSS[318] W 48
AG19 VSS[60] VSS[139] AV38 BH19 VSS[219] VSS[319] Y12
AG2 VSS[61] VSS[140] AV4 H10 VSS[220] VSS[320] Y38
AG31 VSS[62] VSS[141] AV43 BH27 VSS[221] VSS[321] Y4
AG48 VSS[63] VSS[142] AV8 BH31 VSS[222] VSS[322] Y42
AH11 VSS[64] VSS[143] AW 14 BH33 VSS[223] VSS[323] Y46
AH3 VSS[65] VSS[144] AW 18 BH35 VSS[224] VSS[324] Y8
AH36 VSS[66] VSS[145] AW 2 BH39 VSS[225] VSS[325] BG29
AH39 VSS[67] VSS[146] AW 22 BH43 VSS[226] VSS[328] N24
B AH40 VSS[68] VSS[147] AW 26 BH7 VSS[227] VSS[329] AJ3 B
AH42 VSS[69] VSS[148] AW 28 D3 VSS[228] VSS[330] AD47
AH46 VSS[70] VSS[149] AW 32 D12 VSS[229] VSS[331] B43
AH7 VSS[71] VSS[150] AW 34 D16 VSS[230] VSS[333] BE10
AJ19 VSS[72] VSS[151] AW 36 D18 VSS[231] VSS[334] BG41
AJ21 VSS[73] VSS[152] AW 40 D22 VSS[232] VSS[335] G14
AJ24 VSS[74] VSS[153] AW 48 D24 VSS[233] VSS[337] H16
AJ33 VSS[75] VSS[154] AV11 D26 VSS[234] VSS[338] T36
AJ34 VSS[76] VSS[155] AY12 D30 VSS[235] VSS[340] BG22
AK12 VSS[77] VSS[156] AY22 D32 VSS[236] VSS[342] BG24
AK3 VSS[78] VSS[157] AY28 D34 VSS[237] VSS[343] C22
VSS[79] VSS[158] D38 VSS[238] VSS[344] AP13
PANTHER-POINT_FCBGA989 D42 VSS[239] VSS[345] M14
D8 VSS[240] VSS[346] AP3
E18 VSS[241] VSS[347] AP1
E26 VSS[242] VSS[348] BE16
G18 VSS[243] VSS[349] BC16
G20 VSS[244] VSS[350] BG28
G26 VSS[245] VSS[351] BJ28
G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A

PANTHER-POINT_FCBGA989


LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 PCH (9/9) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 22 of 65
5 4 3 2 1
 5 4 3 2 1

UV1A
PCIE _ CTX _ GRX _ N[0..15] +3VS_VGA
<32,5> PCIE_CTX_GRX_N[0..15] +3VS_VGA
PCIE_CTX_GRX_P7 AN12 Part 1 of 7 @
PCIE_ CTX_ GRX_ N7 AM12 PEX_RX0 P6 1
FB_ CLAMP_ MON 2
PCIE _CTX _ GRX _ P[0.. 15]
<32,5> PCIE_CTX_GRX_P[0..15] PEX_RX0_N GPIO0 FB_CLAMP <23,27,45>
PCIE _ CTX _ GRX _ P6 AN14 M3 RV138 0_0402_5%
PCIE _CRX _GTX _ N[0..15] PCIE _ CTX_ GRX_ N6 AM14 PEX_RX1 GPIO1 L6 VGA_BL_PW M PCH_ THRMTRIP#_ R
<32,5> PCIE_CRX_GTX_N[0..15] PEX_RX1_N GPIO2 VGA_BL_PW M <34> PCH_THRMTRIP#_R <19,32>
PCIE _ CTX _ GRX _ P5 AP14 P5 VGA_ENVDD
PCIE _CRX _GTX _ P[0..15] AP15 PEX_RX2 GPIO3 P7 VGA_ENVDD <34>
PCIE_CTX_GRX_N5 VGA_ENBKL RV208
<32,5> PCIE_CRX_GTX_P[0..15] AN15 PEX_RX2_N GPIO4 L7 VGA_ENBKL <34>
PCIE _ CTX _ GRX _ P4 10K_0402_5%
PCIE _ CTX _ GRX_ N4 AM15 PEX_RX3 GPIO5 M7 FB_ CLAMP_ TOGGLE_ REQ#
@ QV7B
PCIE _ CTX _ GRX _ P3 AN17 PEX_RX3_N GPIO6 N8
PEX_RX4 GPIO7 DMN66D0LDW-7 2N_SOT363-6
PCIE _ CTX _ GRX_ N3 AM17 M1 OVERT# 5
AP17 PEX_RX4_N GPIO8 M2 VGA_ALERT#
D
Under GPU(below 150mils) PCIE_CTX_GRX_P2
PCIE _ CTX _ GRX_ N2 AP18 PEX_RX5 GPIO9 L1 D
150mA PCIE _ CTX _ GRX _ P1 AN18 PEX_RX5_N GPIO10 M5 NVVDD PW M_ VID MEM_VREF <28,29,30,31>
LV1 BLM18PG181SN1D_2P QV7A
1 2 AM18 PEX_RX6 GPIO11 N3 NVVDD PW M_VID <58>
+SP_PLLVDD PCIE _ CTX_ GRX_ N1 VGA_AC_DET_R DMN66D0LDW-7 2 N _SOT363-6
+1.05VS_VGA PEX_RX6_N GPIO12 VGA_AC_DET_ R <3 2 >
PCIE _ CTX _ GRX _ P0 AN20 M4 DPRSLPVR_ VGA OVERT# 2
PEX_RX7 GPIO13 DPRSLPVR_VGA <58>
AM20 N4
180ohms (ESR=0.2) Bead 1 1 1 1 PCIE_CTX_GRX_N0
AP20 PEX_RX7_N GPIO14 P2
AP21 PEX_RX8 GPIO15 R8
AN21 PEX_RX8_N GPIO16 M6
2 2 2 2 AM21 PEX_RX9 GPIO17 R1 DGPU_HDMI_HPD
180ohms (ESR=0.2) Bead AN23 PEX_RX9_N GPIO18 P3
DGPU_HDMI_HPD <36>
AM23 PEX_RX10 GPIO19 P4
AP23 PEX_RX10_N GPIO20 P1 D
DV2
AP24 PEX_RX11 GPIO21 PLT _ RST_ VGA# 2
RB751V-40_SOD323-2
+3VS_VGA AN24 PEX_RX11_N VGA_AC_DET_R 2 1 G QV5
AM24 PEX_RX12 VGA_AC_DET <45>
S 2N7002KW _SOT323-3
+3VS_VGA AN26 PEX_RX12_N
AM26 PEX_RX13 Vendor recommand reserve PU/PD resistor 2012-0418 --> Stuff QV7, RV208
AP26 PEX_RX13_N 2012-0429 --> Add QV5, C38 has abnormal shutdown issue
RV24 RV25 AP27 PEX_RX14
2.2K_0402_5% 2.2K_040 2 _5% AN27 PEX_RX14_N AK9 VGA_CRT_R +3VS_VGA
AM27 PEX_RX15 DACA_RED AL10 VGA _CRT _G VGA_CRT_R <35>
PLT_RST_VGA#
PEX_RX15_N DACA_GREEN AL9 VGA _CRT _B VGA_CRT_G <35>
QV1B DACA_BLUE VGA_CRT_B <35> +3VALW
VGA _ SMB _ CK2 4 3 PCIE _ CRX _ GTX _ P7 1 2 0.22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ P7 AK14
EC_SMB_CK2 <15,32,40,45> CV24
PCIE_CRX_GTX_N7 1 2 0.22U _0402 _ 10V6K PCIE_CRX_C_GTX_N7 AJ14 PEX_TX0 AM9 VGA_CRT_HSYNC RV52
CV26
2N7002DW -T/R7_SOT363-6 PCIE_ CRX_ C_ GTX_ P6 AH14 PEX_TX0_N DACA_HSYNC AN9 VGA_ CRT_ VSYNC VGA_CRT_HS YNC <35> GC6@
PCIE _ CRX _ GTX _ P6 CV21 1 2 0 .22U _ 0402 _ 10V6K 10K_0402_5%
PCIE_ CRX_ C_ GTX_ N6 AG14 PEX_TX1 DACA_VSYNC VGA_CRT_VSYNC <35> RV53
PCIE _ CRX _ GTX _ N6 CV23 1 2 0.22U _ 0402 _ 10V6K
PCIE _ CRX _ GTX _ P5 1 2 0 .22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ P5 AK15 PEX_TX1_N 10K_0402_5%
CV25
PCIE _ CRX _ GTX _ N5 1 2 0.22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ N5 AJ15 PEX_TX2 AG10 +DACA_ VDD
CV27 QV6
PCIE_CRX_GTX_P4 1 2 0.22U _0402 _ 10V6K PCIE_CRX_C_GTX_P4 AL16 PEX_TX2_N DACA_VDD AP9 +DACA_VREF
CV29
PCIE _ CRX _ GTX _ N4 1 2 0 .22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ N4 AK16 PEX_TX3 DACA_VREF AP8 DACA_ RSET
CV31 FB_CLAMP_ TOGGLE_ REQ# 3 1
QV1A PCIE _ CRX _ GTX _ P3 1 2 0.22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ P3 AK17 PEX_TX3_N DACA_RSET GC6_EVENT# <19,32,45>
CV33
C VGA _ SMB _ DA2 1 6 PCIE _ CRX _ GTX _ N3 1 2 0 .22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ N3 AJ17 PEX_TX4 C
EC_SMB_DA2 <15,32,40,45> CV28 1
PCIE _ CRX _ GTX _ P2 1 2 0.22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ P2 AH17 PEX_TX4_N
CV30 RV107 2N7002KW _SOT323-3
2N7002DW -T/R7_SOT363-6 PCIE_CRX_GTX_N2 1 2 0.22U _0402 _ 10V6K PCIE_CRX_C_GTX_N2 AG17 PEX_TX5
CV32 124_0402_1%
PCIE _ CRX _ GTX _ P1 1 2 0 .22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ P1 AK18 PEX_TX5_N
CV36 SLI@
PCIE _ CRX _ GTX _ N1 1 2 0.22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ N1 AJ18 PEX_TX6 2 SLI@
CV41
PCIE _ CRX _ GTX _ P0 1 2 0 .22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ P0 AL19 PEX_TX6_N
CV34 +3VS_VGA
PU AT EC SIDE, +3VS AND 4.7K PCIE _ CRX _ GTX _ N0 CV35 1 2 0.22U _ 0402 _ 10V6K PCIE_ CRX_ C_ GTX_ N0 AK19 PEX_TX7 R4 VGA_ CRT_ CLK GPIO 14 of GPU connect to PCH GPIO 0
PEX_TX7_N I2CA_SCL VGA_CRT_CLK <35>
AK20 R5 VGA_CRT_DATA
AJ20
AH20
PEX_TX8
PEX_TX8_N
I2CA_SDA
R7
VGA_CRT_DATA <35>
CRT VGA _ ALERT# 1 2
I2CB _ SCL RV15 2.2K_0402_5%
AG20 PEX_TX9 I2CB_SCL R6 I2CB _ SDA VGA _ EDID_ CLK 1 2
AK21 PEX_TX9_N I2CB_SDA
RV4 2.2K_0402_5%
AJ21 PEX_TX10 R2 VGA_EDID_CLK VGA_EDID_DATA 1 2
AL22
AK22
PEX_TX10_N
PEX_TX11
I2CC_SCL
I2CC_SDA
R3 VGA _EDID _ DATA
VGA_EDID_CLK <34>
VGA_EDID_DATA <34> LVDS VGA _BL _ PW M 2
SLI@
1 RV7 2.2K_0402_5%
2
RV16 10K_0402_5% VGA _ CRT_ DATA 1
+3VS PEX_TX11_N
AK23 T4 VGA _ SMB _ CK2 RV10 2.2K_0402_5%
AJ23 PEX_TX12 I2CS_SCL T3 VGA _ SMB _ DA2 VGA _ CRT_ CLK 1 2
AH23 PEX_TX12_N I2CS_SDA
1 RV11 2.2K_0402_5%
AG23 PEX_TX13 I2CB _ SCL 1 2
C1061
AK24 PEX_TX13_N
0.1U_0402_16V4Z RV12 2.2K_0402_5%
AJ24 PEX_TX14 I2CB _ SDA 1 2
2 AL25 PEX_TX14_N
AK25 PEX_TX15 60mA +PLLVDD
Close to GPU OVERT#
RV131 2.2K_0402_5%
2
PEX_TX15_N RV1 10K_0402_5%
UV2 AD8 1 2 VGA _ CRT_ R 1 SLI@ 2 VGA _ AC_ DET_ R 1 2
PLT _ RST# 2 AJ11 PLLVDD RV2 10K_0402_5%
<18, 32,37,38,44,45,6> PLT_RST# B 45mA RV112 @ 0_0402_5% RV106 150_0402_1%
4 PLT_RST_VGA# PEX_W AKE_N AE8 VGA _ CRT_ G 1 SLI@ 2
DGPU_HOLD_RST# 1 Y SP_PLLVDD
<18> DGPU_HOLD_RST# CLK_PCIE_VGA AL13 150_0402_1%
A <15> CLK_PCIE_VGA
CLK_PCIE_VGA# AK13 PEX_REFCLK AD7
45mA +SP_PLLVDD VGA _ CRT_ B
RV108
1 SLI@ 2
<15> CLK_PCIE_VGA# PEX_REFCLK_N VID_PLLVDD
RV111 CLK_REQ_GPU# AK12 RV109 150_0402_1%
PEX_CLKREQ_N
NC7S Z 08P5X_NL_ S C70-5 10K_0402 _5%
B D ifferential signal 1
RV20
@ 2
200 _0402 _ 1%
PEX _ TSTCLK _ OUT
PEX_TSTCLK_OUT#
AJ26
AK26 PEX_TSTCLK_OUT XTAL_IN
H3
H2
XTAL _ IN
XTAL_OUT B
PEX_TSTCLK_OUT_N XTAL_OUT
PLT _ RST _ VGA# AJ12 J4 XTALOUT
AP29 PEX_RST_N XTAL_OUTBUFF H1 XTALSSIN 1 2
220 ohms @100MHz (ESR=0.05)
1 2 PEX_TERMP XTAL_SSIN 120mA
RV22 2.49K_0402_1%
PEX_ TERMP 10K_0402_5% RV26
RV27 +DACA_VDD Under GPU Near GPU 2
LV5 SLI@
1
0_0402_5% +3VS_VGA
R1495 @ 10K_0402_5% BLM18PG181SN1D_0603
1 2 1 1 1 1 1 1

N14P_FCBGA908 GT@ Internal Thermal Sensor

FB_ CLAMP_ MON 2 2 2 2 2 2
CV126

+3VS_VGA
+3VS RV238 1 2
0_0402_5% RV23 10M_0402_5%
GC6@
10K_0402_5%
RV230 YV1 OPT@
RV235 10K_0402_5% 4 3 XTAL_OUT
10K_0402_5% @ NC OSC
GC6@ RV231
XTAL _ IN 1 2 LV7
2 1 +3VS_VGA OSC NC +PLLVDD 1 2
<18,23,51> DGPU_PWR_EN +1.05VS_VGA
QV2 27MHZ 16PF +-30PPM X3G027000FG1H-HX
1 1 1 1 R_short 0_0402_5%
AO3413_SOT23-3 D RV236 10K_0402_5%
2 10K_0402_5% CV37 CV38
G GC6@ RV32 27P_0402_50V8J 27P_0402_50V8J
GC6@ S 10K_0402_5% 2 2 2 2

QV1 6
A 1 For GC6 1 3 A
D <15> CLK_REQ_GPU#_R
CLK_REQ_GPU#
20120816 --> CV37, CV38 change to 27pf
<18,23,51> DGPU_PWR_EN
2 Under GPU Near GPU
G 2 2N7002H 1N_SOT23-3
FB_CLAMP <23,27,45>
QV3 S @RV232
2N7002KW _SOT323-3 10K_0402_5%
GC6@ @
1 2 Title
RV237 RV233 0_0402_5%
Security Classification LC Future Center Secret Data
10K_0402_5%
@ Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-PCIE/DAC/GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 23 of 65
5 4 3 2 1
 5 4 3 2 1

UV1D

Part 4 of 7
<34> VGA_TXCLK+ VGA_TXCLK+ AM6
VGA_TXCLK- AN6 IFPA_TXC P8
<34> VGA_TXCLK- IFPA_TXC_N NC
<34> VGA_TXOUT0+ VGA_TXOUT0+ AP3 AC6
VGA_TXOUT0- AN3 IFPA_TXD0 NC AJ28
<34> VGA_TXOUT0- IFPA_TXD0_N NC
<34> VGA_TXOUT1+ VGA_TXOUT1+ AN5 AJ4
VGA_TXOUT1- AM5 IFPA_TXD1 NC AJ5
<34> VGA_TXOUT1- IFPA_TXD1_N NC
<34> VGA_TXOUT2+ VGA_TXOUT2+ AL6 AL11
VGA_TXOUT2- AK6 IFPA_TXD2 NC C15
<34> VGA_TXOUT2- IFPA_TXD2_N NC
AJ6 D19
AH6 IFPA_TXD3 NC D20
D IFPA_TXD3_N NC D23 D
NC D26
AJ9 NC H31
AH9 IFPB_TXC NC T8
AP6 IFPB_TXC_N NC V32
AP5 IFPB_TXD4 NC
AM7 IFPB_TXD4_N
IFPB_TXD5
for 15" dual channel AL7
AN8 IFPB_TXD5_N
AM8 IFPB_TXD6
AK8 IFPB_TXD6_N
AL8 IFPB_TXD7
IFPB_TXD7_N L4 VCCSENSE _VGA
VDD_SENSE VCCSENSE_VGA <58>
AK1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L5 VSSSENSE_ VGA
IFPC_L1 GND_SENSE VSSSENSE_VGA <58>
AJ2
IFPC_L1_N
AH3
IFPC_L2 trace width: 16mils
AH4
AG5 IFPC_L2_N differential voltage sensing.
AG4 IFPC_L3 differential signal routing.
IFPC_L3_N
TEST
AM1 AK11 TESTMODE
AM2 IFPD_L0 TESTMODE
AM3 IFPD_L0_N AM10
IFPD_L1 JTAG_TCK TV2
AM4 AM11
IFPD_L1_N JTAG_TDI TV3
AL3 AP12
IFPD_L2 JTAG_TDO TV4 10K_0402_5%
C AL4 AP11 C
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
AK5 IFPD_L3 JTAG_TRST_N
RV34 10K_0402_5%
IFPD_L3_N

<36> VGA_HDMI_TX2+ VGA _ HDMI _ TX2+ AD2

VGA _ HDMI _ TX2- AD3 IFPE_L0
<36> VGA_HDMI_TX2- IFPE_L0_N
VGA _ HDMI _ TX1+ AD1
<36> VGA_HDMI_TX1+
VGA _ HDMI _ TX1- AC1 IFPE_L1 SERIAL
<36> VGA_HDMI_TX1- IFPE_L1_N
<36> VGA_HDMI_TX0+ VGA_HDMI_TX0+ AC2 H6 ROM_CS#
VGA _ HDMI _ TX0- AC3 IFPE_L2 ROM_CS_N H4 ROM_ SCLK
<36> VGA_HDMI_TX0- IFPE_L2_N ROM_SCLK ROM_SCLK <33>
<36> VGA_HDMI_CLK+ VGA _ HDMI _ CLK+ AC4 H5 ROM _ SI
IFPE_L3 ROM_SI ROM_SI <33>
<36> VGA_HDMI_CLK- VGA _ HDMI _ CLK- AC5 H7 ROM _ SO
IFPE_L3_N ROM_SO ROM_SO <33>

AE3
AE4 IFPF_L0
AF4 IFPF_L0_N
AF5 IFPF_L1
AD4 IFPF_L1_N GENERAL RV35 10K_0402_5%
AD5 IFPF_L2 L2 2 1
AG1 IFPF_L2_N BUFRST_N
AF1 IFPF_L3 L3
IFPF_L3_N CEC
J1 1 2
M ULTI_STRAP_REF0_GND RV38 40.2K_0402_1%
AG3
AG2 IFPC_AUX_I2CW _SCL
IFPC_AUX_I2CW _SDA_ N J2 STRAP0
STRAP0 STRAP0 <33>
J7 STRAP1
B STRAP1 STRAP1 <33> B
AK3 J6 STRAP2
+3VS_VGA IFPD_AUX_I2CX_SCL STRAP2 STRAP2 <33>
AK2 J5 STRAP3
IFPD_AUX_I2CX_SDA_N STRAP3 STRAP3 <33>
J3 STRAP4
STRAP4 STRAP4 <33>
SLI@
1
RV113
2 VGA _ HDMI _ CLK
4.7K_0402_5%
HDMI <36> VGA_HDMI_CLK
VGA _ HDMI_ CLK
VGA _ HDMI _ DATA
AB3
AB4 IFPE_AUX_I2CY_SCL
<36> VGA_HDMI_DATA IFPE_AUX_I2CY_SDA_N K3
SLI@ THERMDP
1 2 VGA _ HDMI _ DATA K4
RV114 4.7K_0402_5% AF3 THERMDN
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

1MB SPI ROM FOR VBIOS ROM (SLI)

N14P_FCBGA908
+3VS_VGA
CV295
2 1 20mils
@
0.1U_0402_16V4Z @ @

RV229 RV225
10K_0402_5% 10K_0402_5%
@ @
RV224 0_0402_5% UV15
ROM_CS#1 2 ROM_CS#_R 1 8
2 2 CS# VCC 7 ROM_ HOLD#
ROM _ SO 1 ROM _SO _ R
RV226 0_0402_5% 3 DO HOLD# 6 @
A W P# CLK A
@ 4 5 RV228 0_0402_5%
GND DIO
ROM_SCLK_R1 2 ROM_SCLK
MX25L1005AMC-12G SOP ROM _SI _ R 1 2 ROM _ SI
RV227 0_0402_5%
@
Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-LVDS/HDMI/DP/THM

 
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C ustom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 24 of 65
5 4 3 2 1
 5 4 3 2 1

UV1E
Near GPU
+1.5VS_VGA 2000mA +1.05VS_VGA
For GDDR5 setting. Near GPU 3.5A Part 5 of 7

AA27 AG19
AA30 FBVDDQ_0 PEX_IOVDD_0 AG21
AB27 FBVDDQ_1 PEX_IOVDD_1 AG22
1 1 1 1 1 1 2 2 2 2 1 1 1 1 FBVDDQ_2 PEX_IOVDD_2 1 1 1 1 1 1 2 2 2 2
AB33 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25
2 2 2 2 2 2 1 1 1 1 2 2 2 2 AE27 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
FBVDDQ_8 PEX_IOVDDQ_0
B13
B16 FBVDDQ_9 PEX_IOVDDQ_1
AG15
AG16
Under GPU(below 150mils) +1.05VS_VGA
D D
FBVDDQ_10 PEX_IOVDDQ_2
+1.5VS_VGA
Under GPU(below 150mils) B19
E13 FBVDDQ_11 PEX_IOVDDQ_3
AG18
AG25
FBVDDQ_12 PEX_IOVDDQ_4 1 1 1 1
E16 AH15
E19 FBVDDQ_13 PEX_IOVDDQ_5 AH18
H10 FBVDDQ_14 PEX_IOVDDQ_6 AH26
1 1 1 1 1 1 1 1 1 1 1 1 FBVDDQ_15 PEX_IOVDDQ_7
H11 AH27 2 2 2 2
H12 FBVDDQ_16 PEX_IOVDDQ_8 AJ27
H13 FBVDDQ_17 PEX_IOVDDQ_9 AK27
2 2 2 2 2 2 2 2 2 2 2 2 H14 FBVDDQ_18 PEX_IOVDDQ_10 AL27
H15 FBVDDQ_19 PEX_IOVDDQ_11 AM28
H16 FBVDDQ_20 PEX_IOVDDQ_12 AN28 +3VS_VGA
H18 FBVDDQ_21 PEX_IOVDDQ_13
H19 FBVDDQ_22
H20 FBVDDQ_23
H21 FBVDDQ_24 AH12
H22 FBVDDQ_25 PEX_PLL_HVDD
H23 FBVDDQ_26
FBVDDQ_27 1 1 1
H24
H8 FBVDDQ_28 AG12
H9 FBVDDQ_29 PEX_SVDD_3V3
L27 FBVDDQ_30 2 2 2
M27 FBVDDQ_31
FBVDDQ_32
N27
P27 FBVDDQ_33 PEX_PLLVDD
AG26 +PEX _PLLVDD Under GPU(below 150mils)
R27 FBVDDQ_34
T27 FBVDDQ_35
T30 FBVDDQ_36 J8
FBVDDQ_37 VDD33_0 S3 off --> +3VS, +3VS_VGA, +VDD33MISC +3VS_VGA
T33
V27 FBVDDQ_38 VDD33_1
K8
L8
Place near GPU
FBVDDQ_39 VDD33_2 RV5
W27 M8 +VDD33 2 1
W30 FBVDDQ_40 VDD33_3
FBVDDQ_41 R_short 0_0603_5%
W33 1 1 1 1
Y27 FBVDDQ_42
FBVDDQ_43 NV Check
AH8 +IFPAB _PLLVDD
C IFPAB_PLLVDD C
AJ8 2 1
RV141 IFPAB_RSET 2 2 2 2
1 2 FB _ VDDQ_ SENSE 1K_0402_1% RV40
<55> VDDQ_SENSE
AG8 +IFPAB _ IOVDD
R_short 0_0402_5% IFPA_IOVDD @
AG9
RV142 IFPB_IOVDD
1 2 FB _ VSS _ SENSE F1
FB_VDDQ_SENSE Place near balls
R_short 0_0402_5% @
AF7 +IFPC _PLLVDD 1 2
+1.5VS_VGA F2 IFPC_PLLVDD AF8 10K _ 0402 _ 5% RV42 2 1
FB_GND_SENSE IFPC_RSET 1K_0402_1% RV43
AF6 +IFPC _IOVDD 1 @ 2 @
1 2 J27 IFPC_IOVDD 10K_0402_5% RV44
FB_CAL_PD_VDDQ
CALIBRATION PIN GDDR5 RV6 40.2_ 0402_1% IFPAB & IFPEF have to use
AG7 +IFPD_ PLLVDD 1 2
1 2 H27 IFPD_PLLVDD AN2 10K _0402 _ 5% RV45 2 1
FB_CAL_PU_GND IFPD_RSET
FB_CAL_x_PD_VDDQ 40.2Ohm RV8 40.2_ 0402_1%
AG6 +IFPD_ IOVDD 1
@
1K_0402_1%
2 @
RV46

1 2 H25 IFPD_IOVDD 10K_0402_5% RV47

FB_CAL_TERM_GND
FB_CAL_x_PU_GND 40.2Ohm RV9 60.4_ 0402_1%
AB8 +IFPEF _PLLVDD
@
IFPEF_PLVDD AD6 2 1
IFPEF_RSET
FB_CAL_xTERM_GND 60.4Ohm AC7 +IFPE _IOVDD
1K_0402_1% RV50

IFPE_IOVDD
Place near balls IFPF_IOVDD
AC8

+1.05VS_VGA
120mA LV2
+PEX _PLLVDD 2 1
N14P_FCBGA908
R_short 0_0603_5%
1 1 1

2 2 2
B 300ohms @100MHz (ESR=0.25) B

P/N: SM010031680 120ohms @100MHz (ESR=0.18)

+3VS_VGA
220mA +1.05VS_VGA P/N:SM01000BZ00
2
LV9
1 +IFPEF_PLLVDD LV6 200 mA Place near balls
BLM18PG181SN1D_0603 2 1 +IFPAB_PLLVDD
SLI@ 1 1 1 1 1 BLM18PG181SN1D_060 3
SLI@
1 1 1
CV140
CV147 2 2 2 2 2

2 2 2
SLI@ SLI@ SLI@ SLI@
SLI@
SLI@ SLI@
Place near balls 10K_0402_5% SLI@
10K_0402_5% OPT@
OPT@
Place near balls
180ohms @100MHz (ESR=0.2)
P/N: SM010030710
+1.05VS_VGA 220ohms @100MHz (ESR=0.05) +3VS_VGA
LV10 570mA LV4
2 1 +IFPE_IOVDD 2 1 +IFPAB_IOVDD
BLM18PG181SN1D_0603 1 1 1 1 BLM18PG181SN1D_0603 IFPA_IOVDD and
SLI@ SLI@ 1 1 1 1
IFPB_IOVDD combined
2 2 2 2
CV172 CV176 2 2 2 2

SLI@ SLI@ SLI@ SLI@

SLI@ SLI@ SLI@
SLI@
A A
Place near balls
10K_0402_5% 10K_0402_5%
OPT@ OPT@
Place near balls

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-POWER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400-LA8691P
Date: Monday, January 14, 2013 Sheet 25 of 65
5 4 3 2 1
 5 4 3 2 1

UV1F

Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
UV1G +VGA_CORE AA20 GND_2 GND_102 E10
+VGA_CORE AA22 GND_3 GND_103 E22
AB12 GND_4 GND_104 E25
Part 7 of 7 V17 AB14 GND_5 GND_105 E5
AA12 VDD_56 V18 AB16 GND_6 GND_106 E7
AA14 VDD_0 VDD_57 V20 AB19 GND_7 GND_107 F28
D VDD_1 VDD_58 GND_8 GND_108 D
AA16 V22 AB2 F7
AA19 VDD_2 VDD_59 W 12 AB21 GND_9 GND_109 G10
AA21 VDD_3 VDD_60 W 14 A33 GND_10 GND_110 G13
AA23 VDD_4 VDD_61 W 16 AB23 GND_11 GND_111 G16
AB13 VDD_5 VDD_62 W 19 AB28 GND_12 GND_112 G19
AB15 VDD_6 VDD_63 W 21 AB30 GND_13 GND_113 G2
AB17 VDD_7 VDD_64 W 23 AB32 GND_14 GND_114 G22
AB18 VDD_8 VDD_65 Y13 AB5 GND_15 GND_115 G25
AB20 VDD_9 VDD_66 Y15 AB7 GND_16 GND_116 G28
AB22 VDD_10 VDD_67 Y17 AC13 GND_17 GND_117 G3
AC12 VDD_11 VDD_68 Y18 AC15 GND_18 GND_118 G30
AC14 VDD_12 VDD_69 Y20 AC17 GND_19 GND_119 G32
AC16 VDD_13 VDD_70 Y22 AC18 GND_20 GND_120 G33
AC19 VDD_14 VDD_71 AA13 GND_21 GND_121 G5
AC21 VDD_15 AC20 GND_22 GND_122 G7
AC23 VDD_16 U1 AC22 GND_23 GND_123 K2
M12 VDD_17 XVDD_1 U2 AE2 GND_24 GND_124 K28
M14 VDD_18 XVDD_2 U3 AE28 GND_25 GND_125 K30
M16 VDD_19 XVDD_3 U4 AE30 GND_26 GND_126 K32
M19 VDD_20 XVDD_4 U5 AE32 GND_27 GND_127 K33
M21 VDD_21 XVDD_5 U6 AE33 GND_28 GND_128 K5
M23 VDD_22 XVDD_6 U7 AE5 GND_29 GND_129 K7
N13 VDD_23 XVDD_7 U8 AE7 GND_30 GND_130 M13
N15 VDD_24 XVDD_8 AH10 GND_31 GND_131 M15
N17 VDD_25 AA15 GND_32 GND_132 M17
N18 VDD_26 V1 AH13 GND_33 GND_133 M18
N20 VDD_27 XVDD_9 V2 AH16 GND_34 GND_134 M20
N22 VDD_28 XVDD_10 V3 AH19 GND_35 GND_135 M22
P12 VDD_29 XVDD_11 V4 AH2 GND_36 GND_136 N12
P14 VDD_30 XVDD_12 V5 AH22 GND_37 GND_137 N14
C C
P16 VDD_31 XVDD_13 V6 AH24 GND_38 GND_138 N16
P19 VDD_32 XVDD_14 V7 AH28 GND_39 GND_139 N19
P21 VDD_33 XVDD_15 V8 AH29 GND_40 GND_140 N2
P23 VDD_34 XVDD_16 AH30 GND_41 GND_141 N21
R13 VDD_35 AH32 GND_42 GND_142 N23
R15 VDD_36 W2 AH33 GND_43 GND_143 N28
R17 VDD_37 XVDD_17 W3 AH5 GND_44 GND_144 N30
R18 VDD_38 XVDD_18 W4 AH7 GND_45 GND_145 N32
R20 VDD_39 XVDD_19 W5 AJ7 GND_46 GND_146 N33
R22 VDD_40 XVDD_20 W7 AK10 GND_47 GND_147 N5
T12 VDD_41 XVDD_21 W8 AK7 GND_48 GND_148 N7
T14 VDD_42 XVDD_22 AL12 GND_49 GND_149 P13
T16 VDD_43 AL14 GND_50 GND_150 P15
T19 VDD_44 Y1 AL15 GND_51 GND_151 P17
T21 VDD_45 XVDD_23 Y2 AL17 GND_52 GND_152 P18
T23 VDD_46 XVDD_24 Y3 AL18 GND_53 GND_153 P20
U13 VDD_47 XVDD_25 Y4 AL2 GND_54 GND_154 P22
U15 VDD_48 XVDD_26 Y5 AL20 GND_55 GND_155 R12
U17 VDD_49 XVDD_27 Y6 AL21 GND_56 GND_156 R14
U18 VDD_50 XVDD_28 Y7 AL23 GND_57 GND_157 R16
U20 VDD_51 XVDD_29 Y8 AL24 GND_58 GND_158 R19
U22 VDD_52 XVDD_30 AL26 GND_59 GND_159 R21
V13 VDD_53 AL28 GND_60 GND_160 R23
V15 VDD_54 AA1 AL30 GND_61 GND_161 T13
VDD_55 XVDD_31 AA2 AL32 GND_62 GND_162 T15
XVDD_32 AA3 AL33 GND_63 GND_163 T17
XVDD_33 AA4 AL5 GND_64 GND_164 T18
XVDD_34 AA5 AM13 GND_65 GND_165 T2
XVDD_35 AA6 AM16 GND_66 GND_166 T20
B XVDD_36 GND_67 GND_167 B
AA7 AM19 T22
XVDD_37 AA8 AM22 GND_68 GND_168 AG11
XVDD_38 AM25 GND_69 GND_169 T28
AN1 GND_70 GND_170 T32
AN10 GND_71 GND_171 T5
AN13 GND_72 GND_172 T7
N14P_FCBGA908 AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W 13
B25 GND_86 GND_186 W 15
B28 GND_87 GND_187 W 17
B31 GND_88 GND_188 W 18
B34 GND_89 GND_189 W 20
B4 GND_90 GND_190 W 22
B7 GND_91 GND_191 W 28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
A A
C28 GND_97 GND_197 Y23
C7 GND_98 GND_198 AH11
GND_99 GND_199 C16
GND_OPT W 32
GND_OPT

Security Classification LC Future Center Secret Data Title

N14P_FCBGA908
Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 26 of 65
 5 4 3 2 1

FBC _ D[0..63]
FBA_D[0..63] <30,31> FBC_D[0..63]
<28,29> FBA_D[0..63]

30ohms (ESR=0.01) Bead UV1B PU for X16 mode PU for X16 mode
P/N;SM010007W00 UV1C
Part 2 of 7
+1.05VS_VGA +FB_PLLAVDD FBA_D0 L28 U30 FBA _ CS# _ L Part 3 of 7
M29 FBA_D0 FBA_CMD0 T31 FBA_CS#_L <28> G9 D13
200mA FBA_D1 FBA _ MA3 _ BA3_ L FBC_ D0 FBC_ CS#_ L
FBA_D1 FBA_CMD1 FBA_MA3_BA3_L <28 > FBB_D0 FBB_CMD0 FBC_CS#_L <30>
FBMA-L11-160808300LMA25T_2P
1 2 +FB_PLLAVDD
FBA_D2
FBA_D3
L29
M28 FBA_D2
FBA_D3
FBA_CMD2
FBA_CMD3
U29
R34
FBA _ MA2 _ BA0_ L
FBA_MA4_BA2_L
FBA_MA2_BA0_L <28 >
FBA_MA4_BA2_L <28 >
FBC_ D1
FBC_D2
E9
G8 FBB_D1
FBB_D2
FBB_CMD1
FBB_CMD2
E14
F14
FBC_ MA3_ BA3_ L
FBC_MA2_BA0_L
FBC_MA3_BA3_L <30>
FBC_MA2_BA0_L <30>
GDDR5
Mode H - Mirror Mode Mapping
D FBA_D4 N31 R33 FBA _ MA5 _ BA1_ L FBC_ D3 F9 A12 FBC_ MA4_ BA2_ L D
P29 FBA_D4 FBA_CMD4 U32 FBA_MA5_BA1_L <28 >+1.5VS_VGA F11 FBB_D3 FBB_CMD3 B12 FBC_MA4_BA2_L <30>
LV3 FBA_D5 FBA _ W E# _ L FBC _ D4 FBC_ MA5_ BA1_ L
FBA_D5 FBA_CMD5 FBA_WE#_L <28> FBB_D4 FBB_CMD4 FBC_MA5_BA1_L <30>+1 .5VS_VGA
Place close to BGA FBA_D6 R29
FBA_D6 FBA_CMD6
U33 FBA _ MA7 _ MA8_ L
FBA_MA7_MA8_L <28 >
FBC_ D5 G11
FBB_D5 FBB_CMD5
C14 FBC_ W E#_ L
FBC_WE#_L <30>
FBA_D7 P28 U28 FBA _ MA6 _ MA11_ L FBC_ D6 F12 B14 FBC_ MA7_ MA8_ L
FBA_D7 FBA_CMD7 FBA_MA6_MA11_L <2 8> FBB_D6 FBB_CMD6 FBC_MA7_MA8_L <30>
FBA_D8 J28
H29 FBA_D8 FBA_CMD8
V28
V29
FBA_ABI#_L
FBA_ABI#_L <28>
FBC_D7 G12
G6 FBB_D7 FBB_CMD7
G15
F15
FBC_MA6_MA11_L
FBC_MA6_MA11_L <30 > DATA Bus
FBA_D9 FBA _ MA12 _ RFU_ L RV209 FBC_ D8 FBC_ ABI#_ L
FBA_D9 FBA_CMD9 FBA_MA12_RFU_L < 2 8> FBB_D8 FBB_CMD8 FBC_ABI#_L <30>
FBA_D10 J29
FBA_D10 FBA_CMD10
V30 FBA _ MA0 _ MA10_ L
FBA_MA0_MA10_L <2 8> 10K_ 0 402_5% FBC_ D9 F5
FBB_D9 FBB_CMD9
E15 FBC_ MA12_ RFU_ L
FBC_MA12_RFU_L <30 >
RV210 Address 0..31 32..63
FBA_D11 H28 U34 FBA _ MA1 _ MA9_ L FBC_ D10 E6 D15 FBC_ MA0_ MA10_ L 10K_04 0 2_5%
FBA_D11 FBA_CMD11 FBA_MA1_MA9_L <28 > FBB_D10 FBB_CMD10 FBC_MA0_MA10_L <30 >
FBA_D12 G29
E31 FBA_D12 FBA_CMD12
U31
V34
FBA _ RAS# _ L
FBA_RAS#_L <28>
FBC_ D11 F6
F4 FBB_D11 FBB_CMD11
A14
D14
FBC_ MA1_ MA9_ L
FBC_MA1_MA9_L <30> FBx_CMD0 CS#
FBA_D13 FBA_RST#_L FBC_D12 FBC_RAS#_L
FBA_D13 FBA_CMD13 FBA_RST#_L <28> FBB_D12 FBB_CMD12 FBC_RAS#_L <30>
FBA_D14 E32
F30 FBA_D14 FBA_CMD14
V33
Y32
FBA _ CKE _ L
FBA_CKE_L <28>
FBC_ D13 G4
E2 FBB_D13 FBB_CMD13
A15
B15
FBC_ RST#_ L
FBC_RST#_L <30> FBx_CMD1 A3_BA3
FBA_D15 FBA _ CAS# _ L FBC_ D14 FBC_ CKE_ L
FBA_D15 FBA_CMD15 FBA_CAS#_L <28> FBB_D14 FBB_CMD14 FBC_CKE_L <30>
FBA_D16 C34
D32 FBA_D16 FBA_CMD16
AA31
AA29
FBA _ CS# _ H
FBA_CS#_H <29>
FBC_ D15 F3
C2 FBB_D15 FBB_CMD15
C17
D18
FBC _ CAS#_ L
FBC_CAS#_L <30> FBx_CMD2 A2_BA0
FBA_D17 FBA _ MA3 _ BA3_ H FBC_ D16 FBC_ CS#_ H
FBA_D17 FBA_CMD17 FBA_MA3_BA3_H <2 9 > FBB_D16 FBB_CMD16 FBC_CS#_H <31>
FBA_D18 B33
C33 FBA_D18 FBA_CMD18
AA28
AC34
FBA_MA2_BA0_H
FBA_MA2_BA0_H <2 9 >
FBC_D17 D4
D3 FBB_D17 FBB_CMD17
E18
F18
FBC_MA3_BA3_H
FBC_MA3_BA3_H <31> FBx_CMD3 A4_BA2
FBA_D19 FBA _ MA4 _ BA2_ H FBC_ D18 FBC_ MA2_ BA0_ H
FBA_D19 FBA_CMD19 FBA_MA4_BA2_H <2 9 > FBB_D18 FBB_CMD18 FBC_MA2_BA0_H <31>
FBA_D20 F33
FBA_D20 FBA_CMD20
AC33 FBA _ MA5 _ BA1_ H
FBA_MA5_BA1_H <2 9 >
+1.5VS_VGA
FBC_ D19 C1
FBB_D19 FBB_CMD19
A20 FBC_ MA4_ BA2_ H
FBC_MA4_BA2_H <31> FBx_CMD4 A5_BA1
FBA_D21 F32 AA32 FBA _ W E#_ H FBC_ D20 B3 B20 FBC_ MA5_ BA1_ H
FBA_D21 FBA_CMD21 FBA_WE#_H <29> FBB_D20 FBB_CMD20 FBC_MA5_BA1_H <31>
FBA_D22 H33
H32 FBA_D22 FBA_CMD22
AA33
Y28
FBA _ MA7 _ MA8_ H
FBA_MA7_MA8_H <2 9 >
FBC_ D21 C4
B5 FBB_D21 FBB_CMD21
C18
B18
FBC_ W E#_ H
FBC_WE#_H <31>
+1 .5VS_VGA
FBx_CMD5 WE#
FBA_D23 FBA_MA6_MA11_H FBC_D22 FBC_MA7_MA8_H
FBA_D23 FBA_CMD23 FBA_MA6_MA11_H < 2 9> FBB_D22 FBB_CMD22 FBC_MA7_MA8_H <31>
FBA_D24 P34
P32 FBA_D24 FBA_CMD24
Y29
W 31
FBA _ ABI# _ H
FBA_ABI#_H <29>
FBC_ D23 C5
A11 FBB_D23 FBB_CMD23
G18
G17
FBC_ MA6_ MA11_ H
FBC_MA6_MA11_H <31 > FBx_CMD6 A7_A8
FBA_D25 FBA _ MA12 _ RFU_ H RV221 FBC_ D24 FBC_ ABI#_ H
FBA_D25 FBA_CMD25 FBA_MA12_RFU_H < 29> FBB_D24 FBB_CMD24 FBC_ABI#_H <31>
FBA_D26 P31
P33 FBA_D26 FBA_CMD26
Y30
AA34
FBA _ MA0 _ MA10_ H
FBA_MA0_MA10_H < 2 9> 10K_ 0 402_5% FBC_ D25 C11
D11 FBB_D25 FBB_CMD25
F17
D16
FBC_ MA12_ RFU_ H
FBC_MA12_RFU_H <31 >
RV222 FBx_CMD7 A6_A11
FBA_D27 FBA _ MA1 _ MA9_ H FBC_ D26 FBC_ MA0_ MA10_ H 10K_04 0 2_5%
FBA_D27 FBA_CMD27 FBA_MA1_MA9_H <2 9 > FBB_D26 FBB_CMD26 FBC_MA0_MA10_H <31 >
FBA_D28 L31
L34 FBA_D28 FBA_CMD28
Y31
Y34
FBA_RAS#_H
FBA_RAS#_H <29>
FBC_D27 B11
D8 FBB_D27 FBB_CMD27
A18
D17
FBC_MA1_MA9_H
FBC_MA1_MA9_H <31> FBx_CMD8 ABI#
FBA_D29 FBA _ RST# _ H FBC_ D28 FBC_ RAS#_ H
FBA_D29 FBA_CMD29 FBA_RST#_H <29> FBB_D28 FBB_CMD28 FBC_RAS#_H <31>
FBA_D30 L32
FBA_D30 FBA_CMD30
Y33 FBA _ CKE _ H
FBA_CKE_H <29>
FBC_D29 A8
FBB_D29 FBB_CMD29
A17 FBC _ RST#_ H
FBC_RST#_H <31> FBx_CMD9 A12_RFU
FBA_D31 L33 V31 FBA _ CAS# _ H FBC_D30 C8 B17 FBC _ CKE_ H
FBA_D31 FBA_CMD31 FBA_CAS#_H <29> FBB_D30 FBB_CMD30 FBC_CKE_H <31>
FBA_D32
FBA_D33
AG28
AF29 FBA_D32
FBC_ D31 B8
F24 FBB_D31 FBB_CMD31
E17 FBC _ CAS#_ H
FBC_CAS#_H <31> FBx_CMD10 A0_A10
FBC_D32
FBA_D33 FBB_D32
FBA_D34
FBA_D35
AG29
AF28 FBA_D34 R32
FBC_ D33 G23
E24 FBB_D33 FBx_CMD11 A1_A9
FBC_ D34
FBA_D35 FBA_CMD_RFU0 FBB_D34
C FBA_D36
FBA_D37
AD30
AD29 FBA_D36 FBA_CMD_RFU1
AC32 FBC_ D35 G24
D21 FBB_D35 FBB_CMD_RFU0
C12
C20
FBx_CMD12 RAS# C
FBC_ D36
FBA_D37 FBB_D36 FBB_CMD_RFU1
FBA_D38
FBA_D39
AC29
AD28 FBA_D38
FBC_D37
FBC_ D38
E21
G21 FBB_D37 FBx_CMD13 RST#
@
FBA_D39 R28 60.4_0402_ 1%
1 FBB_D38
FBA_D40 AJ29
FBA_D40 FBA_DEBUG0
2RV58
+1.5VS_VGA
FBC_ D39 F21
FBB_D39 1
@ FBx_CMD14 CKE#
FBA_D41 AK29 AC28 60.4_0402_ 1% 2RV59 FBC_ D40 G27 G14 60.4_0402_ 1% 2RV60
FBA_D41 FBA_DEBUG1 FBB_D40 FBB_DEBUG0 1 +1.5VS_VGA
FBA_D42
FBA_D43
AJ30
AK28 FBA_D42
FBC_ D41
FBC_D42
D27
G26 FBB_D41 FBB_DEBUG1
G20 60.4_0402_ % 2RV61 FBx_CMD15 CAS#
FBA_D43 @ FBB_D42
FBA_D44 AM29
FBA_D44
FBC_ D43 E27
FBB_D43 @ FBx_CMD16 CS#
FBA_D45 AM31 R30 FBA_CLK0 FBC_ D44 E29
FBA_D45 FBA_CLK0 FBA_CLK0 <28> FBB_D44
FBA_D46 AN29
FBA_D46 FBA_CLK0_N
R31 FBA_CLK0#
FBA_CLK0# <28>
FBC_ D45 F29
FBB_D45 FBB_CLK0
D12 FBC_ CLK0
FBC_CLK0 <30> FBx_CMD17 A3_BA3
FBA_D47 AM30 AB31 FBA_CLK1 FBC_ D46 E30 E12 FBC_ CLK0#
FBA_D47 FBA_CLK1 FBA_CLK1 <29> FBB_D46 FBB_CLK0_N FBC_CLK0# <30>
FBA_D48 AN31
FBA_D48 FBA_CLK1_N
AC31 FBA_CLK1#
FBA_CLK1# <29>
FBC_D47 D30
FBB_D47 FBB_CLK1
E20 FBC_CLK1
FBC_CLK1 <31> FBx_CMD18 A2_BA0
FBA_D49 AN32 FBC_ D48 A32 F20 FBC _CLK1#
FBA_D49 FBB_D48 FBB_CLK1_N FBC_CLK1# <31>
FBA_D50 AP30
FBA_D50
FBC_ D49 C31
FBB_D49 FBx_CMD19 A4_BA2
FBA_D51 AP32 FBC_ D50 C32
FBA_D51 FBB_D50
FBA_D52
FBA_D53
AM33
AL31 FBA_D52 FBA_WCK01
K31
L30
FBA_ WCK0
FBA_WCK0 <28>
FBC_ D51 B32
D29 FBB_D51 F8
FBx_CMD20 A5_BA1
FBA_WCK0_N FBC_D52 FBC_WCK0
FBA_D53 FBA_WCK01_N FBA_WCK0_N <28> FBB_D52 FBB_WCK01 FBC_WCK0 <30>
FBA_D54 AK33
FBA_D54 FBA_WCK23
H34 FBA_ WCK1
FBA_WCK1 <28>
FBC_ D53 A29
FBB_D53 FBB_WCK01_N
E8 FBC _ W CK0_ N
FBC_WCK0_N <30> FBx_CMD21 WE#
FBA_D55 AK32 J34 FBA _ W CK1 _ N FBC_ D54 C29 A5 FBC_ W CK1
FBA_D55 FBA_WCK23_N FBA_WCK1_N <28> FBB_D54 FBB_WCK23 FBC_WCK1 <30>
FBA_D56 AD34
FBA_D56 FBA_WCK45
AG30 FBA_ WCK2
FBA_WCK2 <29>
FBC_ D55 B29
FBB_D55 FBB_WCK23_N
A6 FBC _ W CK1_ N
FBC_WCK1_N <30> FBx_CMD22 A7_A8
FBA_D57 AD32 AG31 FBA _ W CK2 _ N FBC_ D56 B21 D24 FBC_ W CK2
FBA_D57 FBA_WCK45_N FBA_WCK2_N <29> FBB_D56 FBB_WCK45 FBC_WCK2 <31>
FBA_D58 AC30
FBA_D58 FBA_WCK67
AJ34 FBA_WCK3
FBA_WCK3 <29>
FBC_D57 C23
FBB_D57 FBB_WCK45_N
D25 FBC_WCK2_N
FBC_WCK2_N <31> FBx_CMD23 A6_A11
FBA_D59 AD33 AK34 FBA _ W CK3 _ N FBC_ D58 A21 B27 FBC_ W CK3
FBA_D59 FBA_WCK67_N FBA_WCK3_N <29> FBB_D58 FBB_WCK67 FBC_WCK3 <31>
FBA_D60 AF31
FBA_D60
FBC_ D59 C21
FBB_D59 FBB_WCK67_N
C27 FBC _ W CK3_ N
FBC_WCK3_N <31> FBx_CMD24 ABI#
FBA_D61 AG34 FBC_ D60 B24
FBA_D61 FBB_D60
FBA_D62
FBA_D63
AG32
AG33 FBA_D62 J30
FBC_ D61 C24
B26 FBB_D61 FBx_CMD25 A12_RFU
FBC_D62
FBA_D63 FBA_WCKB01 FBB_D62
FBA_WCKB01_N
J31 FBC_ D63 C26
FBB_D63 FBB_WCKB01
D6 FBx_CMD26 A0_A10
FBA_DBI0# P30 J32 D7
<28> FBA_DBI0# FBA_DQM0 FBA_WCKB23 FBB_WCKB01_N
<28> FBA_DBI1#
FBA_DBI1# F31
FBA_DQM1 FBA_WCKB23_N
J33 GC6 support on 15" <30> FBC_DBI0#
FBC_DBI0# E11
FBB_DQM0 FBB_WCKB23
C6 FBx_CMD27 A1_A9
FBA_DBI2# F34 AH31 FBC_DBI1# E3 B6
<28> FBA_DBI2# FBA_DQM2 FBA_WCKB45 <30> FBC_DBI1# FBB_DQM1 FBB_WCKB23_N
B
<28> FBA_DBI3#
FBA_DBI3# M32
FBA_DQM3 FBA_WCKB45_N
AJ31
F B _CLAMP <30> FBC_DBI2#
FBC_DBI2# A3
FBB_DQM2 FBB_WCKB45
F26 FBx_CMD28 RAS# B
FBA_DBI4# AD31 AJ32 FBC_DBI3# C9 E26
<29> FBA_DBI4# FBA_DQM4 FBA_WCKB67 FB_CLAMP <23,45> <30> FBC_DBI3# FBB_DQM3 FBB_WCKB45_N
<29> FBA_DBI5#
FBA_DBI5# AL29
FBA_DQM5 FBA_WCKB67_N
AJ33
<31> FBC_DBI4#
FBC_DBI4# F23
FBB_DQM4 FBB_WCKB67
A26 FBx_CMD29 RST#
FBA_DBI6# AM32 FBC_DBI5# F27 A27
<29> FBA_DBI6# FBA_DQM6 <31> FBC_DBI5# FBB_DQM5 FBB_WCKB67_N
<29> FBA_DBI7#
FBA_DBI7# AF34
FBA_DQM7
BOM structure from "NOGC6@" to "Mount" <31> FBC_DBI6#
FBC_DBI6#
FBC_DBI7#
C30
A24 FBB_DQM6 FBx_CMD30 CKE#
RV66 10K_0402_5%
NOGC6@ <31> FBC_DBI7# FBB_DQM7
FBA _EDC0 M31
FBA_DQS_WP0 FB_CLAMP
E1 2 1 FBx_CMD31 CAS#
FBA _EDC1 G31 FBC_ EDC0 D10
<28> FBA_EDC[3..0] FBA_DQS_WP1 +FB_PLLAVDD FBB_DQS_WP0
FBA _EDC2 E33 FBC_ EDC1 D5
FBA _EDC3 M33 FBA_DQS_WP2 FBC_ EDC2 C3 FBB_DQS_WP1
CV106 0.1U_0402_10V7K
<29> FBA_EDC[7..4] FBA_EDC4 AE31 FBA_DQS_WP3 K27 1 2 FBC_EDC3 B9 FBB_DQS_WP2
FBA _EDC5 AK30 FBA_DQS_WP4 FB_DLL_AVDD FBC_ EDC4 E23 FBB_DQS_WP3 H17
FBA_DQS_WP5 FBB_DQS_WP4 FBB_PLL_AVDD +FB_PLLAVDD
FBA _EDC6 AN33 Place close to ball FBC_ EDC5 E28
FBA _EDC7 AF33 FBA_DQS_WP6 FBC_ EDC6 B30 FBB_DQS_WP5
FBA_DQS_WP7 FBB_DQS_WP6 1
U27 FBC_ EDC7 A23
FBA_PLL_AVDD +FB_PLLAVDD FBB_DQS_WP7
M30
H30 FBA_DQS_RN0 D9
FBA_DQS_RN1 1 1 1 <30> FBC_EDC[3..0] FBB_DQS_RN0
E34 E4 2
M34 FBA_DQS_RN2 H26 B2 FBB_DQS_RN1
AF30 FBA_DQS_RN3 FB_VREF <31> FBC_EDC[7..4] A9 FBB_DQS_RN2
AK31 FBA_DQS_RN4 2 2 2 D22 FBB_DQS_RN3
AM34 FBA_DQS_RN5 D28 FBB_DQS_RN4
FBA_DQS_RN6 FBB_DQS_RN5
Place close to ball
AF32 A30
FBA_DQS_RN7 B23 FBB_DQS_RN6 FBC _ RST# _ L
FBB_DQS_RN7
Place close to ball Place close to BGA FBC _ RST# _ H

For N13P-GT GC6 support N14P_FCBGA908

+3VS N14P_FCBGA908 RV74 RV73

FBA _ RST# _ L 10K_0402_5% 10K_0402_5%
D FBA_RST#_H

A
2 QV4 @ A
<18> DGPU_GC6_EN RV172 @
RV169 G 2N7002_SOT23
1 2
1 @ 2 S GC6_EN <32> RV71 RV72
0_0402_5%DV3 DAN202UT106_SC70-3
0_0402_5% 10K_0402_5% 10K_0402_5%
FB_CLAMP RV18
1 2 S_GC6_EN 2
GC6@ 1
2 0_0402_5%1 3 FBVDDQ_PWR_EN <55>
10K_0402_5% RV68 Security Classification LC Future Center Secret Data Title
GC6@ GC6@
RV29 GC6@
Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-MEM Interface
RV156 200K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
1 NOGC6@2 Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
<19,55,58> DGPU_PWROK
Custom 1.0
0_0402_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 27 of 65
5 4 3 2 1
 5 4 3 2 1

Memory - Lower 32 bits UV3 UV4

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBA_ D0 A4 FBA_ D24

FBA_ EDC0 C2 DQ24 DQ0 A2 FBA_ D1 FBA_ EDC3 C2 DQ24 DQ0 A2 FBA_ D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_ D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_ D26
FBA_ EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_ D3 FBA_ EDC1 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_ D27
<27> FBA_D[0..31] EDC2 EDC1 DQ27 DQ3 BYTE0 EDC2 EDC1 DQ27 DQ3
R2 E4 FBA_ D4 R2 E4 FBA_ D28 BYTE3
EDC3 EDC0 DQ28 DQ4 E2 FBA_ D5 EDC3 EDC0 DQ28 DQ4 E2 FBA_ D29
DQ29 DQ5 F4 FBA_ D6 DQ29 DQ5 F4 FBA_ D30
<27> FBA_EDC[3..0] DQ30 DQ6 DQ30 DQ6
FBA_DBI0# D2 F2 FBA_ D7 FBA_ DBI3# D2 F2 FBA_ D31
<27> FBA_DBI0# DBI0# DBI3# DQ31 DQ7 <27> FBA_DBI3# DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
FBA_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_ DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13
<27> FBA_DBI2# DBI2# DBI1# DQ17 DQ9 <27> FBA_DBI1# DBI2# DBI1# DQ17 DQ9
D
P2 B11 P2 B11 D
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBA_ CLK0 J12 DQ19 DQ11 E11 FBA_ CLK0 J12 DQ19 DQ11 E11
<27> FBA_CLK0 CK DQ20 DQ12 CK DQ20 DQ12
FBA_ CLK0# J11 E13 FBA_ CLK0# J11 E13
<27> FBA_CLK0# CK# DQ21 DQ13 CK# DQ21 DQ13
FBA_ CKE_ L J3 F11 FBA_ CKE_ L J3 F11
<27> FBA_CKE_L CKE# DQ22
DQ23
DQ14
DQ15
F13 CKE# DQ22
DQ23
DQ14
DQ15
F13 GDDR5
<27> FBA_MA2_BA0_L
FBA_ MA2_ BA0_ L H11
BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U11
U13
FBA_ D16
FBA_ D17 FBA_ MA4_ BA2_ L H11
BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U11
U13
FBA_ D8
FBA_ D9 Mode H - Mirror Mode Mapping
FBA_ MA5_ BA1_ L K10 T11 FBA_ D18 FBA_ MA3_ BA3_ L K10 T11 FBA_ D10
<27> FBA_MA5_BA1_L BA1/A5 BA3/A3 DQ10 DQ18 BA1/A5 BA3/A3 DQ10 DQ18
<27> FBA_MA4_BA2_L
FBA_MA4_BA2_L K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 FBA_D19 FBA_MA2_BA0_L K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 FBA_D11 BYTE1
FBA_ MA3_ BA3_ L H10 N11 FBA_ D20 BYTE2 FBA_ MA5_ BA1_ L H10 N11 FBA_ D12 DATA Bus
<27> FBA_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 BA3/A3 BA1/A5 DQ12 DQ20
N13 FBA_D21 N13 FBA_D13
DQ13 DQ21 DQ13 DQ21
DQ14 DQ22
M11 FBA _D22
DQ14 DQ22
M11 FBA _D14 Address 0..31 32..63
FBA_MA7_MA8_L K4 M13 FBA_D23 FBA_MA0_MA10_L K4 M13 FBA_D15
<27> FBA_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 A8/A7 A10/A0 DQ15 DQ23
FBA_ MA1_ MA9_ L H5 U4 FBA_ MA6_ MA11_ L H5 U4 FBx_CMD0 CS#
<27> FBA_MA1_MA9_L A9/A1 A11/A6 DQ0 DQ24 A9/A1 A11/A6 DQ0 DQ24
FBA_ MA0_ MA10_ L H4 U2 FBA_ MA7_ MA8_ L H4 U2
<27> FBA_MA0_MA10_L A10/A0 A8/A7 DQ1 DQ25 A10/A0 A8/A7 DQ1 DQ25
FBA_ MA6_ MA11_ L K5 T4 FBA_ MA1_ MA9_ L K5 T4 FBx_CMD1 A3_BA3
<27> FBA_MA6_MA11_L A11/A6 A9/A1 DQ2 DQ26 A11/A6 A9/A1 DQ2 DQ26
FBA_ MA12_ RFU_ L J5 T2 FBA_ MA12_ RFU_ L J5 T2
<27> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27
N4 N4 FBx_CMD2 A2_BA0
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
U5 VPP/NC DQ5 DQ29 M4 +1.5VS_VGA U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ6 DQ30 VPP/NC DQ6 DQ30 FBx_CMD3 A4_BA2
2 RV115 1 M2 2 RV116 1 M2
DQ7 DQ31 DQ7 DQ31
1K_0402 _1%
+1.5VS_VGA
1K_040 2_1%
+1.5VS_VGA
FBx_CMD4 A5_BA1
J1 J1
J10 MF J10 MF
2 RV117 1
SEN
2 RV118 1
SEN FBx_CMD5 WE#
2 RV119 1 1K_0402_1% J13 B1 2 RV120 1 1K_0402_1% J13 B1
121_0402_1% ZQ VDDQ D1 121_0402_1% ZQ VDDQ D1
VDDQ VDDQ FBx_CMD6 A7_A8
F1 F1
J4 VDDQ M1 J4 VDDQ M1
Follow DG <27> FBA_ABI#_L
FBA_ ABI#_ L
ABI# VDDQ
FBA_ ABI#_ L
ABI# VDDQ FBx_CMD7 A6_A11
FBA_ RAS#_ L G3 P1 FBA_ CAS#_ L G3 P1
<27> FBA_RAS#_L RAS# CAS# VDDQ RAS# CAS# VDDQ
FBA_ CS#_ L G12 T1 FBA_ W E#_ L G12 T1 FBx_CMD8 ABI#
<27> FBA_CS#_L CS# WE# VDDQ CS# WE# VDDQ
FBA_CLK0 1 2 FBA_CAS#_L L3 G2 FBA_RAS#_L L3 G2
<27> FBA_CAS#_L CAS# RAS# VDDQ CAS# RAS# VDDQ
RV21 40.2_0402_1 % FBA_W E#_ L L12 L2 FBA_ CS#_ L L12 L2 FBx_CMD9 A12_RFU
<27> FBA_W E#_L WE# CS# VDDQ WE# CS# VDDQ
B3 B3
VDDQ D3 VDDQ D3
VDDQ VDDQ FBx_CMD10 A0_A10
RV123 F3 F3
D5 VDDQ H3 D5 VDDQ H3
160_0402_1% <27> FBA_W CK0_N
FBA_ W CK0_ N
WCK01# WCK23# VDDQ
FBA_ W CK1_ N
WCK01# WCK23# VDDQ FBx_CMD11 A1_A9
@ FBA_ W CK0 D4 K3 FBA_ W CK1 D4 K3
C <27> FBA_W CK0 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ C
M3 M3 FBx_CMD12 RAS#
FBA_ CLK0# 1 2 FBA_ W CK1_ N P5 VDDQ P3 FBA_ W CK0_ N P5 VDDQ P3
<27> FBA_W CK1_N WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ
RV28 40.2_0402_1 % FBA_ W CK1 P4 T3 FBA_ W CK0 P4 T3 FBx_CMD13 RST#
<27> FBA_W CK1 WCK23 WCK01 VDDQ WCK23 WCK01 VDDQ
E5 E5
VDDQ N5 VDDQ N5
VDDQ VDDQ FBx_CMD14 CKE#
1 +FBA_ VREFD_ L A10 E10 +FBA_ VREFD_ L A10 E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
VREFD VDDQ VREFD VDDQ FBx_CMD15 CAS#
+FBA_ VREFC0 J14 B12 +FBA_ VREFC0 J14 B12
VREFC VDDQ D12 VREFC VDDQ D12
2 VDDQ VDDQ FBx_CMD16 CS#
F12 F12
VDDQ H12 VDDQ H12
VDDQ VDDQ FBx_CMD17 A3_BA3
FBA_ RST#_ L J2 K12 FBA_ RST#_ L J2 K12
<27> FBA_RST#_L RESET# VDDQ RESET# VDDQ
M12 M12 FBx_CMD18 A2_BA0
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
+1.5VS_VGA VDDQ VDDQ FBx_CMD19 A4_BA2
G13 G13
H1 VDDQ L13 H1 VDDQ L13
VSS VDDQ VSS VDDQ FBx_CMD20 A5_BA1
K1 B14 K1 B14
B5 VSS VDDQ D14 B5 VSS VDDQ D14
VSS VDDQ VSS VDDQ FBx_CMD21 WE#
RV127 G5 F14 G5 F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
549_0402_1%
VSS VDDQ VSS VDDQ FBx_CMD22 A7_A8
T5 P14 T5 P14
RV212 VSS VDDQ VSS VDDQ
B10 T14 B10 T14 FBx_CMD23 A6_A11
1 2 +FBA_VREFC0 D10 VSS VDDQ D10 VSS VDDQ
G10 VSS G10 VSS
931_0402_1%
VSS VSS FBx_CMD24 ABI#
1 16 mil L10 A1 L10 A1
P10 VSS VSSQ C1 P10 VSS VSSQ C1
RV128
VSS VSSQ VSS VSSQ FBx_CMD25 A12_RFU
1.33K_0402_1% T10 E1 T10 E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
2 VSS VSSQ VSS VSSQ FBx_CMD26 A0_A10
K14 R1 K14 R1
+1.5VS_VGA VSS VSSQ U1 +1.5VS_VGA VSS VSSQ U1
VSSQ VSSQ FBx_CMD27 A1_A9
H2 H2
G1 VSSQ K2 G1 VSSQ K2
VDD VSSQ VDD VSSQ FBx_CMD28 RAS#
L1 A3 L1 A3
G4 VDD VSSQ C3 G4 VDD VSSQ C3
VDD VSSQ VDD VSSQ FBx_CMD29 RST#
L4 E3 L4 E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
B
+1.5VS_VGA VDD VSSQ VDD VSSQ FBx_CMD30 CKE# B
R5 R3 R5 R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
VDD VSSQ VDD VSSQ FBx_CMD31 CAS#
R10 C4 R10 C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
RV129 G11 VDD VSSQ F5 G11 VDD VSSQ F5
549_0402_1% L11 VDD VSSQ M5 L11 VDD VSSQ M5
P11 VDD VSSQ F10 P11 VDD VSSQ F10
RV213 VDD VSSQ VDD VSSQ
G14 M10 G14 M10
1 2 +FBA_VREFD_L L14 VDD VSSQ C11 L14 VDD VSSQ C11
931_0402_1% VDD VSSQ R11 VDD VSSQ R11
VSSQ A12 VSSQ A12
1 VSSQ VSSQ
RV130 C12 C12
D 1.33K_0402_1% VSSQ E12 VSSQ E12
2 VSSQ N12 VSSQ N12
<23,29,30,31> MEM_VREF 2 VSSQ R12 VSSQ R12
G
QV9 170-BALL VSSQ U12 170-BALL VSSQ U12
S VSSQ VSSQ
2N7002W -T/R7_SOT323-3 H13 H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
X76@ X76@

H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE

2 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1

1 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-VRAM A Lower

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C ustom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y400-LA8691P
Date: Monday , March 11 , 2013 Sheet 28 of 65
5 4 3 2 1
 5 4 3 2 1

Memory - Upper 32 bits UV6

UV5
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0
A4 FBA_ D56
A4 FBA_ D32 FBA_ EDC7 C2 DQ24 DQ0 A2 FBA_ D57
FBA_ EDC4 C2 DQ24 DQ0 A2 FBA_ D33 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_ D58
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_ D34 FBA_ EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_ D59
FBA_ EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_ D35 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_ D60
<27> FBA_D[63..32] EDC2 EDC1 DQ27 DQ3 BYTE4 EDC3 EDC0 DQ28 DQ4 BYTE7
R2 E4 FBA_ D36 E2 FBA_ D61
EDC3 EDC0 DQ28 DQ4 E2 FBA_ D37 DQ29 DQ5 F4 FBA_ D62
DQ29 DQ5 F4 FBA_ D38 FBA_ DBI7# D2 DQ30 DQ6 F2 FBA_ D63
<27> FBA_EDC[7..4] DQ30 DQ6 <27> FBA_DBI7# DBI0# DBI3# DQ31 DQ7
FBA_DBI4# D2 F2 FBA_D39 D13 A11
<27> FBA_DBI4# D13 DBI0# DBI3# DQ31 DQ7 DBI1# DBI2# DQ16 DQ8
A11 FBA_DBI5# P13 A13
DBI1# DBI2# DQ16 DQ8 <27> FBA_DBI5# DBI2# DBI1# DQ17 DQ9
D
FBA_DBI6# P13 A13 P2 B11 D
<27> FBA_DBI6# P2 DBI2# DBI1# DQ17 DQ9 B11 DBI3# DBI0# DQ18 DQ10 B13
DBI3# DBI0# DQ18 DQ10 B13 FBA_ CLK1 J12 DQ19 DQ11 E11
FBA _CLK1 J12 DQ19 DQ11 E11 FBA_ CLK1# J11 CK DQ20 DQ12 E13
<27> FBA_CLK1 CK DQ20 DQ12 CK# DQ21 DQ13
FBA _CLK1# J11 E13 FBA_ CKE_ H J3 F11
<27> FBA_CLK1# CK# DQ21 DQ13 CKE# DQ22 DQ14
FBA _CKE_ H J3 F11 F13
<27> FBA_CKE_H CKE# DQ22 DQ14 DQ23 DQ15
F13 U11 FBA_ D40
DQ23 DQ15 U11 FBA _D48 FBA_ MA4_ BA2_ H H11 DQ8 DQ16 U13 FBA_ D41
FBA _ MA2_ BA0_ H H11 DQ8 DQ16 U13 FBA_ D49 FBA_ MA3_ BA3_ H K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_ D42
<27> FBA_MA2_BA0_H BA0/A2 BA2/A4 DQ9 DQ17 BA1/A5 BA3/A3 DQ10 DQ18
<27> FBA_MA5_BA1_H
FBA_MA5_BA1_H K10
BA1/A5 BA3/A3 DQ10 DQ18
T11 FBA_D50 FBA_MA2_BA0_H K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 FBA_D43 BYTE5
FBA _ MA4_ BA2_ H K11 T13 FBA_ D51 FBA_ MA5_ BA1_ H H10 N11 FBA_ D44
<27>
<27>
FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA3_BA3_H H10 BA2/A4
BA3/A3
BA0/A2
BA1/A5
DQ11
DQ12
DQ19
DQ20
N11 FBA_D52 BYTE6
BA3/A3 BA1/A5 DQ12
DQ13
DQ20
DQ21
N13 FBA_D45 GDDR5
DQ13
DQ14
DQ21
DQ22
N13
M11
FBA _D53
FBA_D54 FBA_MA0_MA10_H K4
A8/A7 A10/A0
DQ14
DQ15
DQ22
DQ23
M11
M13
FBA_ D46
FBA_D47 Mode H - Mirror Mode Mapping
FBA _MA7_ MA8_ H K4 M13 FBA_ D55 FBA_ MA6_ MA11_ H H5 U4
<27> FBA_MA7_MA8_H A8/A7 A10/A0 DQ15 DQ23 A9/A1 A11/A6 DQ0 DQ24
FBA _MA1_ MA9_ H H5 U4 FBA_ MA7_ MA8_ H H4 U2
<27> FBA_MA1_MA9_H A9/A1 A11/A6 DQ0 DQ24 A10/A0 A8/A7 DQ1 DQ25
FBA _MA0_ MA10_ H H4 U2 FBA_ MA1_ MA9_ H K5 T4 DATA Bus
<27> FBA_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25 A11/A6 A9/A1 DQ2 DQ26
FBA _MA6_ MA11_ H K5 T4 FBA_ MA12_ RFU_ H J5 T2
<27> FBA_MA6_MA11_H A11/A6 A9/A1 DQ2 DQ26 A12/RFU/NC DQ3 DQ27
<27> FBA_MA12_RFU_H
FBA _MA12_ RFU_ H J5
A12/RFU/N C DQ3 DQ27
T2
DQ4 DQ28
N4 Address 0..31 32..63
N4 A5 N2
A5 DQ4 DQ28 N2 +1.5VS_VGA U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ5 DQ29 VPP/NC DQ6 DQ30 FBx_CMD0 CS#
U5 M4 2 RV132 1 M2
2 RV131 1 VPP/NC DQ6 DQ30 M2 DQ7 DQ31
DQ7 DQ31
1K_0402_1%
+1.5VS_VGA
FBx_CMD1 A3_BA3
1K_0402_1% J1
J1 +1.5VS_VGA J10 MF
MF
2 RV134 1
SEN FBx_CMD2 A2_BA0
2 RV133 1 J10 2 RV136 1 1K_0402_1% J13 B1
2 RV135 1 1K_0402_1% J13 SEN B1 ZQ VDDQ D1
ZQ VDDQ
121_0402_1%
VDDQ FBx_CMD3 A4_BA2
121_0402_1% D1 F1
VDDQ F1 J4 VDDQ M1
Follow DG VDDQ
FBA_ ABI#_ H
ABI# VDDQ FBx_CMD4 A5_BA1
FBA _ABI#_ H J4 M1 FBA_ CAS#_ H G3 P1
<27> FBA_ABI#_H ABI# VDDQ RAS# CAS# VDDQ
FBA _RAS#_ H G3 P1 FBA_ W E#_ H G12 T1 FBx_CMD5 WE#
<27> FBA_RAS#_H RAS# CAS# VDDQ CS# WE# VDDQ
FBA_CS#_H G12 T1 FBA_RAS#_H L3 G2
<27> FBA_CS#_H CS# WE# VDDQ CAS# RAS# VDDQ
FBA_ CLK1 1 2 FBA_ CAS#_ H L3 G2 FBA_ CS#_ H L12 L2 FBx_CMD6 A7_A8
<27> FBA_CAS#_H CAS# RAS# VDDQ WE# CS# VDDQ
RV31 40.2_0402_ 1 % FBA_W E#_H L12 L2 B3
<27> FBA_W E#_H WE# CS# VDDQ VDDQ
B3 D3 FBx_CMD7 A6_A11
VDDQ D3 VDDQ F3
RV139 VDDQ F3 D5 VDDQ H3
VDDQ
FBA_ W CK3_ N
WCK01# WCK23# VDDQ FBx_CMD8 ABI#
160_0402_1% FBA _W CK2_ N D5 H3 FBA_ W CK3 D4 K3
C <27> FBA_W CK2_N WCK01# WCK23# VDDQ WCK01 WCK23 VDDQ C
@ FBA _W CK2 D4 K3 M3 FBx_CMD9 A12_RFU
<27> FBA_W CK2 WCK01 WCK23 VDDQ VDDQ
M3 FBA_ W CK2_ N P5 P3
1 2 P5 VDDQ P3 P4 WCK23# WCK01# VDDQ T3
FBA_ CLK1#
<27> FBA_W CK3_N
FBA_W CK3_ N
WCK23# WCK01# VDDQ
FBA_ W CK2
WCK23 WCK01 VDDQ FBx_CMD10 A0_A10
RV36 40.2_0402_ 1 % FBA_W CK3 P4 T3 E5
<27> FBA_W CK3 WCK23 WCK01 VDDQ VDDQ
E5 N5 FBx_CMD11 A1_A9
VDDQ N5 +FBA_ VREFD_ H A10 VDDQ E10
+FBA_VREFD_H A10 VDDQ E10 U10 VREFD VDDQ N10
1 VREFD VDDQ VREFD VDDQ FBx_CMD12 RAS#
U10 N10 +FBA_ VREFC1 J14 B12
J14 VREFD VDDQ B12 VREFC VDDQ D12
+FBA_VREFC1
VREFC VDDQ VDDQ FBx_CMD13 RST#
D12 F12
2 VDDQ F12 VDDQ H12
VDDQ VDDQ FBx_CMD14 CKE#
H12 FBA_ RST#_ H J2 K12
J2 VDDQ K12 RESET# VDDQ M12
<27> FBA_RST#_H
FBA_RST#_ H
RESET# VDDQ VDDQ FBx_CMD15 CAS#
M12 P12
VDDQ P12 VDDQ T12
VDDQ VDDQ FBx_CMD16 CS#
T12 G13
VDDQ G13 H1 VDDQ L13
VDDQ VSS VDDQ FBx_CMD17 A3_BA3
H1 L13 K1 B14
+1.5VS_VGA K1 VSS VDDQ B14 B5 VSS VDDQ D14
VSS VDDQ VSS VDDQ FBx_CMD18 A2_BA0
B5 D14 G5 F14
G5 VSS VDDQ F14 L5 VSS VDDQ M14
VSS VDDQ VSS VDDQ FBx_CMD19 A4_BA2
L5 M14 T5 P14
T5 VSS VDDQ P14 B10 VSS VDDQ T14
RV143
VSS VDDQ VSS VDDQ FBx_CMD20 A5_BA1
549_0402_1% B10 T14 D10
D10 VSS VDDQ G10 VSS
RV214 VSS VSS FBx_CMD21 WE#
G10 L10 A1
1 2 +FBA_VREFC1 L10 VSS A1 P10 VSS VSSQ C1
VSS VSSQ VSS VSSQ FBx_CMD22 A7_A8
931_0402_1% 16 mil P10 C1 T10 E1
T10 VSS VSSQ E1 H14 VSS VSSQ N1
1 VSS VSSQ VSS VSSQ FBx_CMD23 A6_A11
RV144 H14 N1 K14 R1
K14 VSS VSSQ R1 +1.5VS_VGA VSS VSSQ U1
1.33K_0402_1%
+1.5VS_VGA VSS VSSQ VSSQ FBx_CMD24 ABI#
U1 H2
2 VSSQ H2 G1 VSSQ K2
VSSQ VDD VSSQ FBx_CMD25 A12_RFU
G1 K2 L1 A3
L1 VDD VSSQ A3 G4 VDD VSSQ C3
VDD VSSQ VDD VSSQ FBx_CMD26 A0_A10
G4 C3 L4 E3
L4 VDD VSSQ E3 C5 VDD VSSQ N3
B VDD VSSQ VDD VSSQ FBx_CMD27 A1_A9 B
C5 N3 R5 R3
R5 VDD VSSQ R3 C10 VDD VSSQ U3
VDD VSSQ VDD VSSQ FBx_CMD28 RAS#
C10 U3 R10 C4
R10 VDD VSSQ C4 D11 VDD VSSQ R4
+1.5VS_VGA VDD VSSQ VDD VSSQ FBx_CMD29 RST#
D11 R4 G11 F5
G11 VDD VSSQ F5 L11 VDD VSSQ M5
VDD VSSQ VDD VSSQ FBx_CMD30 CKE#
L11 M5 P11 F10
P11 VDD VSSQ F10 G14 VDD VSSQ M10
VDD VSSQ VDD VSSQ FBx_CMD31 CAS#
RV145 G14 M10 L14 C11
549_0402_1% L14 VDD VSSQ C11 VDD VSSQ R11
VDD VSSQ R11 VSSQ A12
RV215 VSSQ VSSQ
A12 C12
1 2 +FBA _VREFD_ H VSSQ C12 VSSQ E12
931_0402_1% VSSQ E12 VSSQ N12
VSSQ N12 VSSQ R12
1 VSSQ VSSQ
RV146 R12 170-BALL U12
D 1.33K_0402_1% 170-BALL VSSQ U12 VSSQ H13
2 VSSQ H13 SGRAM GDDR5 VSSQ K13
<23,28,30,31> MEM_VREF 2 SGRAM GDDR5 VSSQ K13 VSSQ A14
G
S QV11 VSSQ A14 VSSQ C14
2N7002W-T/R7_SOT323-3 VSSQ C14 VSSQ E14
VSSQ E14 VSSQ N14
VSSQ N14 VSSQ R14
VSSQ R14 VSSQ U14
VSSQ U14 VSSQ
VSSQ X76@
X76@
+1.5VS_VGA UV5 SIDE H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV6 SIDE
2 1 1 1 1 1 1 1

2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2
A A
1 2 2 2 2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-VRAM A Upper

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C ustom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y400S-NM-A141
Date: Monday , March 11 , 2013 Sheet 29 of 65
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits

UV7 UV8

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBC _ D0 A4 FBC_ D24

FBC_ EDC0 C2 DQ24 DQ0 A2 FBC _ D1 FBC_ EDC3 C2 DQ24 DQ0 A2 FBC_ D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBC _ D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_ D26
FBC_ EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_ EDC1 R13 EDC1 EDC2 DQ26 DQ2 B2
<27> FBC_D[0..31] R2 EDC2 EDC1 DQ27 DQ3 E4
FBC _ D3
FBC_D4
BYTE0 R2 EDC2 EDC1 DQ27 DQ3 E4
FBC_ D27
FBC_D28
EDC3 EDC0 DQ28 DQ4 E2 FBC _ D5 EDC3 EDC0 DQ28 DQ4 E2 FBC_ D29
BYTE3
DQ29 DQ5 F4 FBC _ D6 DQ29 DQ5 F4 FBC_ D30
<27> FBC_EDC[3..0] FBC_DBI0# D2 DQ30 DQ6 F2 FBC_ DBI3# D2 DQ30 DQ6 F2
D FBC _ D7 FBC_ D31 D
<27> FBC_DBI0# DBI0# DBI3# DQ31 DQ7 <27> FBC_DBI3# DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
FBC_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBC_DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13
<27> FBC_DBI2# P2 DBI2# DBI1# DQ17 DQ9 B11 <27> FBC_DBI1# P2 DBI2# DBI1# DQ17 DQ9 B11
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBC_CLK0 J12 DQ19 DQ11 E11 FBC_ CLK0 J12 DQ19 DQ11 E11
<27> FBC_CLK0 CK DQ20 DQ12 CK DQ20 DQ12
<27> FBC_CLK0#
<27> FBC_CKE_L
FBC _CLK0#
FBC_CKE_L
J11
J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
E13
F11
FBC _ CLK0#
FBC_CKE_L
J11
J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
E13
F11 GDDR5
DQ23
DQ8
DQ15
DQ16
F13
U11 FBC_ D16 DQ23
DQ8
DQ15
DQ16
F13
U11 FBC _ D8 Mode H - Mirror Mode Mapping
FBC _ MA2 _ BA0_ L H11 U13 FBC_ D17 FBC_ MA4_ BA2_ L H11 U13 FBC_ D9
<27> FBC_MA2_BA0_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11
FBC _ MA5 _ BA1_ L FBC_ D18 FBC_ MA3_ BA3_ L FBC_ D10
<27> FBC_MA5_BA1_L BA1/A5 BA3/A3 DQ10 DQ18 BA1/A5 BA3/A3 DQ10 DQ18
<27> FBC_MA4_BA2_L
FBC_MA4_BA2_L K11
H10 BA2/A4 BA0/A2 DQ11 DQ19
T13
N11
FBC_D19 FBC_MA2_BA0_L K11
H10 BA2/A4 BA0/A2 DQ11 DQ19
T13
N11
FBC_D11
BYTE1 DATA Bus
<27> FBC_MA3_BA3_L
FBC _ MA3 _ BA3_ L
BA3/A3 BA1/A5 DQ12 DQ20
FBC_ D20
BYTE2 FBC_ MA5_ BA1_ L
BA3/A3 BA1/A5 DQ12 DQ20
FBC_ D12
DQ13 DQ21
N13 FBC _D21
DQ13 DQ21
N13 FBC_ D13 Address 0..31 32..63
M11 FBC _D22 M11 FBC_ D14
DQ14 DQ22 DQ14 DQ22
<27> FBC_MA7_MA8_L
FBC _ MA7 _ MA8_ L K4
H5 A8/A7 A10/A0 DQ15 DQ23
M13
U4
FBC_ D23 FBC_ MA0_ MA10_ L K4
H5 A8/A7 A10/A0 DQ15 DQ23
M13
U4
FBC_ D15 FBx_CMD0 CS#
FBC_MA1_MA9_L FBC_MA6_MA11_L
<27> FBC_MA1_MA9_L A9/A1 A11/A6 DQ0 DQ24 A9/A1 A11/A6 DQ0 DQ24
<27> FBC_MA0_MA10_L
FBC _ MA0 _ MA10 _ L H4
K5 A10/A0 A8/A7 DQ1 DQ25
U2
T4
FBC _ MA7_ MA8_ L H4
K5 A10/A0 A8/A7 DQ1 DQ25
U2
T4
FBx_CMD1 A3_BA3
FBC _ MA6 _ MA11 _ L FBC _ MA1_ MA9_ L
<27> FBC_MA6_MA11_L A11/A6 A9/A1 DQ2 DQ26 A11/A6 A9/A1 DQ2 DQ26
<27> FBC_MA12_RFU_L
FBC _ MA12 _ RFU _ L J5
A12/RFU/NC DQ3 DQ27
T2
N4
FBC _ MA12_ RFU_ L J5
A12/RFU/NC DQ3 DQ27
T2
N4
FBx_CMD2 A2_BA0
DQ4 DQ28 DQ4 DQ28
A5
U5 VPP/NC DQ5 DQ29
N2
M4 +1.5VS_VGA
A5
U5 VPP/NC DQ5 DQ29
N2
M4
FBx_CMD3 A4_BA2
VPP/NC DQ6 DQ30 VPP/NC DQ6 DQ30
2 RV147 1
DQ7 DQ31
M2 2 RV148 1
DQ7 DQ31
M2 FBx_CMD4 A5_BA1
1K_04 0 2_1% 1K_04 0 2_1%
+1.5VS_VGA +1.5VS_VGA
2 RV149 1
J1
J10 MF 2 RV150 1
J1
J10 MF FBx_CMD5 WE#
SEN SEN
2 RV151 1 1K_0402_1% J13
ZQ VDDQ
B1
D1
2 RV152 1 1K_0402_1% J13
ZQ VDDQ
B1
D1
FBx_CMD6 A7_A8
121_0402_1% 121_0402_1%
VDDQ VDDQ
J4 VDDQ
F1
M1 J4 VDDQ
F1
M1
FBx_CMD7 A6_A11
Follow DG <27> FBC_ABI#_L
FBC _ ABI# _ L
ABI# VDDQ
FBC _ ABI#_ L
ABI# VDDQ
<27> FBC_RAS#_L
FBC_RAS#_L G3
G12 RAS# CAS# VDDQ
P1
T1
FBC_CAS#_L G3
G12 RAS# CAS# VDDQ
P1
T1
FBx_CMD8 ABI#
FBC _ CS# _ L FBC _ W E#_ L
<27> FBC_CS#_L CS# W E# VDDQ CS# W E# VDDQ
FBC_CLK0 1 2
<27> FBC_CAS#_L
FBC _ CAS# _ L L3
CAS# RAS# VDDQ
G2 FBC _ RAS#_ L L3
CAS# RAS# VDDQ
G2 FBx_CMD9 A12_RFU
RV37 40.2_0402_ 1 % FBC _ W E#_ L L12 L2 FBC _ CS#_ L L12 L2
<27> FBC_W E#_L W E# CS# VDDQ W E# CS# VDDQ
VDDQ
B3
D3 VDDQ
B3
D3
FBx_CMD10 A0_A10
C VDDQ VDDQ C
RV155
VDDQ
F3
VDDQ
F3 FBx_CMD11 A1_A9
160_0402_1% FBC _ W CK0 _ N D5 H3 FBC _ W CK1_ N D5 H3
<27> FBC_WCK0_N W CK01# W CK23# VDDQ W CK01# W CK23# VDDQ
@
<27> FBC_WCK0
FBC_ WCK0 D4
W CK01 W CK23 VDDQ
K3 FBC_ WCK1 D4
W CK01 W CK23 VDDQ
K3 FBx_CMD12 RAS#
M3 M3
VDDQ VDDQ
FBC_CLK0# 1 2
<27> FBC_WCK1_N
FBC_WCK1_N P5
W CK23# W CK01# VDDQ
P3 FBC_WCK0_N P5
W CK23# W CK01# VDDQ
P3 FBx_CMD13 RST#
RV39 40.2_0402_ 1 % FBC_ WCK1 P4 T3 FBC_ WCK0 P4 T3
<27> FBC_WCK1 W CK23 W CK01 VDDQ W CK23 W CK01 VDDQ
VDDQ
E5
VDDQ
E5 FBx_CMD14 CKE#
N5 N5
VDDQ VDDQ
1 +FBC _ VREFD _ L A10
U10 VREFD VDDQ
E10
N10
+FBC _ VREFD _ L A10
U10 VREFD VDDQ
E10
N10
FBx_CMD15 CAS#
VREFD VDDQ VREFD VDDQ
+FBC _VREFC0 J14
VREFC VDDQ
B12 +FBC _ VREFC0 J14
VREFC VDDQ
B12 FBx_CMD16 CS#
D12 D12
2 VDDQ VDDQ
VDDQ
F12
VDDQ
F12 FBx_CMD17 A3_BA3
H12 H12
VDDQ VDDQ
<27> FBC_RST#_L
FBC_RST#_L J2
RESET# VDDQ
K12 FBC_RST#_L J2
RESET# VDDQ
K12 FBx_CMD18 A2_BA0
M12 M12
VDDQ VDDQ
VDDQ
P12
VDDQ
P12 FBx_CMD19 A4_BA2
T12 T12
+1.5VS_VGA VDDQ VDDQ
H1 VDDQ
G13
L13 H1 VDDQ
G13
L13
FBx_CMD20 A5_BA1
VSS VDDQ VSS VDDQ
K1
VSS VDDQ
B14 K1
VSS VDDQ
B14 FBx_CMD21 WE#
B5 D14 B5 D14
VSS VDDQ VSS VDDQ
RV159 G5
VSS VDDQ
F14 G5
VSS VDDQ
F14 FBx_CMD22 A7_A8
549_0402_1% L5 M14 L5 M14
VSS VDDQ VSS VDDQ
RV216
T5
VSS VDDQ
P14 T5
VSS VDDQ
P14 FBx_CMD23 A6_A11
B10 T14 B10 T14
VSS VDDQ VSS VDDQ
1 2 +FBC_VREFC0 D10
VSS
D10
VSS FBx_CMD24 ABI#
931_0402_1% G10 G10
VSS VSS
1 L10
P10 VSS VSSQ
A1
C1
L10
P10 VSS VSSQ
A1
C1
FBx_CMD25 A12_RFU
RV160
VSS VSSQ VSS VSSQ
1.33K_0402_1% T10
VSS VSSQ
E1 T10
VSS VSSQ
E1 FBx_CMD26 A0_A10
H14 N1 H14 N1
2 VSS VSSQ VSS VSSQ
+1.5VS_VGA
K14
VSS VSSQ
R1
+1.5VS_VGA
K14
VSS VSSQ
R1 FBx_CMD27 A1_A9
U1 U1
VSSQ VSSQ
G1 VSSQ
H2
K2 G1 VSSQ
H2
K2
FBx_CMD28 RAS#
VDD VSSQ VDD VSSQ
B
L1
G4 VDD VSSQ
A3
C3
L1
G4 VDD VSSQ
A3
C3
FBx_CMD29 RST# B
VDD VSSQ VDD VSSQ
L4
VDD VSSQ
E3 L4
VDD VSSQ
E3 FBx_CMD30 CKE#
C5 N3 C5 N3
VDD VSSQ VDD VSSQ
+1.5VS_VGA
R5
C10 VDD VSSQ
R3
U3
R5
C10 VDD VSSQ
R3
U3
FBx_CMD31 CAS#
R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
L11 VDD VSSQ M5 L11 VDD VSSQ M5
RV161
P11 VDD VSSQ F10 P11 VDD VSSQ F10
549_0402_1%
G14 VDD VSSQ M10 G14 VDD VSSQ M10
RV217 L14 VDD VSSQ C11 L14 VDD VSSQ C11
1 2 +FBC_VREFD_L VDD VSSQ R11 VDD VSSQ R11
931_0402_1% VSSQ A12 VSSQ A12
VSSQ C12 VSSQ C12
1 VSSQ VSSQ
RV162 E12 E12
VSSQ N12 VSSQ N12
1.33K_0402_1%
VSSQ R12 VSSQ R12
D 2 VSSQ U12 VSSQ U12
170-BALL 170-BALL
2 VSSQ H13 VSSQ H13
<23,28,29,31> MEM_VREF VSSQ K13 VSSQ K13
G SGRAM GDDR5 SGRAM GDDR5
VSSQ A14 VSSQ A14
S QV13
VSSQ C14 VSSQ C14
2N7002W -T/R7_SOT323-3
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ
+1.5VS_VGA UV8 SIDE VSSQ
X76@ X76@
+1.5VS_VGA UV7 SIDE H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
2 1 1 1 1 1 1 1

2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2

A A
1 2 2 2 2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P-VRAM C Lower

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 30 of 65
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits

UV9

MF=0 MF=1 MF=1 MF=0 UV10

A4 FBC_D32 MF=0 MF=1 MF=1 MF=0

FBC_ EDC4 C2 DQ24 DQ0 A2 FBC_ D33
C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_ D34 A4 FBC_ D56
FBC_ EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_ EDC7 C2 DQ24 DQ0 A2
<27> FBC_D[63..32] R2 EDC2 EDC1 DQ27 DQ3 E4
FBC_ D35
FBC_ D36
BYTE4 C13 EDC0 EDC3 DQ25 DQ1 B4
FBC_ D57
FBC_ D58
EDC3 EDC0 DQ28 DQ4 E2 FBC_D37 FBC_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D59
DQ29 DQ5 F4 FBC_ D38 R2 EDC2 EDC1 DQ27 DQ3 E4 FBC_ D60
<27> FBC_EDC[7..4] FBC_DBI4# D2 DQ30 DQ6 F2 FBC_ D39 EDC3 EDC0 DQ28 DQ4 E2 FBC_ D61
BYTE7
<27> FBC_DBI4# DBI0# DBI3# DQ31 DQ7 DQ29 DQ5
D
D13 A11 F4 FBC_ D62 D
DBI1# DBI2# DQ16 DQ8 DQ30 DQ6
<27> FBC_DBI6#
FBC_DBI6# P13
P2 DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
A13
B11
<27> FBC_DBI7#
FBC_ DBI7# D2
D13 DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
F2
A11
FBC_ D63
GDDR5
<27> FBC_CLK1
FBC_CLK1 J12
CK
DQ19
DQ20
DQ11
DQ12
B13
E11 <27> FBC_DBI5#
FBC_ DBI5# P13
P2 DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
A13
B11 Mode H - Mirror Mode Mapping
FBC _CLK1# J11 E13 B13
<27> FBC_CLK1# J3 CK# DQ21 DQ13 F11 J12 DQ19 DQ11 E11
FBC _ CKE _ H FBC_ CLK1
<27> FBC_CKE_H CKE# DQ22 DQ14 CK DQ20 DQ12
DQ23 DQ15
F13
U11
FBC_CLK1# J11
J3 CK# DQ21 DQ13
E13
F11
DATA Bus
FBC_ D48 FBC _ CKE _ H
DQ8 DQ16 CKE# DQ22 DQ14
<27> FBC_MA2_BA0_H
FBC _ MA2 _ BA0_ H H11
BA0/A2 BA2/A4 DQ9 DQ17
U13 FBC_ D49
DQ23 DQ15
F13 Address 0..31 32..63
FBC _ MA5 _ BA1_ H K10 T11 FBC_ D50 U11 FBC_ D40
<27> FBC_MA5_BA1_H BA1/A5 BA3/A3 DQ10 DQ18 DQ8 DQ16
<27> FBC_MA4_BA2_H
FBC _ MA4 _ BA2_ H K11
H10 BA2/A4 BA0/A2 DQ11 DQ19
T13
N11
FBC_ D51 FBC_ MA4_ BA2_ H H11
K10 BA0/A2 BA2/A4 DQ9 DQ17
U13
T11
FBC_ D41 FBx_CMD0 CS#
FBC_MA3_BA3_H FBC_D52 FBC_MA3_BA3_H FBC_D42
<27> FBC_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 BYTE6 BA1/A5 BA3/A3 DQ10 DQ18
DQ13 DQ21
N13
M11
FBC_ D53 FBC _ MA2 _ BA0_ H K11
H10 BA2/A4 BA0/A2 DQ11 DQ19
T13
N11
FBC_ D43
BYTE5 FBx_CMD1 A3_BA3
FBC_ D54 FBC _ MA5 _ BA1_ H FBC_ D44
DQ14 DQ22 BA3/A3 BA1/A5 DQ12 DQ20
<27> FBC_MA7_MA8_H
FBC _ MA7 _ MA8_ H K4
H5 A8/A7 A10/A0 DQ15 DQ23
M13
U4
FBC_ D55
DQ13 DQ21
N13
M11
FBC_ D45 FBx_CMD2 A2_BA0
FBC _ MA1 _ MA9_ H FBC_ D46
<27> FBC_MA1_MA9_H A9/A1 A11/A6 DQ0 DQ24 DQ14 DQ22
<27> FBC_MA0_MA10_H
FBC_MA0_MA10_H H4
K5 A10/A0 A8/A7 DQ1 DQ25
U2
T4
FBC_MA0_MA10_H K4
H5 A8/A7 A10/A0 DQ15 DQ23
M13
U4
FBC_D47 FBx_CMD3 A4_BA2
FBC _ MA6 _ MA11_ H FBC _ MA6_ MA11_ H
<27> FBC_MA6_MA11_H A11/A6 A9/A1 DQ2 DQ26 A9/A1 A11/A6 DQ0 DQ24
<27> FBC_MA12_RFU_H
FBC _ MA12 _ RFU _ H J5
A12/RFU/NC DQ3 DQ27
T2 FBC _ MA7_ MA8_ H H4
A10/A0 A8/A7 DQ1 DQ25
U2 FBx_CMD4 A5_BA1
N4 FBC _ MA1 _ MA9_ H K5 T4
DQ4 DQ28 A11/A6 A9/A1 DQ2 DQ26
A5
U5 VPP/NC DQ5 DQ29
N2
M4
FBC _ MA12 _ RFU _ H J5
A12/RFU/NC DQ3 DQ27
T2
N4
FBx_CMD5 WE#
VPP/NC DQ6 DQ30 DQ4 DQ28
2 RV163 1
DQ7 DQ31
M2
+1.5VS_VGA
A5
U5 VPP/NC DQ5 DQ29
N2
M4
FBx_CMD6 A7_A8
1K_04 0 2_1%
+1.5VS_VGA VPP/NC DQ6 DQ30
2 RV165 1
J1
J10 MF
2 RV164 1
DQ7 DQ31
M2 FBx_CMD7 A6_A11
1K_0402_1%
SEN +1.5VS_VGA
2 RV167 1 1K_0402_1% J13
ZQ VDDQ
B1
D1 2 RV166 1
J1
J10 MF FBx_CMD8 ABI#
121_0402_1%
VDDQ SEN
VDDQ
F1 2 RV168 1 1K_0402_1% J13
ZQ VDDQ
B1 FBx_CMD9 A12_RFU
J4 M1 D1
Follow DG <27> FBC_ABI#_H
FBC _ ABI# _ H
ABI# VDDQ
121_0402_1%
VDDQ
<27> FBC_RAS#_H
FBC _ RAS# _ H G3
G12 RAS# CAS# VDDQ
P1
T1 J4 VDDQ
F1
M1
FBx_CMD10 A0_A10
FBC_CS#_H FBC_ABI#_H
<27> FBC_CS#_H CS# W E# VDDQ ABI# VDDQ
FBC_CLK1 1 2
<27> FBC_CAS#_H
FBC _ CAS# _ H L3
L12 CAS# RAS# VDDQ
G2
L2
FBC _ CAS#_ H G3
G12 RAS# CAS# VDDQ
P1
T1
FBx_CMD11 A1_A9
RV41 40.2_0402_ 1% FBC _ W E#_ H FBC _ W E#_ H
<27> FBC_W E#_H W E# CS# VDDQ CS# W E# VDDQ
VDDQ
B3 FBC _ RAS# _ H L3
CAS# RAS# VDDQ
G2 FBx_CMD12 RAS#
D3 FBC _ CS# _ H L12 L2
VDDQ W E# CS# VDDQ
C RV171
VDDQ
F3
VDDQ
B3 FBx_CMD13 RST# C
160_0402_1% FBC _ W CK2 _ N D5 H3 D3
<27> FBC_WCK2_N W CK01# W CK23# VDDQ VDDQ
@
<27> FBC_WCK2
FBC_ WCK2 D4
W CK01 W CK23 VDDQ
K3
VDDQ
F3 FBx_CMD14 CKE#
M3 FBC _ W CK3 _ N D5 H3
VDDQ W CK01# W CK23# VDDQ
FBC _CLK1# 1 2
<27> FBC_WCK3_N
FBC _ W CK3_ N P5
P4 W CK23# W CK01# VDDQ
P3
T3
FBC_ WCK3 D4
W CK01 W CK23 VDDQ
K3
M3
FBx_CMD15 CAS#
RV48 40.2_0402_ 1% FBC_WCK3
<27> FBC_WCK3 W CK23 W CK01 VDDQ VDDQ
VDDQ
E5 FBC _ W CK2 _ N P5
W CK23# W CK01# VDDQ
P3 FBx_CMD16 CS#
N5 FBC_ WCK2 P4 T3
VDDQ W CK23 W CK01 VDDQ
1 +FBC _ VREFD _ H A10
VREFD VDDQ
E10
VDDQ
E5 FBx_CMD17 A3_BA3
U10 N10 N5
VREFD VDDQ VDDQ
+FBC_VREFC1 J14
VREFC VDDQ
B12 +FBC_VREFD_H A10
VREFD VDDQ
E10 FBx_CMD18 A2_BA0
D12 U10 N10
2 VDDQ VREFD VDDQ
VDDQ
F12 +FBC _VREFC1 J14
VREFC VDDQ
B12 FBx_CMD19 A4_BA2
H12 D12
VDDQ VDDQ
<27> FBC_RST#_H
FBC _ RST# _ H J2
RESET# VDDQ
K12
M12 VDDQ
F12
H12
FBx_CMD20 A5_BA1
VDDQ VDDQ
VDDQ
P12 FBC _ RST# _ H J2
RESET# VDDQ
K12 FBx_CMD21 WE#
T12 M12
+1.5VS_VGA VDDQ VDDQ
VDDQ
G13
VDDQ
P12 FBx_CMD22 A7_A8
H1 L13 T12
VSS VDDQ VDDQ
K1
VSS VDDQ
B14
VDDQ
G13 FBx_CMD23 A6_A11
B5 D14 H1 L13
VSS VDDQ VSS VDDQ
RV175 G5
VSS VDDQ
F14 K1
VSS VDDQ
B14 FBx_CMD24 ABI#
549_0402_1% L5 M14 B5 D14
VSS VDDQ VSS VDDQ
RV218
T5
B10 VSS VDDQ
P14
T14
G5
L5 VSS VDDQ
F14
M14
FBx_CMD25 A12_RFU
VSS VDDQ VSS VDDQ
1 2 +FBC_VREFC1 D10
VSS
T5
VSS VDDQ
P14 FBx_CMD26 A0_A10
931_0402_1% G10 B10 T14
VSS VSS VDDQ
1 L10
VSS VSSQ
A1 D10
VSS FBx_CMD27 A1_A9
RV176 P10 C1 G10
VSS VSSQ VSS
1.33K_0402_1% T10
VSS VSSQ
E1 L10
VSS VSSQ
A1 FBx_CMD28 RAS#
H14 N1 P10 C1
2 VSS VSSQ VSS VSSQ
+1.5VS_VGA
K14
VSS VSSQ
R1 T10
VSS VSSQ
E1 FBx_CMD29 RST#
U1 H14 N1
VSSQ VSS VSSQ
VSSQ
H2
+1.5VS_VGA
K14
VSS VSSQ
R1 FBx_CMD30 CKE#
G1 K2 U1
VDD VSSQ VSSQ
L1
G4 VDD VSSQ
A3
C3 G1 VSSQ
H2
K2
FBx_CMD31 CAS#
B VDD VSSQ VDD VSSQ B
L4 E3 L1 A3
C5 VDD VSSQ N3 G4 VDD VSSQ C3
+1.5VS_VGA R5 VDD VSSQ R3 L4 VDD VSSQ E3
C10 VDD VSSQ U3 C5 VDD VSSQ N3
R10 VDD VSSQ C4 R5 VDD VSSQ R3
D11 VDD VSSQ R4 C10 VDD VSSQ U3
G11 VDD VSSQ F5 R10 VDD VSSQ C4
RV177
L11 VDD VSSQ M5 D11 VDD VSSQ R4
549_0402_1%
P11 VDD VSSQ F10 G11 VDD VSSQ F5
RV219 G14 VDD VSSQ M10 L11 VDD VSSQ M5
1 2 +FBC_VREFD_H L14 VDD VSSQ C11 P11 VDD VSSQ F10
931_0402_1% VDD VSSQ R11 G14 VDD VSSQ M10
VSSQ A12 L14 VDD VSSQ C11
1 VSSQ VDD VSSQ
RV178 C12 R11
VSSQ E12 VSSQ A12
1.33K_0402_1%
VSSQ N12 VSSQ C12
D 2 VSSQ R12 VSSQ E12
2 VSSQ U12 VSSQ N12
170-BALL
<23,28,29,30> MEM_VREF VSSQ H13 VSSQ R12
G
VSSQ K13 VSSQ U12
S QV15 SGRAM GDDR5 170-BALL
VSSQ A14 VSSQ H13
2N7002W -T/R7_SOT323-3
VSSQ C14 VSSQ K13
SGRAM GDDR5
VSSQ E14 VSSQ A14
VSSQ N14 VSSQ C14
VSSQ R14 VSSQ E14
VSSQ U14 VSSQ N14
VSSQ VSSQ R14
+1.5VS_VGA UV10 SIDE VSSQ U14
X76@
VSSQ
+1.5VS_VGA UV9 SIDE H5GQ1H24AFR-T2L_BGA170 X76@
2 1 1 1 1 1 1 1
H5GQ1H24AFR-T2L_BGA170
2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2

1 2 2 2 2 2 2 2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N13P-VRAM C Upper

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 31 of 65
5 4 3 2 1
 5 4 3 2 1

PCIE _CTX_GRX_N[0.. 15]

<23,5> PCIE_CTX_GRX_N[0..15]
11/11 for 2nd VGA fan PCIE _CTX_GRX_ P[0..15]
need to notic EC <23,5> PCIE_CTX_GRX_P[0..15]
PCIE _CRX_ GTX_ N[0..15]
D <23,5> PCIE_CRX_GTX_N[0..15] D
PCIE _CRX_ GTX_ P[0..15]
<23,5> PCIE_CRX_GTX_P[0..15] B+_SLI
follow MXM 3.0 spec

JSLI1

1 2
3 GND GND 4
5 NC GND 6
7 NC GND 8
9 NC GND 10
11 NC +19V 12
13 NC +19V 14
15 NC +19V 16
17 NC +19V 18
19 GND +19V 20
PCIE _CTX_GRX_N15
PCIE _CTX_GRX_ P15 21 PEG_RX_N7 +19V 22
PEG_RX_P7 +19V
23 24
PCIE_CTX_GRX_N14 25 GND +19V 26
PCIE _CTX_GRX_ P14 27 PEG_RX_N6 GND 28 +5VS_SLI
29 PEG_RX_P6 GND 30
31 GND GND 32
33 GND GND 34
PCIE _CTX_GRX_N13
35 PEG_RX_N5 GND 36
PCIE _CTX_GRX_ P13
37 PEG_RX_P5 GND 38
39 GND +5V 40
PCIE _CTX_GRX_N12
PCIE _CTX_GRX_ P12 41 PEG_RX_N4 +5V 42
C 43 PEG_RX_P4 +5V 44 C
PCIE _CTX_GRX_N11 45 GND +5V 46
PCIE_CTX_GRX_P11 47 PEG_RX_N3 +5V 48
49 PEG_RX_P3 GND 50
PCIE _CTX_GRX_N10 51 GND GND 52
PCIE _CTX_GRX_ P10 53 PEG_RX_N2 GND
PEG_RX_P2 +3VS_SLI
55 54
PCIE_CTX_GRX_N9 57 GND NC 56
PCIE _CTX_GRX_ P9 59 PEG_RX_N1 +3V 58
61 PEG_RX_P1 +3V 60 +3VS
63 GND GND 62
PCIE _CTX_GRX_N8
PCIE _CTX_GRX_ P8 65 PEG_RX_N0 NC 64
67 PEG_RX_P0 NC 66 SLI_B+_ON#
GND NC SLI_B+_ON# <52>
69 68 SLI_5V_ON#
GND NC SLI_5V_ON# <52>
PCIE _CRX_ GTX_ N15 0.22U_ 0402_ 10V6K 2 1 SLI@ CV20 PCIE_ CRX_ C_ GTX_ N15 71 70 SUSP#
PEG_TX_N7 NC SUSP# <45,51,55,57>
PCIE _CRX_ GTX_ P15 0.22U_ 0402_ 10V6K 2 1 SLI@ CV22 PCIE_ CRX_ C_ GTX_ P15 73 72
75 PEG_TX_P7 NC 74 SLI_FAN_ SPEED
GND TH_TACH SLI_FAN_SPEED <41,45>
PCIE _CRX_ GTX_ N14 0.22U_ 0402_ 10V6K 2 1 SLI@ CV16 PCIE_ CRX_ C_ GTX_ N14 77 76 SLI_ FAN_ PWM SLI_FAN_PWM <41,45>
PCIE_ CRX_ C_ GTX_ P14 79 PEG_TX_N6 TH_PW N 78
PCIE _CRX_ GTX_ P14 0. 22U_ 0402_ 10V6K 2 1 SLI@ CV18
81 PEG_TX_P6 NC 80
PCIE _CRX_ GTX_ N13 0.22U_ 0402_ 10V6K 2 1 SLI@ CV19 83 GND PEX_STD_SW # 82
PCIE_ CRX_ C_ GTX_ N13 VGA_ AC_ DET_ R
PEG_TX_N5 AC_DC VGA_AC_DET_R <23>
PCIE _CRX_ GTX_ P13 0.22U_ 0402_ 10V6K 2 1 SLI@ CV14 PCIE_ CRX_ C_ GTX_ P13 85 84 S_ DGPU_ PWROK
PEG_TX_P5 PW R_GOOD S_DGPU_PWROK <19>
87 86 S_DGPU_ PWR_ EN#
GND PW R_EN S_DGPU_PWR_EN# <51>
PCIE _CRX_ GTX_ N12 0. 22U_ 0402_ 10V6K 2 1 SLI@ CV15 PCIE_ CRX_ C_ GTX_ N12 89 88 CLK2_ REQ_ GPU#_ R
PEG_TX_N4 CLK_REQ# CLK2_REQ_GPU#_R <15>
PCIE_CRX_GTX_P12 0.22U_0402_10V6K 2 1 SLI@ CV17 PCIE_CRX_C_GTX_P12 91 90 S_NVDD_PWR_EN
PEG_TX_P4 RSVD S_NVDD_PWR_EN <19>
93 92 S_DGPU_ RST
GND RSVD S_DGPU_RST <15,18>
PCIE _CRX_ GTX_ N11 0.22U_ 0402_ 10V6K 2 1 SLI@ CV12 PCIE_ CRX_ C_ GTX_ N11 95 94 SLAVE_ PRESENT#
PEG_TX_N3 NC SLAVE_PRESENT# <19>
PCIE _CRX_ GTX_ P11 0.22U_ 0402_ 10V6K 2 1 SLI@ CV13 PCIE_ CRX_ C_ GTX_ P11 97 96 PCH_ THRMTRIP#_ R
PEG_TX_P3 TH_OVERT# PCH_THRMTRIP#_R <19,23>
99 98 PLT _RST# PLT_RST# <18,23,37,38,44,45,6> 1
PCIE _CRX_ GTX_ N10 0. 22U_ 0402_ 10V6K 2 1 SLI@ CV10 PCIE_ CRX_ C_ GTX_ N10 101 GND NC 100 GC6_ EVENT_ SLI# RV158 1 @ 2 0_0402_5% CV177
PEG_TX_N2 RSVD GC6_EVENT# <19,23 ,45>
PCIE_CRX_GTX_P10 0.22U_0402_10V6K 2 1 SLI@ CV11 PCIE_CRX_C_GTX_P10 103 102 EC_SMB_DA2 0.01U_0402_25V7K
PEG_TX_P2 SMB_DAT EC_SMB_DA2 <15,23,40,45>
B 105 104 EC _SMB_ CK2 Close to SLI connector B
GND SMB_CLK EC_SMB_CK2 <15,23,40,45> 2
PCIE _CRX_ GTX_ N9 0.22U_ 0402_ 10V6K 2 1 SLI@ CV8 PCIE_ CRX_ C_ GTX_ N9 107 106
PCIE _CRX_ GTX_ P9 0.22U_ 0402_ 10V6K 2 1 SLI@ CV9 PCIE_ CRX_ C_ GTX_ P9 109 PEG_TX_N1 WAKE# 108 GC6_ EN
111 PEG_TX_P1 RSVD 110 S_DGPU_ PWR_ EN S_DGPU_PWR_EN <19,51>
0.22U_0402_10V6K 2 1 SLI@ CV6 113 GND RSVD 112
PCIE_CRX_GTX_N8 PCIE_CRX_C_GTX_N8
0.22U_ 0402_ 10V6K 2 1 SLI@ CV7 115 PEG_TX_N0 GND 114
PCIE _CRX_ GTX_ P8 PCIE_ CRX_ C_ GTX_ P8 CLK_ PCIE_ 2VGA#
PEG_TX_P0 CLK_PCIE_N CLK_PCIE_2VGA# <15>
117 116 CLK_PCIE_ 2VGA
GND CLK_PCIE_P CLK_PCIE_2VGA <15>
118
GND
119 120
121 GND GND 122 GC6_EN <27>
GND GND

TE_2199022-1_118P-T ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 2ND VGA CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 32 of 65
 5 4 3 2 1

+3VS_VGA
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
RV92 RV93 RV94 RV121 RV122 STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
45.3K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1% 20K_0402_1%
D
@ @ @ STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0] D

STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

<24> STRAP0 STRAP0
<24> STRAP1 STRAP1 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
<24> STRAP2 STRAP2
<24> STRAP3 STRAP3 STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
STRAP4
<24> STRAP4 CHANGE_GEN3

@ RV95 RV96 RV97

@
RV124 RV125 Resistor Values
Pull-up to
Pull-down to Gnd
SLOT_CLK_CFG
+3VS_VGA
45.3K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
5K 1000 0000 0 GPU and MCH don't share a common reference clock
10K 1001 0001
1 GPU and MCH share a common reference clock (Default)
15K 1010 0010
20K 1011 0011
25K 1100 0100 SUB_VENDOR
30K 1101 0101
0 No VBIOS ROM (Default)
35K 1110 0110
C C
+3VS_VGA
45K 1111 0111 1 BIOS ROM is present

3GIO_PADCFG XCLK_417 USER Straps

RV98 RV99 RV100 3GIO_PADCFG[3:0] 0 277MHz (Default) User[3:0]
4.99K_0402_1% 10K_0402_1% 4.99K_0402_1%
@ @
2012-0418 --> Set BOM 0000 Notebook Default 1 Reserved 1000-1100 Customer defined
structure as Stuff for ALL SKU

<24> ROM_SI ROM _ SI PEX_PLL_EN_TERM PCIE_MAX_SPEED FB_0_BAR_SIZE

<24> ROM_SO ROM_SO
<24> ROM_SCLK ROM _ SCLK 0 Disable (Default) 0 Limit to PCIE Gen1 0 Reserved

1 Enable 1 PCIE Gen 2/3 Capable 1 Reserved

X76 RV101
20K_0402_1% RV102 RV103
X76@ 30K_0402_1%
@
15K_0402_1%
SMBUS_ALT_ADDR VGA_DEVICE 2 256MB (Default)

0 0x9E (Default) 0 3D Device (Class Code 302h) 3 Reserved

B B

1 0x9C (Multi-GPU usage) 1 VGA Device (Default)

X76

GPU FB Memory (GDDR5) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 VRAM X76 VRAM P/N

K4G20325FD-FC04 2G 64Mx32 PD 30K X76409JVL01 (2G 64Mx32) SA00005B70J

Samsung Samsung
K4G10325FG-HC04 1G 32Mx32 PD 45K PU 35K X76409JVL51 (1G 32Mx16) SA00003RS0J
N13P-GT1 PU 10K (ALL SKU) PU 45K PD 5K PD 25K PU 5K PD 45K
28nm EOL
H5GQ2H24MFR-T2C 2G 64Mx32 PD 25K X76409JVL02 (2G 64Mx32) SA00004GD0J EOL

Hynix H5GQ1H24BFR-T2C 1G 32Mx32 PD 20K Hynix X76409JVL02 (2G 64Mx32) SA00004GD1J

A A

H5GQ2H24AFR-T2C 2G 64Mx32 PD 5K X76409JVL52 (1G 32Mx16) SA00003WL1J

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 N14P_MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D Size Document Number Rev

 
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 33 of 65
5 4 3 2 1
 5 4 3 2 1

+LEDVDD B+
2A 80 mil 2A 80 mil

+LCDVDD_CONN
1 R813 2 CMOS Camera +CMOS_PW

+LEDVDD
1 1 R_short 0_0805_5% Q94 AO3413_SOT23-3 R432
JLVDS1ME@ C523 0_0603_5% W=40mils
LVDS_A0#_CONN 1 2 470P_0603_50V8J C524 (40 MIL)
1 2 3 1 +CMOS _PW _ R 1 2
LVDS _A0_ CONN 3 4 4.7U_0805_25V6-K +3VS
3 4 2 2 1 CMOS@ 1
LVDS_A1#_CONN 5 6 9/23 EMI Request
5 6 W=60mils CMOS@ CMOS@
LVDS _A1_ CONN 7 8
7 8 C518
LVDS_A2#_CONN 9 10 1 1
9 10 C1051 CMOS@ C1052 CMOS@ 0.1U_0402_16V4Z
LVDS _A2_ CONN 11 12 2 2 @
11 12 +3VS 0.1U_0402_16V4Z
LVDS _ ACLK#_ CONN 13 14
15 13 14 16 @ 0.01U_0402 _ 16V7K
LVDS _ ACLK _ CONN R822 2 1 4. 7K_ 0402_ 5%
+3VS 1
17 15 16 18 2 2
@
19 17 18 20 DISPOFF# R891 2 1 R _short 0_ 0402_ 5% BKOFF# 680P_0402_50V7K
D 19 20 BKOFF# <45> CMOS@ D
<45> ECR_EN 21 22 INVPW M C528 1 R435 2
23 21 22 24 EDID _DATA _ CONN 2 <45> CMOS_ON#
25 23 24 26 EDID _CLK _ CONN 100K_0402_5% 1
27 25 26 28 C520
27 28 @
29 30 0.1U_0402_16V4Z
29 30
2
31 32
GNDGND

<17> EDID_CLK EDID _ CLK R1210 1 2 EDID _ CLK_ CONN

0_0402_5% OPT@

VGA _ EDID_ CLK R1199 1 2

<23> VGA_EDID_CLK
0_0402_5% SLI@

<17> EDID_DATA EDID _ DATA R1211 1 2 EDID _ DATA_ CONN

0_0402_5% OPT@

<23> VGA_EDID_DATA VGA _ EDID_ DATA R1200 1 2

0_0402_5% SLI@

2 @ 1 R1515
EC_INVT_PW M <45>
0_0402_5%
SLI@
INVPW M 2 1 R824
VGA_BL_PW M <23>
0_0402_5%
C C
OPT@ PCH_PW M <17>
2 1 R847 C58 For RF request
0_0402_5% @
2 1
20120806 --> change to 0-ohm normal symbol
0.047U_0402_16V4Z
20120807 -->
1. R1515 change to "@",
2. R824 change to "SLI@", R847 change to "OPT@" W=40mils JCMOS1
+CMOS_PW 1
USB20 _N0 2 1
<18>
USB20_N0 2
<18>
USB20_P0 USB20_P0 3
4 3
OPT@ 1 R1212 2 +3VS 4
<17> PCH_ENBKL <42> DMIC_CLK 5
0_0402_5% 6 5
For CMOS <42> DMIC_DATA 6
7
SLI@ 1 R1201 2 8 7
<23> VGA_ENBKL ENBKL <45> 8
0_0402_5% 9
R827 10 GND
100K_0402_1% GND

ME@

LVDS _ ACLK# R1255 1 OPT@ 2 0_0402_5% LVDS _ ACLK#_ CONN

<17> LVDS_ACLK# 1 2
LVDS_ACLK R1257 OPT@ 0_0402_5% LVDS_ACLK_CONN
<17> LVDS_ACLK
LVDS _A0# R1259 1 OPT@ 2 0_0402_5% LVDS _ A0#_ CONN
<17> LVDS_A0# LVDS_A0 1 2 LVDS_A0_CONN
R1261 OPT@ 0_0402_5%
<17> LVDS_A0 LVDS _A1# 1 2 LVDS _ A1#_ CONN
PCH R1262 OPT@ 0_0402_5%
<17> LVDS_A1# 1 2
LVDS _A1 R1265 OPT@ 0_0402_5% LVDS _ A1_ CONN
B <17> LVDS_A1 1 2 B
LVDS _A2# R1267 OPT@ 0_0402_5% LVDS _ A2#_ CONN
<17> LVDS_A2# 1 2
LVDS _A2 R1269 OPT@ 0_0402_5% LVDS _ A2_ CONN
<17> LVDS_A2

VGA_TXCLK- R1260 1 SLI@ 2 0_0402_5% LVDS_ACLK#_CONN

<24> VGA_TXCLK- LVDS _ ACLK_ CONN
VGA _ TXCLK+ R1264 1 SLI@ 2 0_0402_5%
<24> VGA_TXCLK+ 1 2 LVDS_A0#_CONN
VGA_TXOUT0- R1263 SLI@ 0_0402_5%
<24> VGA_TXOUT0- 1 2
VGA VGA _ TXOUT0+ R1266 SLI@ 0_0402_5% LVDS _ A0_ CONN
<24> VGA_TXOUT0+ 1 2
VGA _ TXOUT1- R1268 SLI@ 0_0402_5% LVDS _ A1#_ CONN
<24> VGA_TXOUT1-
VGA _ TXOUT1+ R1270 1 SLI@ 2 0_0402_5% LVDS _ A1_ CONN
<24> VGA_TXOUT1+ 1 2 LVDS _ A2#_ CONN
VGA _ TXOUT2- R1271 SLI@ 0_0402_5%
<24> VGA_TXOUT2- 1 2 LVDS _ A2_ CONN
VGA _ TXOUT2+ R1272 SLI@ 0_0402_5%
<24> VGA_TXOUT2+

+LCDVDD_CONN +5VALW +3VS +3VS

LCDVDD EMI request
W=60mils D59 @
R816 R1467 R817 INVPW M USB20_P0 4 1 DMIC_DATA
150_0603_1% 100K_0402_5% @ 100K_0402_5% DMIC _CLK 1
@ 2 I/O3 I/O1
1
C530 R1498 DISPOFF#
0.1U_0402_16V4Z 0_0402_5% 1 C525
1@ 1@ 5 2
2 +3VS VDD GND
@ C527
Q67A R820
2 LCD _ ENVDD# 1 2 2 Q68
2N7002DW -T/R7_SOT363-6 2
AO3413_SOT23-3
100K_0402_5% 2 2 6 3
1 1 USB20 _N0 DMIC _ CLK
A I/O4 I/O2 A
C1050
@ AZC099-04S.R7G_SOT23-6
0.1U_0402_16V4Z +LCDVDD_CONN
2 2
SLI@
R1197 1 2 0 _0402_ 5% 5 W=60mils
<23> VGA_ENVDD Q67B
OPT@ 2 2N7002DW -T/R7_SOT363-6
R1195 1 0 _0402_ 5%
<17> PCH_ENVDD
1 1 Security Classification LC Future Center Secret Data Title
C531 C532
LVDS/ CMOS/ USB-REDRIVER

 
R821 4.7U_0603_6.3V6K 0.1U_0402_16V4Z Issued Date 2011/11/01 Deciphered Date 2012/12/31
100K_0402_5% 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 34 of 65
5 4 3 2 1
 A B C D E

+5VS +5VS +5VS

3 3 3

R1276 1 2 0_ 0402_ 5% 2
1 BLUE

2
1 GREEN

2
1 RED
+5VS
D36
+CRT_VCC
CRT Connector
VGA _ CRT _ R BAT54S-7-F_SOT23-3 F1
<23> VGA_CRT_R
@ @ @ 2 1 1 2 +CRT _ VCC _ CONN
SLI@ D31 D32 D33 1
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 RB491D_SC59-3 0.5A_8V_KMC3S050RY
VGA _ CRT _ G R1273 1 2 0_ 0402_ 5% C536
<23> VGA_CRT_G

1 SLI@
W=40mils 2
0.1U_0402_16V4Z
1

VGA _ CRT _ B R1275 1 2 0_ 0402_ 5%

<23> VGA_CRT_B

SLI@

JCRT1
6
T75 PAD CRT _ TEST 11
DAC _ RED _ 1 L16 1 2 NBQ100505T-800Y _ 0402 RED 1
7
CRT _ DDC _ DAT_ CONN 12
DAC _ GRN _ 1 L17 1 2 NB Q100505T-800Y_ 0402 GREEN 2
8
JVGA _ HS 13
DAC_BLU_1 L18 1 2 N B Q100505T- 8 00Y_0402 BLUE 3
9
1 1 1 1 1 1 JVGA _ VS 14
4
R830 R831 R832 C537 C538 C539 C540 C542 C541 10 G 16
150_0402_1% 150_0402_1% 150_0402_1 % 10P_0402_50V8J 10P_0402_50V8J CRT _ DDC _ CLK_ CONN 15 G 17
2 2 2 2 2 2 5
1
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50 V 8J10P_0402_50V8J C543 SUYIN_070546HR015M22BZR
CLOSE TO CONN
100P_040 2_50V8J
2 ME@

DAC _ RED R1274 1 2 0 _ 0402 _ 5%

<17> DAC_RED
2 OPT@ 2
DAC _ GRN R1181 1 2 0 _ 0402 _ 5% +CRT_VCC
<17> DAC_GRN R833

OPT@ 1 2
DAC _ BLU R1182 1 2 0 _ 0402 _ 5% 1
<17> DAC_BLU
1K_0402_5%
OPT@ C544 OE#
0.1U_0402_16V4Z
2
R840 NBQ100505T-800Y_0402
OPT@
CRT_HSYNC R1183 1 2 0_0402_5% HSYNC_G 2 4 CRT_HSYNC_1 1 2 CRT_HSYNC_2 1 2 JVGA_HS
<17> CRT_HSYNC A Y
L19
33_0603_5%
U24
VGA _ CRT _ HSYNC R1184 1 2 0_ 0402_ 5% SN74AHCT1G125DCKR_SC70-5 1
<23> VGA_CRT_HSYNC
@
D8
SLI@ C545 @
10P_0402_50V8J JVGA _ VS 3 6 JVGA _ HS
+CRT_VCC 2 I/O2 I/O4

1 2 5 +5VS
GND VDD
C546 OE#
0.1U_0402_16V4Z
CRT _VSYNC R1185 1 2 0_ 0402_ 5% 2 CRT _ DDC_ CLK_ CONN 1 4 CRT_ DDC_ DAT_ CONN
<17> CRT_VSYNC I/O1 I/O3
R839 NBQ100505T-800Y_0402
OPT@
2 4 CRT_VSYNC_1 1 2 1 2 AZC099-04S.R7G_SOT23-6
VGA _ CRT _ VSYNC R1186 1 2 0_ 0402_ 5% VSYNC _ G CRT_VSYNC_2 JVGA_ VS
3 <23> VGA_CRT_VSYNC A Y 3
L20
33_0603_5%
SLI@ U25 1
SN74AHCT1G125DCKR_SC70-5
+3VS
@ C547
10P_0402_50V8J
+CRT_VCC 2

R837 R838
2.2K_0402_5%

<17> CRT_DDC_DATA CRT _ DDC _ DATA R1189 1 2 0_ 0402_ 5% CRT _ DDC _ DATA_ R 4 3 CRT_ DDC_ DAT_ CONN
OPT@

Q73B
2N7002KDW H_S OT363-6
<17> CRT_DDC_CLK CRT _ DDC _ CLK R1190 1 2 0_ 0402_ 5% CRT_ DDC_ CLK_ R 1 6 CRT_ DDC_ CLK_ CONN
OPT@ 1 1
@ @
Q73A C548 C549
<23> VGA_CRT_DATA VGA _ CRT _ DATA R1191 1 2 0_ 0402_ 5% 2N7002KDW H_SOT363-6 100P_0402_50V8J 68P_0402_50V8K
SLI@ 2 2

<23> VGA_CRT_CLK VGA _ CRT _ CLK R1192 1 2 0_ 0402_ 5%

SLI@
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 CRT CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 35 of 65
A B C D E
 5 4 3 2 1

+3VS +3VS_VGA
W CM-2012-900T_4P
HDMI_CLK+_CK 4 3 HDMI_CLK+_CONN 1 2
4 3 C1016 3.3P_0402_50V8C
@ R1468 R1469
HDMI_CLK-_CK 1 2 HDMI_CLK-_CONN 1 2
1 2 HDMIDAT _R 0_0402_5% 0_0402_5%
C1015 3.3P_0402_50V8C
L23 HDMICLK _R OPT@ SLI@
@

L24 D57
HDMI _ TX0+ _ CK 1 2 HDMI _ TX0+ _ CONN 1 2 PJSOT24C 3P C/A SOT-23 Q152
1 2 C1018 3.3P_0402_50V8C @ BSH111_SOT23-3
D D
HDMI@
@ VGA _ HDMI_ CLK R1470 1 SLI@ 2 0_0402_5%
HDMI _ TX0- _ CK 4 3 HDMI _ TX0- _ CONN 1 2 <24> VGA_HDMI_CLK
4 3 C1017 3.3P_0402_50V8C
W CM-2012-900T_4P <17> HDMICLK HDMICLK R1471 1 OPT@ 2 0 _ 0402 _ 5% 3 1 HDMICLK _ R
@
W CM-2012-900T_4P
HDMI _ TX1+ _ CK 4 3 HDMI_TX1+_CONN 1 2 VGA_HDMI_DATA R1472 1 SLI@ 2 0_0402_5%
4 3 <24> VGA_HDMI_DATA
C1020 3.3P_0402_50V8C
@ <17> HDMIDAT
HDMIDAT R1473 1 OPT@ 2 0_0402 _5% 3 1 HDMIDAT _ R
HDMI _ TX1- _ CK 1 2 HDMI_TX1-_CONN 1 2
1 2 C1019 3.3P_0402_50V8C
L26 Q80
@
+3VS BSH111_SOT23-3
L27 HDMI@
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN 1 2 +5VS
1 2 C1022 3.3P_0402_50V8C
@
HDMI _ TX2- _ CK 4 3 HDMI _ TX2-_ CONN 1 2
4 3 C1021 3.3P_0402_50V8C R862 +5VS PMEG2010AEH
1M_0402_5%
W CM-2012-900T_4P @ IF=0.1A, 0.29V HDMI@

Q85 IF=1A, 0.43V D37

PMEG2010AEH_SOD123
R1486 1 OPT@ 2 3 1
<17> TMDS_B_HPD
0_0402_5%
2N7002_SOT23
R885 @
20K_0402_5% D38 F2 HDMI@
C BAT54S-7-F_SOT23-3 0.5A_8V_KMC3S050RY C
R320
499_0402_1%
HDMI _ CLK+ _ CONN SLI@ 1 2
R1499 +5VS _ HDMI
HDMI _ CLK- _ CONN SLI@ 1 2 0_0402_5%
R321 499_0402_1%
SLI@ SLI@ 1 C561
HDMI _ TX0+ _ CONN 1 2
R322 499_0402_1%
for NV recommend 0.1U_0402_16V4Z
HDMI@
HDMI _ TX0- _ CONN SLI@ 1 2 L67
R323 499_0402_1% R860 R861 2
BLM18PG181SN1D_0603
HDMI_TX1+_CONN SLI@ 1 2 @ 2.2K_0402_5% 2.2K_040 2 _5%
R859 2 1 HDMI_DET_R 2 1
R324 499_0402_1% <23> DGPU_HDMI_HPD @ HDMI@ HDMI@
HDMI _ TX1- _ CONN SLI@ 1 2 1K_0402_5%
R325 499_0402_1%
HDMI _ TX2+ _ CONN SLI@ 1 2 1
R326 499_0402_1% @
SLI@ C59
HDMI _ TX2- _ CONN 1 2 JHDMI1
220P_0 4 02_25V8J
R327 499_0402_1%
D 2 HDMI _ DET 19
18 HP_DET
2 Q114 17 +5V
+3VS
G 2N7002H 1N_SOT23-3 HDMIDAT _R 16 DDC/CEC_GND
S HDMI@ HDMICLK _R 15 SDA
1 @ 2 14 SCL
R328 100K_0402_5% 13 Reserved
VGA _ HDMI_ CLK- SLI@ CV254 1 2 0.1U_0402_10V6KHDMI_CLK-_CK R866 1 @ 2 0_ 0402_ 5% HDMI _ CLK-_ CONN 12 CEC 20
<24> VGA_HDMI_CLK- CK- GND
11 21
VGA _ HDMI_ CLK+ SLI@ CV253 1 2 0.1U_0402_10V6KHDMI_CLK+_CK R865 1 @ 2 0_ 0402_ 5% HDMI _ CLK+_ CONN 10 CK_shield GND 22
<24> VGA_HDMI_CLK+ CK+ GND
VGA _ HDMI_ TX0- SLI@ CV256 1 2 0.1U_0402_10V6KHDMI_TX0-_CK R868 1 @ 2 0_ 0402_ 5% HDMI _ TX0-_ CONN 9 23
B <24> VGA_HDMI_TX0- D0- GND B
R327 R326 8
VGA _ HDMI_ TX0+ SLI@ CV255 1 2 0.1U_0402_10V6KHDMI_TX0+_CK R867 1 @ 2 0_ 0402_ 5% HDMI _ TX0+_ CONN 7 D0_shield
<24> VGA_HDMI_TX0+ D0+
VGA _ HDMI_ TX1- SLI@ CV258 1 2 0.1U_0402_10V6KHDMI_TX1-_CK R870 1 @ 2 0_ 0402_ 5% HDMI _ TX1-_ CONN 6
<24> VGA_HDMI_TX1- D1-
5
VGA _ HDMI_ TX1+ SLI@ CV257 1 2 0.1U_0402_10V6KHDMI_TX1+_CK R869 1 @ 2 0_ 0402_ 5% HDMI _ TX1+_ CONN 4 D1_shield
<24> VGA_HDMI_TX1+ D1+
VGA _ HDMI_ TX2- SLI@ CV260 1 2 0.1U_0402_10V6KHDMI_TX2-_CK R872 1 @ 2 0_ 0402_ 5% HDMI _ TX2-_ CONN 3
<24> VGA_HDMI_TX2- D2-
680_0402_1% 680_0402_1% 2
VGA_HDMI_TX2+ SLI@ CV259 1 2 0.1U_0402_10V6KHDMI_TX2+_CK R871 1 @ 2 0_0402_5% HDMI_TX2+_CONN 1 D2_shield
OPT@ OPT@ <24> VGA_HDMI_TX2+ D2+
R324 R323 TAITW _PDVBR0-19FLBS4NN4N0
ME@

680_0402_1% 680_0402_1%
OPT@ OPT@

R321 R320

TMDS _ B _ DATA2# _ PCH OPT@ C200 1 2 0.1U _ 0402_ 10V6K HDMI _ TX2-_ CK
<17> TMDS_B_DATA2#_PCH @
<17> TMDS_B_DATA2_PCH
TMDS _ B _ DATA2 _ PCH OPT@ C201 1 2 0.1U _ 0402_ 10V6K HDMI _ TX2+_ CK
<17> TMDS_B_DATA1#_PCH
TMDS _ B _ DATA1# _ PCH OPT@ C203 1 2 0.1U _ 0402_ 10V6K HDMI _ TX1-_ CK
680_0402_1% 680_0402_1% TMDS _ B _ DATA1 _ PCH OPT@ C206 1 2 0.1U _ 0402_ 10V6K HDMI _ TX1+_ CK
OPT@ OPT@ <17> TMDS_B_DATA1_PCH 46@
<17> TMDS_B_DATA0#_PCH
TMDS _ B _ DATA0# _ PCH OPT@ C204 1 2 0.1U _ 0402_ 10V6K HDMI _ TX0-_ CK
<17> TMDS_B_DATA0_PCH
TMDS _ B _ DATA0 _ PCH OPT@ C205 1 2 0.1U _ 0402_ 10V6K HDMI _ TX0+_ CK
R325 R322 TMDS _ B _ CLK# _ PCH OPT@ C208 1 2 0.1U _ 0402_ 10V6K HDMI_ CLK-_ CK
<17> TMDS_B_CLK#_PCH W/LOGO
A TMDS _B _ CLK _ PCH OPT@ C207 1 2 0.1U _ 0402_ 10V6K HDMI_ CLK+_ CK A
<17> TMDS_B_CLK_PCH
HDMI W/O Logo: RO0000001HM

680_0402_1% 680_0402_1%
OPT@ OPT@ Title
Security Classification
2011/11/01 Deciphered Date 2012/12/31 HDMI CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 36 of 65
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX) 9/18 JP1 Pin2,24,52 contact to +3VS_WLAN for AOAC function
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
+3VS_WLAN LPC_FRAME#_R R873 1 @ 2 0_0402_5% LPC_FRAME#
LPC_FRAME# <14,45>
LPC_AD3_R R874 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 <14,45>
LPC_AD2_R R875 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 <14,45>
LPC_AD1_R R876 1 @ 2 0_0402_5% LPC_AD1
+1.5VS +1.5VS LPC_AD1 <14,45>
LPC_AD0_R R878 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <14,45>
PCI_RST#_R R879 1 @ 2 0_0402_5% PLT_RST#
1 CLK _ PCI _ DB
CLK_PCI_DB <18>
1 1

@ R400 C564 C565

1 2 1
R_short 0_0603_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
R1620 1 @ 2 0_0402_5%
<38,45> LAN_WAKE#
JWLN1
PCIE_W AKE# 1 2
<16,19,38> PCIE_WAKE# WAKE# 3.3V
3 4
R897 NC GND
BT _ CTRL COMBT@ 1 2 BT _ CTRL _ R 5 6 +1.5VS_ W LAN
NC 1.5V
WLAN_CLKREQ1# 7 8 LPC _ FRAME# _ R
0_0402_5% <15> WLAN_CLKREQ1# CLKREQ# NC
9 10 LPC _ AD3 _ R
GND NC
11 12 LPC _ AD2 _ R
R1556 <15> CLK_PCIE_WLAN1# REFCLK- NC
COMBT@ 1 2 BT _ D ISABLE# 13 14 LPC _ AD1_ R
<15> CLK_PCIE_WLAN1 REFCLK+ NC
15 16 LPC _ AD0 _ R
1K_0402_5% GND NC
PCI _ RST# _ R 17 18 R1541 2 @ 1 0_0402_5%
NC GND EC_W L_OFF# <45>
For isolate Intel CLK _ PCI _ DB 19
NC NC
20 WL_ OFF# R880 1 2 0 _ 0402_ 5%
PCH_W L_OFF# <18>
21 22 PLT _ RST#
Rainbow Peak and 23 GND PERST# 24 R881 1 @ 2 0_0402_5%
PLT_RST# <18,23,32,38,44,45,6>
+3VALW
Compal debug card. <15>
<15>
PCIE_PRX_D TX_N2
PCIE_PRX_D TX_P2
25 PERn0
PERp0
+3.3Vaux
GND
26 R882 1 2 0 _0402 _5%
+3VS_WLAN
27 28
29 GND +1.5V 30 SMB _ CLK _ S3_ R R883 1 @ 2 0_0402_5%
GND SMB_CLK SMB_CLK_S3 <12,13,15,46>
31 32 SMB _ DATA _ S3_ R R884 1 @ 2 0_0402_5%
<15> PCIE_PTX_C_DRX_N2 PETn0 SMB_DATA SMB_DATA_S3 <12,13,15,46>
33 34
<15> PCIE_PTX_C_DRX_P2 PETp0 GND
35 36 +3VS +3VS_W LAN
+3VS_W LAN GND USB_D- USB20_N10 <18>
37 38
NC USB_D+ USB20_P10 <18>
39 40 J8
41 NC GND 42
NC LED_W W AN# 1 2
43 44 1 2
45 NC LED_W LAN# 46
100_0402_1%
47 NC LED_W PAN# 48
R887 JUMP_43X79
EC _ TX 1 2 49 NC +1.5V 50
<45> EC_TX NC GND +3VALW
EC _ RX 1 2 BT _ DISABLE# 51 52 Q104
<45> EC_RX NC +3.3V
R888 AO3413_SOT23-3
100_0402_1% 53 54
GND GND 3 1 1
AOAC@
1 C533
TAITW_PFPET0-AFGLBG1ZZ4N0 AOAC@ AOAC@ 1 0.1U_0402_16V4Z
C526 2
For EC to detect ME@ 0.1U_0402_16V4Z
C1048
R889 2 0.01U_0402_25V7K
2
debug card insert. 100K_0402_5% AOAC@
AOA C@
2
2

R436
1 2 1
<51> AOAC_ON#
@
100K_0402_5%
C1055
0.1U_0402_16V4Z
2

softstart (RC) will check on EVT PCB

R1557 COMBT@ 2
<19> PCH_BT_DISABLE# 1 BT _ CTRL
0_0402_5% WLAN&BT Combo module circuits
D D BT on module BT on module 9/18 Increase for Intel AOAC function
<19,47> PCH_BT_ON# 2 5 SUSP <10,51,55,57> Enable Disable
G G

@
S S
@
* BT_CRTL (GPIO22) H L
PCH_BT_ON# L H

3 3

Mini-Express Card(SSD)
SSD Active:4.5W(1.5A)
+3VS_SSD
+3VS +3VS_SSD
0.1U _ 0402_ 16V4Z 10U_0805_10V6K
J5

1 1 1 1 1 2
@ 1 2
C566 C567 C568 C569
JUMP_43X79
2 2 2 2 @
JSSD1
0.01U_0402_25V7K 10U _0805_10V6K 1 2
3 WAKE# 3.3V 4
5 NC GND 6
7 NC 1.5V 8
9 CLKREQ# NC 10
11 GND NC 12
13 REFCLK- NC 14
15 REFCLK+ NC 16
17 GND NC 18
19 NC GND 20
21 NC NC 22
0.01U_0402_16V7K
23 GND PERST# 24
SATA _DTX _C _ IRX_ P0 2 1 C572 SATA _ DTX _ IRX_ P0
<14> SATA_DTX_C_IRX_P0 25 PERn0 +3.3Vaux 26
SATA _DTX _C _ IRX_ N0 2 1 C573 SATA _ DTX _ IRX_ N0
<14> SATA_DTX_C_IRX_N0 27 PERp0 GND 28
29 GND +1.5V 30
0.01U_0402_16V7K
SATA _ITX _ DRX_ N0 31 GND SMB_CLK 32
<14> SATA_ITX_DRX_N0 PETn0 SMB_DATA
SATA _ITX _ DRX_ P0 33 34
<14> SATA_ITX_DRX_P0 PETp0 GND
4 35 36 4
37 GND USB_D- 38
+3VS_SSD 39 NC USB_D+ 40
41 NC GND 42
43 NC LED_W W AN# 44
45 NC LED_W LAN# 46
47 NC LED_WPAN# 48
NC +1.5V 50
49
SATA_DET# 1 2 51 NC GND 52
<14> SATA_DET# NC +3.3V
R896 0_0402_5%
For SSD use: @ 53 54
Security Classification LC Future Center Secret Data Title

 
GND GND

TAITW_PFPET0-AFGLBG1ZZ4N0
Issued Date 2011/11/01 Deciphered Date 2012/12/31 MINI-CARD CONN.
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
ME@
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , March 11 , 2013 Sheet 37 of 65
A B C D E
 5 4 3 2 1

+3VALW +3V_LAN
Atheros request can't disable LAN power +LX
LX Voltage Configure
J10 <Pin 40>
1 2
Close together
Layout Notice : Place as close 1 2 +1.7V
+1.7_VDDCT
chip as possible.
JUMP_43X79
AR8151 <VDDCT> R1356,C955
R1356 8151@ 0_0402_5% L74

Q70 LP2301ALT1G_SOT-23
1 2 +LX _R 1 2 +LX +1.1V
4.7UH_SIA4012-4R7M_20% AR8161 <DVDDL,AVDDL> R1357,R1372,L76
R1357 8161@ 0_0402_5% 1 1
3 1 +1.1 _DVDDL 1 2
Note: Place Close to LAN chip L75 L76
1 1
C552 C1047 2 2 L39 DCR< 0.15 ohm FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
D
0.1U_0402_16V4Z 0.01U_0402_25V7K Rate current > 1A +1.1_AVDDL_L 1 2 +1.1_AVDDL 1 2 +1.1_DVDDL
D

2 2
R59 8161@
<45> LAN_PW R_ON#
LAN_PW R_ON# 2 1 Close to 1 1 1
100K_0402_5% 1 Pin40
@ C1056
0.1U_0402_16V4Z 2 2 2
2
20120806 -->
1. Main source was EOL, P/N : SHI0000740J
Vendor recommand reseve the 2. Change L74 P/N to "SH00000GT0J" (has used on SIT by SMT Memo)
Place close to Pin34
PU resistor close LAN chip

+3V_LAN R345 1 @ 2 4.7K_0402_5%

PLT _ RST#
<18,23,32,37,44,45,6> PLT_RST#

H --> Overclocking mode

Place Close to Chip U63 8161@
L --> Not overclocking mode
C C946 1 2 0.1U _0402_ 16V7K PCIE _PRX _ C_ DTX_ N1 29 38 ACTIVITY# C
<15> PCIE_PRX_DTX_N1 TX_N LED_0 ACTIVITY# <39>
C947 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1
39
23
LAN_LINK #
LAN_CLK_SEL 2 @ 1
LAN_LINK# <39>
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161 R58 10K_0402_5% 2 011103 for vendor comment
36
<15> PCIE_PTX_C_DRX_N1 RX_N 12 MDI0-
TRXN0 MDI0- <39>
<15> PCIE_PTX_C_DRX_P1
35
RX_P TRXP0
11
15
MDI0+
MDI1-
MDI0+ <39> Place Close to LAN chip
32 TRXN1 MDI1- <39>
14 MDI1+
<15> CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ <39>
33 18 MDI2-
<15> CLK_PCIE_LAN REFCLK_P TRXN2 MDI2- <39>
17 MDI2+ MDI0+ R1358 1 8151@ 2 49.9_0402_1% 1 @ 2 C938 1000P _ 0402_ 50V7K
TRXP2 MDI2+ <39>
PLT _ RST# 2 21 MDI3-
PERST# TRXN3 MDI3- <39>
R1369 1 2 0 _0402_ 5% PCIE_ W AKE#_ R 3 TRXP3
20 MDI3+
MDI3+ <39> Place Close to PIN1 MDI0- R1359 1 8151@ 2 49.9_0402_1% 1 2 8151@ C939 0.1U _0402 _16V4Z
<16,19,37> PCIE_W AKE# W AKE# MDI1+ R1360 1 8151@ 2 49.9_0402_1% 1 @ 2 C940 1000P _ 0402_ 50V7K
R1370 1 @ 2 0_0402_5% 25 10 LAN _RBIAS 1 2 +3V_LAN
<37,45> LAN_W AKE# SMCLK RBIAS
26 R1371 2.37K _ 0402_ 1% MDI1- R1361 1 8151@ 2 49.9_0402_1% 1 2 8151@ C941 0.1U _0402 _ 16V4Z
SMDATA
Place Close to PIN10
20120718 --> for LAN wakeup backlight issue 28
NC VDD33
1 +3V _ LAN MDI2+ R1362 1 8151@ 2 49.9_0402_1% 1 @ 2 C942 1000P _ 0402_ 50V7K
27
1. R1369 to "Mount" TESTMODE 1 1 1 1
MDI2- R1363 1 8151@ 2 49.9_0402_1% 1 2 8151@ C943 0 .1U _0402 _16V4Z
2. R1370 ro "@" 40 +LX @
LX +LX
LAN_XTALO 7 R1372 1 8161@ 2 30K_0402_5% MDI3+ R1364 1 8151@ 2 49.9_0402_1% 1 @ 2 C944 1000P _ 0402_ 50V7K
8 XTLO +3VS 2 2 2 2
LAN _ XTALI
XTLI 5 +1.7 _ VDDCT MDI3-
C955 1 2 0.1U _ 0402_ 16V4Z R1365 1 8151@ 2 49.9_0402_1% 1 2 8151@ C945 0.1U _0402 _ 16V4Z
VDDCT/ISOLAN 8151@
4
<15> CLKREQ_LAN# CLKREQ# 24 +1.1 _DVDDL _R +1.1_DVDDL
R1366 1 8151@ 2 0_0402_5%
DVDDL/PPS 37
DVDDL_REG/DVDDL
B
+1.1 _ AVDDL 13
AVDDL
+1.1_ DVDDL Note : C938, C940, C942, 944, reserved for EMI. B
+1.1_AVDDL 19
AVDDL
+1.1 _ AVDDL 31
AVDDL AVDDH/AVDD33
16 +AVDDH _ AVDD3.3 For AR8151: Stuff 49.9K and 0.1u
+1.1 _AVDDL _L 34 22 +2.7_ AVDDH
+1.1 _ AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
For AR8161: NC
AVDDL_REG/AVDDL AVDDH_REG
1 1 1 1 1
41 1 1 1
GND +3V_LAN
1 1 2
AR8161-AL3A-R_QFN40_5X5
2 2 2 2 2 8151@ +2.7_AVDDH
2 2 2 8161@
U63 R1367 1 2 0 _0402_ 5%
2 2 1

8151@ 2
8151@ For AR8151: Stuff C966,R1366 +AVDDH _ AVDD3.3 R1368 1 0_ 0402_ 5% +2.7_ AVDDH
For AR8161: NC
Near Near Near Near
Near Near Near Near SA00003LE20 Pin9 Pin22 Pin37 Pin24
Pin13 Pin19 Pin31 Pin6
1 1

8161@
2 2
LAN _ XTALI
Y6
LAN IC X76 VRAM P/N
Place close to Pin16
1 3 LAN _ XTALO
1 3
GND GND 8161 X76409JVL04 SA000050E1J
A For AR8151: Stuff R1368 for +AVDD3.3 A
1
2 4
1 For AR8161: Stuff R1367,C949 for +AVDDH
C968 25MHZ_10PF_7V25000014 C969 8151 X76409JVL03 SA00003LE2J
15P_0402_50V8J
2 2
15P_0402_50V8J No use
Security Classification LC Future Center Secret Data Title
20120816 --->
1. change P/N to 7V2500014(10pf), SJ10000E80J Issued Date 2011/11/01 Deciphered Date 2012/12/31 LAN-AR8151/8161
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, March 11, 2013 Sheet 38 of 65
5 4 3 2 1
 5 4 3 2 1

LAN Transformer
+1.7_VDDCT
T49
2 8151@ 1 1 24 2 R1374 1
+1.7_VDDCT_R MCT3
TCT1 MCT1
R1373 1 2 R_short 0_0402_5% If vendor test result is "ok", need to change as below
MDI3+ 2 1:1 23 MDO3+
0_0603_5% C976 C970 <38> MDI3+ TD1+ MX1+ 1. Change R1374,R1375,R1376,R1377 to 0 ohm
@ 8151@
1U_0402_6.3V4Z 0.1U_0402_16V4Z 2. Change R1194 to 75 ohm
D D
2 1 3. Mount F6
4. Un mount F3,F4,F5
MDI3- 3 22 MDO3- --> 2012/02/20 : already implement to Sch
<38> MDI3- TD1- MX1-
6/23 update
4 21 MCT2 2 R1375 1
TCT2 MCT2
2 R_short 0_0402_5%
MDI2+ 5 1:1 20 MDO2+
8151@ C972 <38> MDI2+ TD2+ MX2+ BOM option:
0.1U_0402_16V4Z 1. For GDTx4
1 R1374/R1375/R1376/R1377=75 ohm
R1194=0 ohm
<38> MDI2-
MDI2- 6 19 MDO2- MCT0~3=Mount
TD2- MX2-
7 18 MCT1 2 R1377 1 2. For GDTx1
TCT3 MCT3
2 R_short 0_0402_5% R1374/R1375/R1376/R1377=0 ohm
C970 C972 MDI1+ 8 1:1 17 MDO1+ R1194=75 ohm
C974 <38> MDI1+ TD3+ MX3+
8151@ MCT0=Mount
0.1U_0402_16V4Z
8161S@ 8161S@ 1 MCT1~3=Mount

MDI1- 9 16 MDO1-
<38> MDI1- TD3- MX3-
0.1U_0402_16V4Z 0.1U_0402_16V4Z
10 15 MCT0 2 R1376 1
TCT4 MCT4
2 R_short 0_0402_5%
MDI0+ 11 1:1 14 MDO0+
C975 <38> MDI0+ TD4+ MX4+
C974 C975 8151@
0.1U_0402_16V4Z
1 R1194
8161S@ 8161S@ 75_0402_5%
MDI0- 12 13 MDO0-
<38> MDI0- TD4- MX4-
1
C 0.1U_0402_16V4Z 0.1U_0402_16V4Z Place close to T49(TCT) pin NS892402 1G C
C973
10P_1206_2KV7K
2

Place Close to T49 Place Close to T49

LAN Conn.
D68 8151S@
MDI2- 1 10 MCT3
2 1 10 9 MDI3+ JRJ1 ME@
MDI2+ 3 2 9 8 MCT2 LAN _ LINK# 9
B 4 3 8 7 <38> LAN_LINK# Green LED- B
MDI3-
5 4 7 6 2 R1378 1 10
MCT1 1 +3V_LAN
5 6 Green LED+
MCT0 220_0402_5% MDO0+ 1
C978 @
TCLAMP3302N.TCT_SLP2626P10-10 470P_0402_50V7K PR1+
R02 2 MDO0- 2
PR1-
MDO1+ 3
PR2+
@ @ @
MDO2+ 4
PR3+
MDO2- 5
PR3-
MDO1- 6
PR2-
MDO3+ 7 14
D67 8151S@ PR4+ G2
MDI0- 1 10 MDO3- 8 13
2 1 10 9 MDI1+ PR4- G1
MDI0+ 3 2 9 8 ACTIVITY# 11
4 3 8 7 MDI1- <38> ACTIVITY# Yellow LED-
4 7 6 2 R1442 1
5 1 12
5 6 +3V_LAN Yellow LED+
Reserve for EMI go rural solution 220_0402_5%
C979 @ SANTA_130456-111
TCLAMP3302N.TCT_SLP2626P10-10 470P_0402_50V7K
R02 2
2012-0622 -->
1. Change the BOM Structure of LAN SURGE to "@" --> F3, F4, F5
Reserve D67,D68 for EMI go rural solution 2. Del SURGE@ on Y400 BOM, and change the BOM structure of F6 to "Stuff"
20120807 -->
A 1. Change Lan Surge P/N to "SCV00001F0J" to meet DC400V Lenovo spec A

2. Only change P/N(F3,F4,F5 and F6), not used correct symbol.

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 LAN TRANSFORMER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 39 of 65
5 4 3 2 1
 5 4 3 2 1

D
Close U29 SMSC thermal sensor D

REMOTE1+
1
+3VS
placed near by VRAM REMOTE1+
Under VRAM
C449 1
2200P_0402_50V7K U29 @ C
2 2
REMOTE1- Remove +VDD netname C982
B
Q137
100P_0402_50V8J MMST3904-7-F_SOT323-3
1 10 EC _ SMB _ CK2 2 E
VDD SMCLK EC_SMB_CK2 <15,23,32,45>
REMOTE1-
REMOTE1+ 2 9 EC _ SMB _ DA2
REMOTE2+
DP1 SMDATA EC_SMB_DA2 <15,23,32,45>
2
1 REMOTE1- 3 8
DN1 ALERT# R624
C443
C658
2200P_0402_50V7K 1
0.1U_0402_16V4Z REMOTE2+ 4
DP2 THERM#
7 2 1 +3VS Close to SSD side
2 REMOTE2- REMOTE2- 5 6 REMOTE2+
DN2 GND 10K_0402_5%
1
@ @ C
C984 2 Q138
B
FAN_PWM & TACH EMC1403-2-AIZL-TR_MSOP10 100P_0402_50V8J
2 E
MMST3904-7-F_SOT323-3

for PWM FAN Address 1001_101xb REMOTE2-

REMOTE2+/-:
C
internal pull up 1.2K to 1.5V Trace width/space:10/10 mil C
R for initial thermal Trace length:<8"
shutdown temp

B B

FAN1 Conn
+5VS

JFAN1
1
2 1
2 1 <45> EC_FAN_SPEED 2
<45> EC_FAN_PW M
3
C986 C49 @ 4 3
10U_0805_10V6K 0.1U_0402_10V7K 5 4
1 2 6 G5
G6
ACES_85205-04001
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 EMC THERMAL SENSOR/FAN CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 40 of 65
5 4 3 2 1
 A B C D E F G H

1
SATA ODD Conn. 1

SATA HDD Conn.

JHDD1 ME@ JODD2 ME@

1 1
SATA _ITX_ DRX_ P1 2 GND SATA_ ITX_ DRX_ P2_ CONN 2 GND
<14> SATA_ITX_DRX_P1 A+ <14> SATA_ITX_DRX_P2_CONN A+
SATA _ITX_ DRX_ N1 3 SATA_ ITX_ DRX_ N2_ CONN 3
<14> SATA_ITX_DRX_N1 A- <14> SATA_ITX_DRX_N2_CONN A-
4 4
SATA _DTX_ C_ IRX_ N1 C627 1 2 0.01U_ 0402_ 16V7K SATA_ DTX_ IRX_ N1 5 GND SATA_ DTX_ C_ IRX_ N2 C629 1 2 0.01U_ 0402_ 16V7K SATA_ DTX_ IRX
_ N2 5 GND
<14> SATA_DTX_C_IRX_N1 SATA _DTX_ C_ IRX_ P1 C628 1 2 0. 01U_ 0402_ 16V7K SATA_ DTX_ IRX_ P1 6 B- <14> SATA_DTX_C_IRX_N2 SATA_ DTX_ C_ IRX_ P2 6 B-
C630 1 2 0. 01U_ 0402
_ 16V7K SATA_ DTX_ IRX
_ P2
<14> SATA_DTX_C_IRX_P1 7 B+ <14> SATA_DTX_C_IRX_P2 7 B+
GND R1479 1 2 R _short 0_ 0402_ 5% GND
<32,45> SLI_FAN_SPEED
<19> ODD_DETECT# R1476 1 @ 2 0 _0402_ 5%
R710 1 @ 2 0 _0402_ 5% 8
8 9 DP
9 VCC3.3 10 +5V
10 VCC3.3 +5VS_ODD 11 +5V
11 VCC3.3 12 MD 15
12 GND R921 1 2 10K _0402 _ 5% ODD_ DA# 13 GND GND 14
GND +3VS GND GND
@ J12 13
1 2 +5VS _ HDD 14 GND R1497 1 @ 2 0_0402_5%
+5VS 1 2 15 VCC5 <18> ODD_DA#_R R1494 1 2 R _short 0 _0402_ 5% SANTA_202404-1
16 VCC5 <32,45> SLI_FAN_PWM
JUMP_43X79
17 VCC5
18 GND
19 RESERVED
+5VS 20 GND
21 VCC12
22 VCC12
2 VCC12 2
1 1 1 1 1
23
C631 C632 C633 C634 C635 24 GND
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0603_6.3V6M 10U_0603_6.3V6M GND
2 2 2 2 2 SANTA_190302-1

ODD Power Control

@ J6
1 2
1 2
JUMP_43X79
+5VALW +5VS +5VS_ODD +5VS_ODD
Q88 AO3413_SOT23-3 AO3413
3 VGS= -4.5V, Id=-3A, Rds<97m ohm 3
3 1

R923 R1496 1 2 1 1 R1477 @

100K_0402_5% @ 100K_0402_5% C1049 C638 C639 C637 470_0603_5%
0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0603_6.3V6M 0.1U_0402_16V4Z
2 1 2 2
2 R1110 1 ODD _EN#
100K_0402_5% D
2
C1057 ODD _EN# 5 Q89B
D @ 0.01U_0402_16V7K G 2N7002KDW H_SOT363-6
2
<19> ODD_EN 1
G Q89A S
2N7002KDW H_SOT363-6
S
R1478
100K_0402_5%

4 4

Security Classification LC Future Center Secret Data Title

HDD/ODD CONN.

 
Issued Date 2011/11/01 Deciphered Date 2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 41 of 65
A B C D E F G H
 A B C D E F G H

LA1 +5VS_AVDD +3VS +3VS_DVDD

1 2 +5VS _ AVDD
+5VS RA7
FBMA-L11160808601LMA10T_2P 1 2 +3VS _ DVDD
R_short 0_0603_5%
600ohms @100MHz 1A 1 1
P/N: SM01000BU00 1 1

1 2 2 1
2 2

Place near UA8.Pin25

Place near UA8.Pin1

+3VS_DVDD +3VS_DVDDIO
+5VS_AVDD
RA6
Place near UA8.Pin39, Pin46 1 2 +3VS _ DVDDIO

1 RA5 2 FBMA-10-100505-101T 0402

+5VS_PVDD +5VS_AVDD 1 1
+5VS
R_short 0_0805_5% P/N: SM01000DI0J

2 1 1 1 2 20120813 --> RA6 symbol

2 2
600ohms @100MHz 2A from R_short to Bead @ @
P/N: SM01000EE00 symbol
1 2 2 2 1
Place near UA8.Pin1

11/07 -->
UA8 Place near UA8.Pin38 Change CA17 type to 0603

2012-0418 --> Channge EAPD netname to EAPD# 30 mils

EAPD# 47 24 SPKOUT _ R1
<43> EAPD# DAPD/COMB_JACK LINE1-R(PORT-C-R) SPKOUT_R1 <43>
2 4 23 SPKOUT _ L1
External SPK (One Channel) 2
PD# LINE1-L(PORT-C-L) SPKOUT_L1 <43>
HDA _ SDOUT_ AUDIO 5 22 C_ MIC2 CA12 77 2 1 2.2U_ 0603_ 6.3V6K MIC2_ R
<14> HDA_SDOUT_AUDIO SDATA-OUT MIC1-R(PORT-B-R) MIC2_R <49>
HDA _ BITCLK_ AUDIO 6 21 MIC1_ R
Ext. MIC
C_ MIC1 CA12 76 2 1 2. 2U_ 0603_ 6. 3V6K
+3VS <14> HDA_BITCLK_AUDIO BIT-CLK MIC1-L(PORT-B-L) MIC1_R <49>
HDA _ SDIN0 2 RA1637 1 HDA_ SDIN0_ R 8 17 10 mils
<14> HDA_SDIN0 SDATA-IN MIC2-R(PORT-F-R)
22_0402_5%
16
RA475 MIC2-L(PORT-F-L)
@ 4.7K_0402_5% HDA_SYNC_AUDIO 10 15
<14> HDA_SYNC_AUDIO SYNC LINE2-R(PORT-E-R)
HDA_RST_AUDIO# HDA_RST_AUDIO# 11 14
<14> HDA_RST_AUDIO# RESET# LINE2-L(PORT-E-L)
PC_BEEP 12
PCBEEP
@ CA1368 40
100P_0402_50V8J~N 2 RA1640 1 JDREF 19 SPK-OUT-L+
MIC Sense --> RA1639 place near pin13 JDREF 41
Capless HP Sense --> RA1638 place near pin34 20K_0402_1% 20 SPK-OUT-L-
MONO-OUT(PORT-H) 44
MIC _JD RA1639 2 1 20K _ 0402_ 1% SENSEA 13 SPK-OUT-R-
<49> MIC_JD Sense A 45
PLUG_IN 18 SPK-OUT-R+
<49> PLUG_IN RA1638 2 1 39.2K _0402 _ 1%
Sense-B 10 mils
1 2 CBN 35 33 HPOUTR_R R3 2 1 75 _0402 _ 5% HP_OUTR
CBN HPOUT-R(PORT-A-R) HP_OUTR <49>
CA1288 2.2U_0603_6.3V6K HeadPhone
CBP 36 32 HPOUTL_R R4 2 1 75 _0402 _ 5% HP_OUTL
CBP HPOUT-L(PORT-A-L) HP_OUTL <49>
2 1 CPVEE 34 48 SPDIF R945 1 2 SPDIF_OUT
CA19 2.2U_0603_6.3V6K CPVEE SPDIF-OUT SPDIF_OUT <49> SPDIF
FBMA-10-100505-301T_2P
2 1 LDO _ CAP 28 EMI Request
3 CA20 4.7U_0603_6.3V6K LDO-CAP 3 DMIC _CLK_ R R955 1 2 DMIC_ CLK 3
GPIO1/DMIC-CLK DMIC_CLK <34>
FBMA-10-100505-301T _2P Int. MIC
Del RA3, RA4 29 2 DMIC _DATA_ R R954 2 1 R_ short 0_ 0402_ 5% DMIC_ DATA
MIC2-VREFO GPIO0/DMIC-DATA DMIC_DATA <34>
10 mils 30 10 mils
+MIC1_VREFO_R MIC1-VREFO-R
10 mils 31
+MIC1_VREFO_L MIC1-VREFO-L

For EMI 42 27 AC97 _ VREF 10 mils

PVSS1 VREF
43 26 2 1
HDA _SYNC_ AUDIO HDA_SDOUT_AUDIO PVSS2 AVSS1
2 2 7 37
DVSS AVSS2
CA1278 @ CA1285 49 1 2
10P_0402_50V8J 10P_0402_50V8J Thermal PAD
1 1
Close to UA8.Pin27
@ 2
RA1635
1 HDA_BITCLK_AUDIO
ALC269Q-VC2-GR_QFN48_6X6
AGND
1 0_0402_5%
@ CA1282
22P_0402_50V8J~N
2

Pin Assignment Location Function

PC Beep SPK-OUT (Pin40/41/44/45) Internal Int Speaker
4 1 2 4
<45> BEEP#
EC Beep CA4 0.1U_0402_16V4Z Capless HP-OUT (Pin32/33) External Headphone out
RA1
1 2 PC_BEEP1 1 2 PC_BEEP MIC1(Pin21/22) External Mic in
<14> HDA_SPKR
PCH Beep CA5 0.1U_0402_16V4Z 33_0402_5%
1 RA1647 2 @
0_0402_5% Security Classification LC Future Center Secret Data Title
@ RA2
10K_0402_5%
HD AUDIO ALC269Q-VC3

 
Issued Date 2011/11/01 Deciphered Date 2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
DGND AGND Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
Custom
Rev
1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 42 of 65
A B C D E F G H
 A B C D E F G H

B+ B+_PVDD

2 LA57 1 B+ _ PVDD B+ = 19V

0_0603_5%
1A, W=40 mils 2 2 2
@ @ @ @ @
1 1
1 C40 C41 1
1U_0603_25V6 1U_0603_25V6
1 1 1 2 2

22uf*3, 10uf*8 for Damage issue

Stuff --> CA1, CA2, CA3, CA1374, CA1375 and CA1376
GAIN SETTING
+5VS

C42 2012-0418 --> Add R892 for Gain setting

1 2
+5VS
R892 @
1U_0402_6.3V6K U73 1 2
B+_PVDD
4 5 GAIN1 0 _0402_ 5%
21 VS G1 6 GAIN2
22 PVDD G2 2012-0418 --> W=40 mils GAIN1
PVDD
One channel analog input 3 SPKOUT _ L1+ LA56 2 1 R_ short 0_ 0603_ 5% SPK_ L1 GAIN2
OUTL+
SPKOUT _L1 C43 1 2 1U _ 0402_ 6.3V6K 8 1 SPKOUT_ L2- LA58 2 1 R_ short 0_ 0603_ 5% SPK_ L2
<42> SPKOUT_L1 INL+ OUTL- 2
SPKOUT _ R1 C44 1 2 1U _ 0402_ 6.3V6K 12 OUTL-
+5VS <42> SPKOUT_R1 INR+ 17 SPKOUT _ R2- LA61 2 1 R_ short 0_ 0603_ 5% SPK_ R2 R895 R890
9 OUTR- 18 0_0402_5% 0_0402_5%
1 INL- OUTR-
R899 C45 C46 1 2 11 16 SPKOUT _ R1+ LA60 2 1 R _ short 0_ 0603_ 5% SPK_ R1
1U_0402_6.3V6K INR- OUTR+
0_0402_5%
2 2 1U_0402_6.3V6K Add JUMP for layout route 2
@
7
LIM_TH 10
13 GND 19
GAIN1 GAIN2 GAIN SETTING (dB)
R960 1 @ 2 0_0402_5%
TEMPLOCK PGND 20
PGND
R898
R_short 0_0402_5% +3VALW
2 @ 1 AMP OFF# 15
SHUTDOW N
PGND
PGND
23
24 * GND GND 9 (Default)
R1407 10K_0402_5% 14 25
RELEASE EP NC GND 13
Change BOM structure to @ 1
for leakage C47
MAX98400BETGLFT_TQFN-EP24_4X4 +5VS GND 16.7
1U_0402_6.3V6K
2
GND NC 20.1
2012-0429 --> Change C42~C47 Cap to X5R type for Vendor suggestion
NC NC 23.3

+5VS NC 26.4

2012-0418 --> Set R890 BOM structure as Stuff

3 R959 1 @ 2 0_0402_5% 3
SPK _R1 @ CA9 1 2 1000P _0402_ 50V7K~N
+3VS Speaker Conn.
SPK _R2 @ CA10 1 2 1000P _0402_ 50V7K~N
JSPK1 ME@
2 SPK _L1 @ CA11 1 2 1000P _0402_ 50V7K~N SPK_ L1 1
SPK_L2 2 1
C1064
0.1U_0402_10V7K SPK _L2 @ CA12 1 2 1000P _0402_ 50V7K~N SPK_ R1 3 2
SPK_R2 4 3
1 5 4
2009/11/02 Modify 6 G5
<45> EC_MUTE# EC _ MUTE# 1
IN1 4 AMP OFF# G6
EAPD# 2 O ACES_85205-04001
<42> EAPD# IN2 U74
SN74AHC1G08DCKR_SC70-5

D62 @ D61 @
AZ5125-02S.R7G_SOT23- 3 AZ5125-02S.R7G_SOT23-3

1 @ 2
R958 0_0402_5%

2012-0622 --> change these BOM structure for BOBO noise issue
1. R958, R959 --> "UnStuff"
2. U74, C1064 --> "Stuff"
Reserve for ESD request.

4 4

Security Classification LC Future Center Secret Data Title

AMP-MAX98400BETG+T

 
Issued Date 2011/11/01 Deciphered Date 2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 43 of 65
A B C D E F G H
 5 4 3 2 1

R1458
2 1
+3VS +3VS_CARD
R_short 0_0603_5% close to JREAD1 pin 9 @
MDIO5_R R1459 2 @ 1 C1023 1 2

close to JREAD1 pin 17 100_0402_5% 100P_0402_50V8J

@
U71 CLK _ PCIE_ CARD_ PCH# MDIO5 _ R R1460 2 @ 1 C1024 1 2
CLK_PCIE_CARD_PCH# <15>
JMB389
D CLK _ PCIE_ CARD_ PCH D
CLK_PCIE_CARD_PCH <15>
+1.8VS_CARD
5
10 APVDD close to JREAD1 pin 36 100_0402_5% 100P_0402_50V8J
@
36 APV18 3 1 2 1
+3VS_CARD R14612 MDIO5 _ RR R1462 @ C1025 1 2
19 TAV33 APCLKN 4 12K_0402_1%
20 DV33 APCLKP 7 APREXT 100_0402_5% 100P_0402_50V8J
44 DV33 APREXT 9 PCIE _ PTX _ C _ DRX_ N4
DV33 APRXN PCIE_PTX_C_DRX_N4 <15>
18 8 PCIE _ PTX _ C _ DRX_ P4
+1.8VS_CARD DV18 APRXP PCIE_PTX_C_DRX_P4 <15>
37 11 PCIE _ PRX _ C _ DTX_ N4 C1026 1 2 .1U _ 0402_ 16V7K PCIE_ PRX_ DTX_ N4 Close to connector for EMI request.
DV18 APTXN PCIE_PRX_DTX_N4 <15>
1 2 43 12 PCIE _ PRX _ C _ DTX_ P4 C1028 1 2 .1U _ 0402_ 16V7K PCIE_ PRX_ DTX_ P4
SDDV33_18 APTXP PCIE_PRX_DTX_P4 <15>
C1027 W=20mils
2.2U_0603_6.3V6K
Please close to pin43 +CRD_POWER
48 MDIO0
MDIO0 47 MDIO1
MDIO1
4 5,6 > PLT_RST#
1
XRSTN MDIO2
46 MDIO2 (40mil)
2 45 MDIO3 +CRD _POWER
XTEST MDIO3
13
CPPE_N MDIO4
41 MDIO4
R1463 R1464 800mA
21 42 MDIO5 1 2 MDIO5 _ R 1 2 MDIO5 _ RR
CR1_LEDN MDIO5
+CRD_POWER
17
CR1_PCTLN MIDO6
24 MDIO6
R_short 0_0402_5% R_short 0_0402_5% 1 JREAD1 ME@ (40mil)
SD _ CD# 16 40 MDIO7 C1029 22 11
MS _ CD# 15 CR1_CD0N/WAKEN MDIO7 29 MDIO8 XD-VCC SD4-VDD 18
CR1_CD1N MDIO8 1 MS9-VCC
XD _ CD# 14
CR2_CD2N MDIO9
28 MDIO9 10U_0805_10V6K
2
MDIO0 30
XD10-D0 (40mil)
33 27 MDIO10 C1031 Close to CONN. MDIO1 29 9 MDIO5_R
C SPI_CSN MDIO10 XD11-D1 SD5-CLK C
34 26 MDIO11 @ 22P_0402_50V8J MDIO2 28 4 MDIO0
35 SPI_SO MDIO11 25 MDIO12 2 MDIO3 27 XD12-D2 SD7-DAT0 3 MDIO1
SPI_SI MDIO12 1 XD13-D3 SD8-DAT1 1 1
30 23 MDIO13 MDIO8 26 21 MDIO2
39 SPI_SCK MDIO13 22 MDIO9 25 XD14-D4 SD9-DAT2 19 MDIO3
MDIO14
TXIN MDIO14 MDIO10 24 XD15-D5 SD1-DAT3 16 MDIO4
2 MDIO11 23 XD16-D6 SD2-CMD 1 SD_CD# 2 2
XD17-D7 SD-CD 2 MDIO6
MDIO4 33 SD-WP
MDIO6 32 XD07-WE 6
6 MDIO14 34 XD08-WP SD6-VSS 13
31 APGND XD _ CD# 39 XD06-ALE SD3-VSS
32 GND MDIO13 38 XD01-CD
38 GND MDIO12 37 XD02-R/B
GND MDIO5 _ RR 36 XD03-RE 17 MDIO5_R
MDIO7 35 XD04-CE MS8-SCLK 10 MDIO0
XD05-CLE MS4-DATA0 8 MDIO1
JMB389-LGAZ0C_LQFP48_7X7
31 MS3-DATA1 12 MDIO2
40 XD GND MS5-DATA2 15 MDIO3
XD GND MS7-DATA3 14 MS _ CD#
MS6-INS 7 MDIO4
MS2-BS 5
41 MS1-VSS 20
+1.8VS_CARD 42 SD CD/WP GND MS10-VSS
SD CD/WP GND
B B
T-SOL_144-1313002600_40P_NR-T

+3VS_CARD

1 1 1

+1.8VS_CARD
2 2 2
1 1 1 1

2 2 2 2
1
Close to pin10 @ @ C1042 1
C1043
Close to pin5->1000P->0.1u->10u 0.1U_0402_16V4Z
2 10U_0805_10V6K
2
Close to pin 19,20 Close to pin 36 Close to pin 37 Close to pin 18
XD_CD#
Close to pin 44
SD _ CD# +CRD_POWER
A A

1 1
C1044 C1045
MDIO6 1 R1465 2 Title
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1K_0402_5% Security Classification LC Future Center Secret Data
@ 2 @ 2
MDIO13 1 R1466 2
Issued Date 2011/11/01 Deciphered Date 2012/12/31 CARD READER JMB389
1K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 44 of 65
5 4 3 2 1
 Support DC S5 Charge

NOS5C@
R1524 1 2 0 _0603 _5% +3VALW

S5C@
R1525 1 2 0 _0603 _5%
close EC +3VL

C1082
EC _SCI#/ EC_ SMI# pull up to PCH 1 2 VCOREVCC
+3VALW_R +3VALW_R +3VALW _EC
All capacitors close to EC L80 +3VS
D70 2 1 EC _ SMI# _ R .1U_0402_16V7K
<19> EC_SMI# +3VALW _R 1 2
RB751V-40_SOD323-2 BLM18PG181SN1D_0603 1
D71 2 1 1
1 EC _SCI# _ R C1072 C1073 C1075
<19> EC_SCI# 1 1 1 1 1 1
RB751V-40_SOD323-2 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z
@ +3VS +3VALW _EC L81
2
R1519 2 1 1 2 ECAGN D 2 2
+RTCBATT
0_0402_5% 2 2 2 2 2 2 BLM18PG181SN1D_0603

R1520
2 1

R_short 0_0402_5%

minimum trace width 12 mil Support DC S5 Charge

U70
+3VALW +3VL

NOS5C@ S5C@
R1529 R1530
KBRST# 4 24 PWR _ LED# 0_0603_5% 0_0603_5%
<19> KBRST# KBRST#/GPB6 PWM0/GPA0 PW R_LED# <47>
pull up to PCH <14> SERIRQ
SERIRQ 5
SERIRQ/GPM6 PWM1/GPA1
25 BATT _ CHG _ LED#
BATT_CHG_LED# <47>
LPC _ FRAME# 6 28 BATT _ LOW _ LED#
<14,37> LPC_F RAME# LFRAME#/GPM5 PWM2/GPA2 BATT_LOW _LED# <47>
LPC _ AD3 7 29 LED _ KB_ PWM EC_ SMB_ CK1 2 1
<14,37> LPC_AD3 LAD3/GPM3 PWM3/GPA3 LED_KB_PW M <46>
Support DC S5 Charge <14,37> LPC_AD2
LPC _ AD2 8 PWM PWM4/GPA4 30 SLI _ FAN_ PWM
SLI_FAN_PW M <32,41>
For 2nd fan R1417 2.2K_0402_5%
LAD2/GPM2
<14,37> LPC_AD1
LPC_AD1 9
LAD1/GPM1 PWM5/GPA5
31 EC_FAN_PW M
EC_FAN_PW M <40>
For fan
<14,37> LPC_AD0
LPC _ AD0 10
LAD0/GPM0 PWM6/SSCK/GPA6
32 BEEP#
BEEP# <42> For EC beep EC _ SMB_ DA1 2 1
+3VALW
NOS5C@ <18> CLK_PCI_EC
CLK _ PCI _ EC 13
LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7
34 EC_ INVT_ PWM
EC_INVT_PW M <34>
R1424 2.2K_0402_5%
R1404 1 2 WRST# 14 120 ACIN 2 R1430
1
WRST# TMRI0/WUI2/GPC4 ACIN <62> GC6_EVEN T# <19,23,32>
100K_0402_5% 1 EC _ SMI# _ R 15
ECSMI#/GPD4 TMRI1/WUI3/GPC6
124 VGA _ AC_ DET
VGA_AC_DET <23>
20120713 --> change to normal footprint
C999 BATT _ LEN# 16 0_0402_5%
+3VL <53> BATT_LEN# PWUREQ#/BBO/SMCLK2A L T/GPC7
1U_0402_6.3V6K 17 66 VGA_IMON Cancel
S5C@ NC ADC0/GPI0
R1405 1 2 PLT _ RST# 22 67 SA_P GOOD SA_PGOOD <56>
2 <18,23,32,37,38,44,6> PLT_RST# LPCRST#/W UI4/GPD2 ADC1/GPI1
100K_0402_5% EC _ SCI# _ R 23 68 BATT _ TEMP +3VS
ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP <53> +3VALW
<19> GATEA20
GATEA20 126
GA20/GPB5
ADC ADC3/GPI3
69 IMVP_IMON
IMVP_IMON <59>
70 LAN _ WAKE# R1532 1 @ 2 100K_0402_5% EC _ FAN_ SPEED 2 1
ADC4/WUI28/GPI4 71 ADP _ I R1431 10K_0402_5%
ADC5/DCD1#/WUI29/GPI5 ADP_I <53,62>
72 AD _ ID AD _ ID R1533 1 @ 2 100K_0402_5%
ADC6/DSR1#/WUI30/GPI6 AD_ID <53>
73 LID _ SW # SLI _ FAN_ SPEED 2 1
KSO[0..15] ADC7/CTS1#/WUI31/GPI7 LID_SW # <46>
<46> KSO[0..15] KSI0 58 for power adapter ID OPT,35W --> R1532 R1485 10K_0402_5%
KSI1 59 KSI0/STB# 78 SUSW ARN# 3V--- 90W OPT,45W --> R1532, R1533
KSI1/AFD# DAC2/TACH0B/GPJ2 SUSWARN# <16> 1.5V--- 120W SLI --> R1533 +3VS
KSI[0 .. 7] KSI2 60 79 AC _ PRESENT
<46> KSI[0..7] KSI2/INIT# DAC3/TACH1B/GPJ3 AC_PRESENT <16> 0V--- 170W
KSI3 61
KSI3/SLIN# DAC DAC4/DCD0#/GPJ4
80 DRAMRST_CNTRL_ EC
DRAMRST_CNTRL_EC <7>
KSI4 62 81 EC _ WL_ OFF# TP _ CLK 1 2
KSI4 DAC5/RIG0#/GPJ5 EC_W L_OF F# <37>
KSI5 63 1. Change BOM structure of R1532 and R1533 to "@" R1410 4.7K_0402_5%
KSI6 64 KSI5 85 USB_CH# 2. For Adapter AD_ID function, Power team had
KSI6 PS2CLK0/TMB0/GPF0 USB_CH# <49> reserved resistance (PR396, Pr397) at power side
KSI7 65
KSI7 PS2 PS2DAT0/TMB1/GPF1
86 PBTN _ OU T#
PBTN_OUT# <16>
TP_ DATA 1 2
KSO0 36 87 PM _ SLP_ SUS# R1412 4.7K_0402_5%
KSO0/PD0 PS2CLK1/DTR0#/GPF2 PM_SLP_SUS# <16,51>
KSO1 37
KSO1/PD1
Int. K/B PS2DAT1/RTS0#/GPF3
88 SUSACK#
SUSACK# <16> +3VS
KSO2 38 89 TP _ CLK
39 KSO2/PD2 Matrix PS2CLK2/WUI20/GPF4 90
TP_CLK <46>
KSO3 TP_ DATA
KSO3/PD3 PS2DAT2/WUI21/GPF5 TP_DATA <46>
KSO4 40 EC _ SMB_ CK2 2 1
KSO5 41 KSO4/PD4 96 CAPS_LED#
CAPS_LED# <47> R1423 2.2K_0402_5%
KSO6 42 KSO5/PD5 WUI19/GPH3/ID3 97 PCH _ PWR _ EN
KSO6/PD6 GPH4/ID4 PCH_PW R_EN <51>
KSO7 43 98 ACOFF R1433 EC _ SMB_ DA2 2 1
KSO7/PD7 GPH5/ID5 ACOFF <62>
KSO8 44 99 PCH _ PWROK PCH _ PWROK 1 @ 2 R1422 2.2K_0402_5%
KSO8/ACK# GPH6/ID6 PCH_PW ROK <16>
KSO9 45
KSO9/BUSY 10K_0402_5%
EC _ SMB_ CK1 KSO10 46 101 GPG3 +5VALW
<49,53,62> EC_SMB_CK1 KSO10/PE GPG3
EC _ SMB_ DA1 KSO11 51 102 GPG4
<49,53,62> EC_SMB_DA1 KSO11/ERR# GPG4
KSO12 52
KSO12/SLCT
SPI Flash ROM GPG5
103 GPG5 USB_CH# 1 2
EC _ SMB_ CK2 KSO13 53 105 CMOS_ ON# R1482 10K_0402_5%
<15,23,32,40> EC_SMB_CK2 KSO13 GPG7 CMOS_ON# <34>
EC_SMB_DA2 KSO14 54
<15,23,32,40> EC_SMB_DA2 KSO14
KSO15 55 USB_ON# 1 2
KSO15
Reserved SMBus channel 0 56
KSO16/SMOSI/GPC3 RXD/SIN0/GPB0
108 EC _ RX
EC_RX <37>
R1409 10K_0402_5%
for debugging 57
KSO17/SMISO/GPC5 UART TXD/SOUT0/GPB1
109 EC _ TX
EC_TX <37>

EC _ SMB_ CK2 110 82 SYSON

SMCLK0/GPB3 EGAD/WUI25/GPE1 SYSON <55> +3VS
Please place R1435 EC _ SMB_ DA2 111
SMDAT0/GPB4 SM Bus EGCS#/WUI26/GPE2
83 SUSP#
SUSP# <32,51,55,57>
close to EC within 790mil EC _ SMB_ CK1 115
SMCLK1/GPC1 EGCLK/WUI27/GPE3
84 VR_ ON
VR_ON <59>
EC _ SMB_ DA1 116 EC_ FAN_ PWM 2 @ 1
117 SMDAT1/GPC2 77
H _ PECI R1435 2 1 43 _ 0402_ 1% PECI_ EC EC_ MUTE# R1402 10K_0402_5%
<6> H_PECI SMCLK2/PECI/WUI22/GPF6 GPJ1 EC_MUTE# <43>
LAN _ PWR _ ON# 118 100 ENBKL
<38> LAN_PW R_ON# SMDAT2/PECIRQT#/WUI23/GPF7 SSCE0#/GPG2 ENBKL <34>
<16> PM_SLP_S3# PM _ SLP_ S3# 94
WUI17/CRX1/SIN1/SMCLK3/GPH1/ID1 GPIO SSCE1#/GPG0 106 H_ PROCHOT#_ EC 2 @ 1 R1429
PROCHOT <53> +3VS
<16> PM_SLP_S4# PM _ SLP_ S4# 95 104 ME_ FLASH 0_0402_5%
WUI18/CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 ME_FLASH <14>
107 EC _ ON
DTR1#/SBUSY/GPG1/ID7 EC_ON <50,54>
119 BKOFF#
CRX0/GPC0 BKOFF# <34>
EC _ RSMRST# 112 123 AOAC _ ON LPC _ FRAME# 1 2
<16> EC_RSMRST# RING#/PWRFAIL#/CK32K OUT/LPCRST#/ G PB7 CTX0/TMA0/GPB2 AOAC_ON <51>
<50> ON/OFF ON/OF F 125
PW RSW/GPE4 TouchPad_LED R1521 10K_0402_5%
WAKE UP TP_LED# <47>
76 TP_LED# 1 @ 2 R1619
TACH2/GPJ0 A_DET#_R <49>
48 SLI _ FAN_ SPEED 0_0402_5%
TACH1A/TMA1/GPD7 SLI_FAN_SPEED <32,41>
NOVO# 19 47 EC _ FAN_ SPEED
<50> NOVO# BAO/WUI24/GPE0 TACH0A/GPD6 EC_FAN_SPEED <40>
USB_ ON# 33
<48,49> USB_ON# GINT/CTS0#/GPD5
<16> DPWROK_EC
DPW ROK _EC 35
RTS1#/W UI5/GPE5
GPIO
93
NUM_LED# only for Y500 CLKRUN#/WUI16/GPH0/ID0
VR _ HOT# 1
R1427
2
<59> VR_HOT# H_PROCHOT# <53,6>
EC _ LID_ OUT# 2 R_short 0_0402_5%
<19> EC_LID_OU T# CK32KE/GPJ7
128 Clock D
CK32K/GPJ6
H_ PROCHOT#_ EC 2 1
R1539 1 2 ECR _EN _ R G
<34> ECR_EN
0_0402_5% Q141 S C1004
2N7002H_SOT23-3 47P_0402_50V8J
R1540 1 @ 2 2
<10> CPU1.5V_S3_GATE
0_0402_5% R1102
100K_0402_5%
For Deep S3
R1542 1 GC6@ 2 IT8580E-HX_LQFP128
<23,27> FB_CLAMP
0_0402_5%

EMC Request BATT _ TEMP 1 2 SUSP# SYSON +3VALW

C1000 100P_0402_50V8J
SYSON ACIN 1 2
C1001 100P_0402_50V8J
100K_0402_5% 100K_0402_5%
R1434
R1101 R1522
10K_0402_5%
1
@

2 LAN _ W AKE#
LAN_W AKE# <37,38>
For factory EC flash

GPG5 PAD IT0

CMOS_ON# PAD IT1
GPG3 PAD IT2
GPG4 PAD IT3
H_ PROCHOT#_ EC PAD IT4
PAD IT5
PAD IT6 Security Classification LC Future Center Secret Data Title
PAD IT7

 
Issued Date 2011/11/01 Deciphered Date 2012/12/31 EC IT8580E
WRST# PAD IT8 THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETEN T DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZE D BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 45 of 65
 5 4 3 2 1

14" INT_KBD Conn.

KSI[0..7]
KSI[0..7] <45>
KB Lighting CONN.4pin
KSO[0 ..15]
KSO[0..15] <45>
D JKBL1 D
+VCC_KB_LED
JKB1 1
KSO2 C734 1 2 @ 100P _0402 _ 50V8J KSO1 C735 1 2 @ 100P _ 0402_ 50V8J KSI1 1 2 1
KSI7 2 1 3 2
KSO15 C736 1 2 @ 100P _0402 _ 50V8J KSO7 C737 1 2 @ 100P _ 0402_ 50V8J KSI6 3 2 4 3
KSO9 4 3 5 4
4 2 G1
KSO6 C738 1 2 @ 100P _0402 _ 50V8J KSI2 C739 1 2 @ 100P _ 0402_ 50V8J KSI4 5 6
KSI5 6 5 G2
KSO8 C740 1 2 @ 100P _0402 _ 50V8J KSO5 C741 1 2 @ 100P _ 0402_ 50V8J KSO0 7 6 @ E&T_6906-Q04N-00R
KSI2 8 7 1 ME@
KSO13 C742 1 2 @ 100P _0402 _ 50V8J KSI3 C743 1 2 @ 100P _ 0402_ 50V8J KSI3 9 8
KSO5 10 9
KSO12 C744 1 2 @ 100P _0402 _ 50V8J KSO14 C745 1 2 @ 100P _ 0402_ 50V8J KSO1 11 10
KSI0 12 11
KSO11 C746 1 2 @ 100P _0402 _ 50V8J KSI7 C747 1 2 @ 100P _ 0402_ 50V8J KSO2 13 12
KSO4 14 13
KSO10 C748 1 2 @ 100P _0402 _ 50V8J KSI6 C749 1 2 @ 100P _ 0402_ 50V8J KSO7 15 14
KSO8 16 15 +5VS
KSO3 C750 1 2 @ 100P _0402 _ 50V8J KSI5 C751 1 2 @ 100P _ 0402_ 50V8J KSO6 17 16 AO3413
KSO3 18 17 VGS= -4.5V, Id=-3A, Rds<97m ohm
KSO4 C752 1 2 @ 100P _0402 _ 50V8J KSI4 C753 1 2 @ 100P _ 0402_ 50V8J KSO12 19 18 +VCC_KB_LED
KSO13 20 19 Q121 AO3413_SOT23-3
KSI0 C754 1 2 @ 100P _0402 _ 50V8J KSO9 C755 1 2 @ 100P _ 0402_ 50V8J KSO14 21 20
21 KBL@
KSO11 22 3 1
KSO0 C756 1 2 @ 100P _0402 _ 50V8J KSI1 C757 1 2 @ 100P _ 0402_ 50V8J KSO10 23 22 R1229
KSO15 24 23 10K_0402_5%
25 24 KBL@ 1 1
G1 2
CONN PIN define need double check 26 @ @
G2 C1053 C1054
C908@
0.1U_0402_16V4Z
ACES_85202-24051 2 2 0.1U_0402_16V4Z
ME@ 1 2 1
R1232 0_0402_5%
C 1 C
KBL@
C907
@
D 0.01U_0402_16V7K
2
2 Q122
<45> LED_KB_PW M
G 2N7002_SOT23
S KBL@

R1480
100K_0402_5%
KBL@

To TP/B Conn.

JTP1 ME@
SMB_DATA_S3 1
<12,13,15,37> SMB_DATA_S3 1
SMB _CLK _ S3 2
<12,13,15,37> SMB_CLK_S3 3 2
TP _ DATA 4 3
<45> TP_DATA 5 4
TP _ CLK
B <45> TP_CLK
1
@
1
@
+3VS
6 5
6 Lid Switch B

C761 C76 2 C760 7

100P_0402_50V8J 100 P_0402_50V8J 8 GND
2 2 0.1U_0402_16V4Z GND
ACES_88514-00601-071
1 R1002 2 +VCC_LID
+3VALW R1003 1 2 100K_0402_5%
R_short 0_0402_5%
5711ACDL-M3T1S SOT-23
D58
4 1
I/O3 I/O1 1
+3VALW 3
OUTPUT LID_SW # <45>
C758
5 2 0.1U_0402_16V4Z 2
VDD GN D 2
C759
U37 10P_0402_50V8J
1
6 3
I/O4 I/O2

AZC099-04S.R7G_SOT23-6
@
For ESD request

A A


LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 KB /SW /LPC DEBUG CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 46 of 65
5 4 3 2 1
 +3VALW +3VALW
BATT _LOW _ LED#_ R BATT_ CHG_ LED#_ R
BATT CHARGE/LOW LED
R1562 R1558
100K_0402_5% 100K_0402_5% White
D Q160A D Q158A LED2
2 2
Amber
R1012 1
G G BATT _LOW _ LED#_ R 2 3
1 1 470_0402_5%
S S White 1
C1100 C1098 +5VALW
D 0.1U_0402_16V4Z D 0.1U_0402_16V4Z 2 R1014 1 2
BATT _ CHG_ LED#_ R
5 2 5 2
<45> BATT_LOW_LED# <45> BATT_CHG_LED# 470_0402_5%
G G
Q160B Q158B 12-22-S2ST3D-C30-2C_W HI-ORG
S 2N7002KDW H_SOT363-6 S 2N7002KDW H_SOT363-6

R1564 1 @ 2 R1561 1 @ 2
0_0402_5% 0_0402_5%
2012-0507 --> Add MOS solution onLED3, 2 to avoid the light blinked.

+3VALW +5VS
PWR LED HDD LED CapsLK LED
@
1 R1491 2 TP_LED#_R
PW R_LED#_R +5VS
10K_0402_1% White
R1559
100K_0402_5% LED3
R1013
R1490 1 2 2 1
@ <50> PW R_LED#_R +5VALW
10K_0402_1%
D Q159A D Q151A 300_0402_5%
@ 12-21SYGCS530-E1S155TR8_W
2 2
G TouchPad_LED G 2012-0507 --> Change LED1 to T/P LED
1 LED1
1 2 2 R1322 1
S R1621 1 2 S TP _ LED#_ R
C1099 <45 > TP_LED# +5VS
0 _0402_ 5%
D 0.1U_0402_16V4Z @ D 300_0402_5%
12-21SYGCS530-E1S155TR8_W
5 2 R1622 1 @ 2 5
<45> PW R_LED# <14> HDD_LED#
G 0_0402_5% G
Q159B Q151B LED4
2N7002KDW H_SOT363-6 1 2 2 R1323 1
S 2N7002KDW H_SOT363-6 S <45> CAPS_LED# +5VS
300_0402_5%
12-21SYGCS530-E1S155TR8_W
R1560 1 @ 2 R1492 1 2 LED3 LED2 LED1 LED4
0_0402_5% 0_0402_5%

POWER BATTERY T/P CapsLK

Screw Hole
BlueTooth DC

+3VS +3VS_BT
CPU and GPU: H_3P8X 6 MIN PCIE: H_3P3 X 1
BT@ Q154
AO3413_SOT23-3
30mils C: H_3P8X 3 B: H_3P8X 3 E: H_3P3X 1
3 1
H13 H10 H12 H11 H14 H15 H28
1 1 1 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
C1070 C1069 C1083
BT@ 0.1U_0402_16V4Z BT@ 0.01U_0402_25V7K BT@ 0.1U_0402_16V4Z

BT@ 2 2 2
1 R1526 2
<19,37> PCH_BT_ON#
100K_0402_5%
CPU GPU
1
C1084
@ 0.1U_0402_16V4Z
2

BT Conn.
+3VS_BT
JBT1 ME@ ME: H_8P0 X 8; H_3P3X 1; H_4P0X3P0N X 2; H_2P0X 1
1
1
USB20 _ P13
2
3 2 A: H_2P8X 8
<18> USB20_P13 3
<18> USB20_N13 USB20 _ N13 4
4 H16 H22 H24 H25 H31 H33
H30 H32
5 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
6 GND
GND
ACES_50209-0040N-001

E: H_3P3X 1 H_4P0X3P0NX 3 H_2P0X 2

H29 H20 H21 H23
HOLEA HOLEA HOLEA HOLEA

PCB Fedical Mark PAD

Security Classification LC Future Center Secret Data Title
FD1 FD2 FD3 FD4 Issued Dat 2011/11/01 Deciphered Date 2012/12/31 LED/EC SPI ROM/BT

 
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 47 of 65
 A B C D E

LEFT SIDE USB3.0 PORT X1

+5VALW +USB_VCCA
U39
1 8
C767 0.1U_0402_16V4Z 2 GND VOUT 7
1 2 1 3 VIN VOUT 6 1
USB _ ON# 4 VIN VOUT 5 USB _ OC1#
<45,49> USB_ON# EN FLG USB_OC1# <18> +USB_VCCA
G547I2P81U_MSOP8 C814 220U_6.3V_M
1
C904 1 2
Low Active 2A @ 1000P_0402_50V7K

2 1 2
C816 470P_0402_50V7K

JUSB1
For EMI request 1
USB20_N2 R1162 1 2 0_0402_5% USB20_N2_R 2 VBUS
<18> USB20_N2 @ D-
USB2.0 choke --> SM070000I00 <18> USB20_P2
USB20 _ P2 R1163 1 @ 2 0_0402_5% USB20 _ P2_ R 3
4 D+
USB3.0 Choke --> SM070001U00 <18> USB30_RX_N3
USB30 _RX _ N3 R1154 1 @ 2 0_0402_5% USB30_RX_R_N3 5 GND_1
USB30 _RX _ P3 R1155 1 2 0_0402_5% USB30_RX_R_P3 6 SSRX- 13
<18> USB30_RX_P3 @
7 SSRX+ GND_6 12
USB30 _TX _ N3 C300 1 2 0.1U _ 0402_ 10V6K USB30 _TX _ C_ N3 R1156 1 2 0_0402_5% USB30_TX_R_N3 8 GND_2 GND_5 11
<18> USB30_TX_N3 @ SSTX- GND_4
USB30 _TX _ P3 C299 1 2 0.1U _ 0402_ 10V6K USB30 _TX _ C_ P3 R1157 1 @ 2 0_0402_5% USB30_TX_R_P3 9 10
L68 <18> USB30_TX_P3 SSTX+ GND_3
USB30_RX_N3 2 1USB30_RX_R_N3 SANTA_370300-1
2 1

ME@
USB30_RX_P3 3 4 USB30 _RX _R _ P3
3 4
2 2
WCM-2012-900T_4P

L70
USB30_TX_C_N3 2 1 USB30_TX_R_N3
2 1
For ESD request
USB30_TX_C_P3 3 4 USB30_TX_R_P3
3 4 D27 D24
@ @
WCM-2012-900T_4P USB30 _RX _ R_ N3 9 10 1 1USB30 _RX _ R_ N3 USB20 _ N2_ R 3 6
I/O2 I/O4
L72 USB30 _RX _ R_ P3 8 9 2 2 USB30 _RX _ R_ P3
USB20 _ N2 2 1 USB20 _ N2_ R
2 1 USB30 _TX _ R_ N3 7 4 USB30 _TX _ R_ N3 2 5
7 4 +5VALW
GND VDD
USB20 _ P2 3 4 USB20 _ P2_ R USB30 _ TX_ R_ P3 6 6 5 5 USB30_ TX_ R_ P3
3 4
WCM-2012-900T_4P 3 3 1 4 USB20 _P2 _ R
I/O1 I/O3
8
AZC099-04S.R7G_SOT23-6

YSCLAMP0524P_SLP2510P8-10-9

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 USB3.0 PORT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 48 of 65
A B C D E
 5 4 3 2 1

Sleep & Charge

Right side USB Charger Port (USB_Port5, near JMIC1)
D D

+5VALW +5V_CHGUSB
Active Mode Selection:

1 2
M1 M2 EM_EN ACTIVE MODE

2 1
0 0 1 Dedicated Charger Emulation Cycle
0 1 0 Date Pass-through
Del C1095 0 1 1 BC1.2 DCP
1 0 0 BC1.2 SDP
U8 1 0 1 Dedicated Charger Emulation Cycle
1 1 0 Date Pass-through
+5VALW
7
VS1 *1 1 1 BC1.2 CDP
1 1 3 R1587
8 VBUS1 4 10K_0402_5% +3VALW
VS2 VBUS2 1 @ 2
2 2 USB20 _ P5 14 17 USB20_ P5_ C
<18> USB20_P5 USB20 _ N5 15 DPIN DPOUT 16 USB20_ N5_ C
R1583
10K_0402_5%
ILIM SETTING SEL Pin Decode
<18> USB20_N5 DMIN DMOUT 1 2
USB _CH# 10 18 A_ DET#_ R Pull Low Pull Low
<45> USB_CH# PW R_EN A_DET# A_DET#_R <45>
13 USB _ OC2# OR-500mA 0R -1010_000
ALERT# USB_OC2# <18>
EM _EN 19
EM_EN SMDATA/LATCH
11 EC _ SMB_ DA1
EC_SMB_DA1 <45,53,62>
10K-900mA * 10K-1010_000
12 EC _ SMB_ CK1 12K-1000mA 12K-1010_000
SMCLK/S0 EC_SMB_CK1 <45,53,62>
CH _ M1 1 6 CH _ SEL 1 2 15K-1200mA 15K-1010_000
CH_M2 2 M1 SEL 5 CH_ILIM 1 2 R1553 18K-1500mA 18K-0110_000
M2 COMM_SEL/ILIM R1555 10K_0402_5% 22K-1800mA 22K-0110_000
33K_0402_5% 27K-2000mA 27K-0110_000
C
1 2
* 33K-2500mA 33K-0110_000 C

R1551 EM _EN R1584 2 @ 1

+5VALW
10K_0402_5% 10K_0402_5%
UCS1002-1-BP-TR_QFN20_4X4
R1585 1 2 CH _ M1 R1552 2 @ 1
10K_0402_5% 10K_0402_5%

R1586 1 2 CH _ M2 R1554 2 @ 1
10K_0402_5% 10K_0402_5%

2012-0429 --> Set default mode is "BC1.2 CDP" Mode (2.5A on S0)for USB Port5

USB Power (USB20_P9) AUDIO/B Conn.

JSB1 ME@
1
+5VS 1
2
+5VALW +USB_VCCB +USB_VCCB 2
3
U69 4 3
B 1 8 5 4 B
GND VOUT +5V_CHGUSB 5
2 7 6
3 VIN VOUT 6 7 6
USB _ON# 4 VIN VOUT 5 USB _ OC4# 8 7
<45,48> USB_ON# EN FLG USB_OC4# <18> 8
9
G547I2P81U_MSOP8 10 9
1 1 10
Low Active 2A 11
C988 C989 USB20 _ P9 12 11
@
0.1U_0402_16V4Z 1000P_0402_50V7K <18> USB20_P9 USB20_N9 13 12
2 2 <18> USB20_N9 14 13
USB20 _P5_ C 15 14
USB20 _N5_ C 16 15
17 16
EXT _MIC _ L 18 17
EXT _MIC _ R 19 18
MIC _JD 20 19
<42> MIC_JD 20
HP _ OUTR 21
<42> HP_OUTR HP _ OUTL 22 21
<42> HP_OUTL SPDIF _ OUT 23 22
<42> SPDIF_OUT 23
PLUG_IN 24
<42> PLUG_IN 24
25
26 GND1
Ext. MIC +MIC1_VREFO_L
GND2
ACES_88514-02401-071
+MIC1_VREFO_R

Realtek Review 10.24

A A

Remove Diode (DA1, DA2)

RA1622 RA1623
2.2K_0402_5% 2.2K_0402_5%

Security Classification LC Future Center Secret Data Title

RA1634 2 1 1K _0402 _ 5% EXT_ MIC_ R
AUDIO/B, USB CHARGER

 
<42> MIC2_R Issued Date 2011/11/01 Deciphered Date 2012/12/31
RA1633 2 1 1K _0402 _ 5% EXT_MIC_L
<42> MIC1_R THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 49 of 65
5 4 3 2 1
ON/OFF switch Power Button/B link
Support DC S5 Charge

SW 2@ +3VALW +3VL
to Function/B Conn. 10pin
1 3
Power Button
TOP Side 2 4
NOS5C@ S5C@
SMT1-05_4P R1116 R1117
100K_0402_5% 100K_0402_5%

J7 @
S5C@
Bottom Side 1 2 R1531 1 2 0 _ 0603 _ 5%
+5VALW
SHORT PADS JPW R1 ME@
D72 NOS5C@
1
3 ON/OFF
2 1
ON/OFF <45>
ON/OFFBTN# 1 NOVO _ BTN# 3 2
2 51 _ ON#
4 3
51_ON# <52> <47> PW R_LED#_R
ON/OFFBTN# 5 4
DAN202UT106_SC70-3 6 5
6
@ 1 7
C551 8 GND
D GND
EC _ ON 2 100P_0402_50V8J ACES_88514-00601-071
<45,54> EC_ON
G 2
S Q153
R1523 2N7002_SOT23-3 9/23 ESD Request
10K_0402_5%

Support DC S5 Charge

+3VALW +3VL

R1119
R1118
NOS5C@ S5C@ 100K_0402_5%
100K_0402_5%

D56
NOVO# 2
<45> NOVO#
1 NOVO _ BTN# EMI REQUEST 1ST = SCA00000E00
51_ON# R19 1 NOS5C@ 2 0_0402_5% 3
2ST = SCA00000R00
R28 1 @ 2 0 _ 0402 _ 5% DAN202UT106_SC70-3
ON/OFF

Security Classification LC Future Center Secret Data Title

2011/11/01 Deciphered Date 2012/12/31 OTHER I/O CONN.


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 50 of 65
 A B C D E

+5VALW to +5VS +3VALW to +3VS +1.5V to +1.5VS

J15 @
1 2
+1.5V_CPU_VDDQ 1 2 +1.5VS
AP4800BGM AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V VGS=+-25V JUMP_43X79

+5VALW +5VS +3VALW +3VS

+1.5V +1.5VS
U46 U47
8 1 8 1 1 3 1
1 7 2 1 1 1 7 2 1 1 1 1
1 6 3 6 3 C856 Q120 1
5 5 C857 C835
C837 C838 C840 C841 10U_0805_10V6K
2 SI2301BDS-T1-E3_SOT23-3 10U_0603_6.3V6M 1U_0603_10V4Z
C836 10U_0603_6.3V6M 1U_0603_10V4Z C839 10U_0603_6.3V6M 1U_0603_10V4Z
2 10U_0805_10V6K AP4800BGM-HF 2 2 2 10U_0805_10V6K AP4800BGM-HF 2 2 2 2

R1474 +3VALW
R1475 @ @
470_0603_5%
470_0603_5%

R1481 @
R1087 470_0603_5%
100K_0402_5%
5VS _GATE_ R 1 R1088 2 5VS _GATE R1085 3VS_ GATE_ R 1 R1089 2 3VS_ GATE 2 R1086 1
+VSB +VSB R1090 2
1 1.5VS _GATE
82K_0402_5% 150K_0402_5% R_short 0_0402_5% 470K_0402_5%
1 D D 1 D D D R_short 0_0402_5% 1 D
C842 C843
0.01U_0402_25V7K 2 5
SUSP 0.01U_0402_25V7K 2 SUSP 5 SUSP# 2 C845 1.5VS _GATE 5
R1484 R1483
@ G G @ G G G .1U_0402_16V7K G
2 820K_0402_5% 2 820K_0402_5% 2
Q99A Q99B Q100A Q100B Q101A
S 2N7002KDW H_SOT363-6 S S 2N7002KDW H_SOT363-6 S S 2N7002KDW H_SOT363-6 Q101B S
2N7002KDW H_SOT363-6 2N7002KDW H_SOT363-6 2N7002KDW H_SOT363-6

+5VALW +3VALW to +3V_PCH +5VALW to +5V_PCH

+5VALW +0.75VS

+3VALW +3V_PCH +5VALW +5V_PCH

J11 @ J14 @
R1120 1 2 1 2
DS3@
100K_0402_5% 1 2 1 2
1 1 R1097 R1094
2 C38 @ C39 @ 100K_0402_5% 22_0603_5% 2
JUMP_43X79 JUMP_43X79
PCH _PW R_ EN#_ R R60 1 DS3@ 2 PCH_PW R_EN# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
100K_0402_5% SUSP
D DS3@ 2 2 <10,37,55,57> SUSP
PCH _PW R_ EN 1 R117 2 2 Q118 Q148 Q149
<45> PCH_PW R_EN D D
R_short 0_0402_5% G 2N7002_SOT23 AO3413_SOT23 AO3413_SOT23
S 2 5 SUSP
1. C38, C39 resistance change to 0.1u_0402 <32,45,55,57> SUSP#
<16,45> PM_SLP_SUS# PM_SLP_SUS# R1448 2 @ 1 3 1 3 1 G G
0_0402_5% 2. and the BOM structure as "@" for discharge Q107B
R1121 DS3@ 1 DS3@ 1 1 DS3@ 1 Q107A S S 2N7002KDW H_SOT363-6
100K_0402_5% 2N7002KDW H_SOT363-6
C1065 C1067
DS3@ DS3@ C1066 DS3@ DS3@ C1068
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.01U_0402_25V7K 0.01U_0402_25V7K For Intel S3 Power Reduction.
2 2 2 2

PCH _PW R_ EN#_ R PCH_ PW R_ EN#_ R

+5VALW

+3VALW +3VS +3VS_VGA

+3VS to +3VS_VGA
R1122 Q145
AOAC@
100K_0402_5%
AO3413_SOT23
R6 +5VALW
@
AOAC_ON# 100K_0402_5% 3 1
<37> AOAC_ON#
D AOAC@ 1 1
AOAC@ 2 <57> 0.75VR_EN# C1058 C1059
<45> AOAC_ON AOAC _ON R1453 1 2 Q119 2
D@ R1449 0.1U_0402_16V4Z 0.01U_0402_25V7K
0_0402_5% G 2N7002_SOT23
2 R8 @ 10.75VR EN 5 47K_0402_5% 2 2
S <56,57> +V1.05S_VCCP_PW RGOOD _ R1450 @ C37
G 470_0603_5% 10U_060 3_6.3V6M
3 100K_0402_5% 1 3
Q144B
R1123 AOAC@ D@ S 1 R1451 2
2 DGPU_PW R_EN#
100K_0402_5% SUSP 2N7002K D W H_SOT363-6
10K_0402_5%
G 1
Q144A D D
C1011
2N7002KDW H_SOT363-6
S 2 R1452 1 2 0.1U_0402_10V7K @ DGPU _ PW R_ EN# 5
<18,23> DGPU_PW R_EN
G G
R_short 0_0402_5% 2
Q146A Q146B
S 2N7002KDW H_SOT363-6 2N7002KDW H_SOT363-6 S
R1454
For S3 CPU Power Saving 100K_0402_5%

+3VS +3VS_SLI
+3VS to +3VS_SLI
2012-0419 --> modify +3VS_SLI BOM structure to "SLI@" Q147 SLI@
AO3413_SOT23
+5VALW
3 1
1 1
SLI@ SLI@
C1062 C1063
SLI@ 2
R1502 0.1U_0402_16V4Z 0.01U_0402_25V7K
47K_0402_5% 2 2 R1500 @ C48 SLI@
470_0603_5% 10U_0603_6.3V6M
4 SLI@ 1 4
1 R1513 2
<32> S_DGPU_PWR_EN#
10K_0402_5%
D 1 D
SLI@ C1012
2 R1503 1 2 5
0.1U_0402_10V7K @ S _ DGPU_ PW R_ EN#
<19,32> S_DGPU_PWR_EN G G
0_0402_5% 2
Security Classification LC Future Center Secret Data Title
S Q150A SLI@ SLI@ Q150B S
SLI@ R1501 2N7002KDW H_SOT363-6 2N7002KDW H_SOT363-6
DC INTERFACE

 
Issued Date 2011/11/01 Deciphered Date 2012/12/31
100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , March 11 , 2013 Sheet 51 of 65
A B C D E
 5 4 3 2 1

DC030006J00 VIN B+ to SLI_B+

PF1 PL1
B+ B+_SLI

4
4 APDIN 1
12A_65V_451012MRL
2 APDIN1
SMB3025500YA_2P
1 2 PQ49
SLI@

AON7403L_DFN8-5
+5VS to +5VS_SLI
3 1 JUMP_43X79
3 +5VS +5VS_SLI
2 5
2 3 PJ19
2 1 2
D 1 1 2 D
1
PQ50 AO6409L_TSOP6
@ 4602-Q04C-09R 4P P2.5
JDCIN1 6
PR303 4 5
200K_0402_1% 2
1 1 1
SLI@ 1
PR305 PC351
200K_0402_1% 10U_0603_6.3V6M
SLI@ 2 2
2 SLI@

SLI@
PR304
47K_0402_1%
1 2 PR308
<32> SLI_B+_ON#
47K_0402_1%
1 2
<32> SLI_5V_ON#
SLI@

VIN

2012/04/13
C
PD2
LL4148_LL34-2 PJ1 51ON-1
add SLI Hot-plug Load-SW solution C

BATT+ 2 1 @ JUMP_43X39
1 2
1 2

PQ1
PR3 @ TP0610K-T1-E3_SOT23-3
200_0402_1%
1 2 51ON-2 3 1
VS

PR5
22K_0402_1%

- +
1 2 51ON-3
<50> 51_ON#
JRTC1 PR6 PR7
+3VLP 560_0603_5% 560_0603_5%
PD3
2 1 1 2 1 2 2 1
+RTCBATT

RB751V-40_SOD323-2
@ MAXEL_ML1220T10 1 2 +CHGRTC
+CHGRTC
PD4
@ PU1 PR9 RB751V-40_SOD323-2
@ 200_0603_5%

3.3V APL5156-33DI-TRL_SOT89-3 RTC Battery

3 2CHGRTC IN
B VOUT VIN B

GND PC8
PC7 1U_0805_25V6K
10U_0603_6.3V6M 1
@
@

A A

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 VIN DETECTOR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 52 of 65
5 4 3 2 1
 5 4 3 2 1

VMB2 VMB
PF2 PL2
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2
1 2 BATT+
2 3 EC _ SMCA
3 4 EC _ SMDA
4 5 PC92
D 5 6 33P_0201_50V8J D
6 7 PC9 PC10
7 8 1000P_0402_50V7K 0.01U_0402_25V7K
GND 9
GND
TYCO_1775789-1
@ 2012/0705
add to PC92 for EMI

For KB930 --> Keep PU1 circuit

PH1 under CPU botten side : (Vth = 0.825V)
EC_SMB_CK1 <45,49,62> CPU thermal protection at 92+-3 degree C
For KB9012 (Red square) --> Remove PU1 circuit, but keep PR206
Recovery at 56 +-3 degree C PH201, PR205,PR211,PQ201,PR208,PR212
EC_SMB_DA1 <45,49,62>

1 2
+3VALW
VL
PR12
6.49K_0402_1%
+3VLP
<45,62> ADP_I PR15
4.42K:90W
1
PR14
2
BATT_TEMP <45> A/D 9.1K:120W @
10K_0402_5%
16.5K:170W
+3VS PU2
1 8
VCC TMSNS1
C 2 7 OTP _N_ 002 2 1 C
GND RHYST1 PR19
3 6 Turbo_V 10K_0402_1%
< 45,6> H_PROCHOT# OT1 TMSNS2
4 5 ADP _OCP _ 2 1 2
OT2 RHYST2
D G718TM1U_SOT23-8 PR20
PQ3 2AD P_OCP _1 57.6K_0402_1%
2N7002KW _SOT323-3 G
2012/04/13 S PR20
add power adapter ID
OPT,35W --> PR396 3V--- 90W
PR22 @
0_0402_5%
PR23
R_short 0_0402_5%
57.6K:90W
+3VALW OPT,45W --> PR396, PR397 1.5V--- 120W <45> PROCHOT 1 2 2 1
MAINPW ON <54>
82.5K:120W
SLI --> PR397
0V--- 170W 76.8K:170W
PR396
2 1 AD_ID <45>

100K_0402_5%

2 1

PR397 100K_0402_5%
CPU3@

B B

P2
PQ4
+3VALW +3VALW TP0610K-T1-E3_SOT23-3

3 1
B+ +VSBP
VMB2

PR27 PR28
768K_0402_1% 10M_0402_5% PC14
1 2 0.1U_0603_25V7K
BATT_OUT <62>
PR29 PQ5
10K_0402_1% 2N7002KW _SOT 323-3 PR30
1 2 VL 22K_0402_1%
3 D 1 2
+ 1 2
2 O
PR31 G
- PU3A PR32
221K_0402_1% S
AS393MTR-E1 SO 8P OP 100K_0402_1%

+3VALW PR33 PQ6

1K_0402_1% D PJ2
1 2 2 2N7002KW _SOT323-3 @ JUMP_ 43X39
2 1 <54> SPOK 1 2
+CHGRTC G +VSBP +VSB
1 2
S
PR34 @
10K_0402_1%

2 1 PQ7
A 2VREF_8205 A
PR37 2N7002KW _SOT323-3
PR36 D
10K_0402_1% 2 1 2
<45> BATT_LEN#
G
10K_0402_1% S

Security Classification
LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 53 of 65
5 4 3 2 1
 5 4 3 2 1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205 PJ3
+3VALW P
2 1 +3VALW
2 1
@ JUMP_43X118

D D

PJ4
2 1 +5VALW
+5VALW P 2 1

2012/07/05 @ JUMP_43X118

change PR38 from 13K to 13.7K

PR38 PR39
13.7K_0402_1% 30K_0402_1%
1 2 1 2

PR40 PR41
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2
PJ5 Typ: 175mA
B+ 2 1 +3VLP
2 1
@ JUMP_43X118 PR55 PR43 PR42
0_0402_5% 154K_0402_1% 88.7K_0402_1%
2 1 1 2 1 2
+3VL

PU4
PQ9
C PQ8 AO4406AL_SO8 C
25
AO4466L_SO8
P PAD
4 4
7 24
VO2 VO1 SPOK <53>
8 23 PR45 PC28
PR44
VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1 2 1 2 BST _3V 9 22 BST _ 5V 1 2 1 2
BOOT2 BOOT1
PL3 PC27
2.2_0603_5%
UG _ 3V 10
VFB=2.0V 21 UG _ 5V PL4
UGATE2 UGATE1 4.7UH_VMPI1004AR-4R7M-Z01_10A_2 0%
3.3UH +-20% PCMC063T-3R3MN 6A 0.1U_0603_25V7K +5VALWP
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1
LG _ 3V 12 19 LG _ 5V
PQ10
LGATE2 LGATE1
AO4712_SO8 PQ11
2012/02/29 RT8205LZQW _W QFN24_4X4 1 1
change PC29, PC32, 1 4
+ +
PC34 from + PR48
4

SGA00001E0J to 499K_0402_1%
2 2
SGA00002N8J 2
1 2
AO4456_SO8
B+
VL
B Typ: 175mA B
ENTRIP1 ENTRIP2

PQ12B RT8205 _ B+
2N7002KDW -2N_SOT363-6
PR50
PQ12A 0_0402_5% RT8205
2N7002KDW -2N_SOT363-6 2 5 2 1 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
2VREF_8205
PR52 @
(2)SMPS2=375KHZ(+3VALWP)
PR51 0_0402_5% TPS51125A
0_0402_5% 2 1 TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
<53> MAINPW ON 2 1 VL
(2)SMPS2=305KHZ(+3VALWP)
PR54 @
PR53 0_0402_5%
100K_0402_1% 2 1
2 1
VL
PR185
<45,50> EC_ON 0_0402_5% +3.3VALWP Imax=7.5A ; Ipeak=9A +5VALWP Imax=11.1A ; Ipeak=13.32A
2 1
@
1/2 Delta I=1.113A (F=375K Hz) 1/2 Delta I=1.33A (F=300K Hz)
Vtrip=0.169V Vtrip=0.098V
PQ14 Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Rds(on)=7.0m ohm(max) ; Rds(on)=5.1m ohm(typical)
PR56 2N7002KW _SOT323-3
200K_0402_1% D Ilimit_min=0.169/18m=9.388A Ilimit_min=0.098/7m=14.03A
2> ACPRN 2 1 2 1 2 2 PQ13 Ilimit_max=0.169/15=11.26A Ilimit_max=0.098/5.1m=19.21A
G VS DTC115EUA_SC70-3 Iocp=Ilimit+1/2Delta I=10.5A~12.373A Iocp=Ilimit+1/2Delta I=15.36A ~ 20.54A
S PR57
A A
100K_0402_1%

EC_ ON


2 Title
PQ15
Security Classification
DTC115EUA_SC70-3
2011/11/01 Deciphered Date 2012/12/31 3VALWP/5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 54 of 65
5 4 3 2 1
 A B C D

PJ6
1.5V _B+ 2
2 1
1 B+
Freq= 266~314KHz , 290KHz(typ)
@ JUMP_43X118
PQ16
Iocp=13.58A~23.10A AO4406AL_SO8

4
PR59
0_0402_5%
1 2
<45> SYSON
1
PR61 PC45 PL5 1

PU5 2.2_0603_5% 0.22U_0603_16V 7K S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A

1
PGOOD VBST
10 BST _ 1.5V 1 2BST _1.5V-1 1 2 1 2 +1.5VP
2 9 DH _1.5V
TRIP DRVH
3 8 LX _1.5V
EN SW
1
4 7
VFB V5IN +5VALW PQ17 +
5 6 DL _1.5V
RF DRVL PC47
11 1U_0603_10V6K 2
TP 4
TPS51212DSCR_SON10_3X3 PJ7 +1.5V
VFB=0.7V +1.5VP 2
2 1
1

AO4456_SO8 @ JUMP_43X118

PR65
1 2
PD9 PJ8
RB751V-40_SOD323-2
11.5K_0402_1%
1.5VSP _VGA_ B+ 2
2 1
1 B+
1 2
@ JUMP_43X118
PR66 <BOM Structure>
PR67 10K_0402_1% PQ18
2
0_0402_5% 2

FBVDDQ_PWR_EN 1 2
4
PR68
@ 0_0402_5%
1 2
<32,45,51,57> SUSP# M D V1525URH_PDFN33-8-5

PR70 PC55 PL6

PU6 2.2_0603_5% 0.22U_0603_16V 7K 1UH_PCMC063T-1R0MN_11A_20%
1
PGOOD VBST
10 BST _ 1.5VSP_VGA
1 2BST_1.5VSP_VGA-1
1 2 1 2 +1.5VSP_VGA
2 9 DH_1.5VSP_VGA
TRIP DRVH
3 8 LX_ 1.5VSP_ VGA
EN SW
1
4 7
VFB V5IN +5VALW +
5 6 DL_1.5VSP_VGA PQ19
RF DRVL PC57
11 1U_0603_10V6K 2
TP
TPS51212DSCR_SON10_3X3 4 PJ9 +1.5VS_VGA
VFB=0.7V +1.5VSP_VGA 2
2 1
1

@ JUMP_43X118
AON6504_POW ERDFN56-8-5

PR75
PR74
0_0402_5%
1 2 2 1
VDDQ_SENSE <25>
3 3

11.5K_0402_1%

Freq= 266~314KHz , 290KHz(typ) PR76

10K_0402_1% PJ10
2 1
Iocp=12.25A~20.77A +1.05VS 2 1 +1.05VS_VGA
@ JUMP_43X118
+1.05VS +1.05VS_VGA

8 PQ20 1
+5VALW 7 2
+5VALW 6 3
5

PR78
10K_0402_1% PR79
100K_0402_1% AO4456_SO8 PR80 PQ21 @
@ 0_0402_5% D
PR81 2N7002KW _SOT323-3
1 2 2
PR82 1 2 <10 ,37 ,51 ,57> S U SP G
0_0402_5% S
<19,27,58> DGPU_PWROK 1 2
100K_0402_1%
PR84
PC63 @ 0_0402_5%
PR83 PD10 0.01u_0603_10V6K 1 2
@ 0_0402_5% RB751V-40_SOD323-2
SUSP# 1 2 5 2 1 2

4 4

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 1.5VP/1.5VSP_VGA/1.05VSP_VGA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 55 of 65
A B C D
 5 4 3 2 1

+3VS PR85
1K_0402_1%

VID [0] VID[1] VCCSA Vout

2 1

0 0 0.9V +VCC_SAP 1
PJ11
2 +VCCSA
H_VCCSA_VID1 <10>
TDC 4.2A +VCCSAP
0 1 0.8V Peak Current 6A PAD-OPEN 4x4m

1 0 0.725V OCP current 7.2A

1 1 0.675V H_VCCSA_VID0 <10>

PR87
<45> SA_PGOOD
output voltage adjustable network 1K_0402_1%
2 1
D D
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
+5VALW VCCSA VID is 00 prior to VCCIO stability.

PR88 PR89
10_0402_1% 0_0402_5%
2 1 +VCCSA _EN 1 2
+V1.05S_VCCP_PW RGOOD <51,57>
PC66
2.2U_0603_10V7K
1 2

PU7
PR90 PC67
2.2_0603_5% 0.22U_0603_16V7K
12 +VCCSA _BT 1 2+VCCSA _BT _ 1 1 2
19 BST
PL7
PGND
0.47UH_F DVE0630-H-R47M=P3_17.7A_20%

SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND
10
21 SW PC68 @ @ @ @
PGND
1000P_0603_50V7K
TPS51461RGER_QFN24_4X4 9
22 SW
1 2 2 VIN
8 PR91
SW
23 4.7_1206_5%
2 1 1 VIN
PJ12 7
+3VALW 2
2 1
1 +VCCSA_ PWR_ SRC +VCCSA_ PW R_ SRC 24
VIN
SW

C @ JUMP_43X118 25 C
TP

@ PR92
2 1

33K_0402_5%
PC81 PR93
2 1 100_0402_5%
2 1
0.22U_0402_10V6K

2 1 2 1
PR95
PC82 PR94 0_0402_5%
3300P_0402_50V7K 4.99K_0402_1% 2 1
+VCCSA_SENSE <10>

B B

A A

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 VCCSAP/1.05S_VCCPP

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14, 2013 Sheet 56 of 65
5 4 3 2 1
 5 4 3 2 1

PL8 PU8 SY8033BDBC_DFN10_3X3 PL9

HCB1608KF-121T30_0603 1UH_PH041H-1R0MS_3.8A_20%
1 2 1.8VSP _ VIN 10 2 1.8VSP_ LX 1 2
+5VALW PVIN LX +1.8VSP
9 3
PVIN LX
PC84 8
22U_0805_6.3VAM
SVIN PR97
D D
6 20K_0402_1%
5 FB
EN PJ13
FB=0.6Volt +1.8VSP 2 1 +1.8VS
2 1
<32,45,51,55> SUSP# 1
PR98
2 EN _ 1.8VSP @ JUMP_43X118

0_0402_5%
+1.5V
1.8VSP _ FB PJ14
PR99 +0.75VSP
2 1 +0.75VS
1M_0402_5% 2 1
@ JUMP_43X118
PJ15 PR100
JUMP_43X118 10K_0402_1%
@ PJ16
2 1
2 1
PU9 @ JUMP_43X118
1
VIN NC
8 +3VALW +1.05VS_VCCPP PJ17 +1.05VS
2 1
PC90 2 7 2 1
4.7U_0805_6.3V6K
GND NC @ JUMP_43X118
3 6 PC91
PR101
VREF VCNTL
PR102 1K_0402_1% 4 5 1U_0603_10V6K
@ 0_0402_5%
VOUT NC
1 2 9
<51> 0.75VR_EN# TP
C APL5336KAI-TRL_SOP8P 8 C

PR103
47K_0402_1% D PQ23 +0.75VSP
1 2 2
<10,37,51,55> SUSP G
2N7002KW _SOT323-3

S
2012/02/29
change PR103 from 33k to 47k

PR105
0_0402_5%
SUSP# 1 2

+3VS +1.05VS_VCCPP OCP(min)=22.38A

PJ18
1.05VS _ B+ 2 1
2 1 B+
@ JUMP_43X118
PR108
0_0402_5% PR110 PC103
1 2 0_0603_5% 0.1U_0603_25V7K PQ24
<51,56> +V1.05S_VCCP_PWRGOOD
BST _ 1.05VS _ 1VCCP 2 1 2
B B

PU10 4

AON6428L_DFN8-5
1 12 LX _ 1.05VS _ VCCP PL10
VREF SW 1UH_PCMB062D-1R0MS_9A_20%
1 2 +1.05VS_VCCPP
2 11 DH _ 1.05VS _ VCCP
REFIN DH PQ25
PC104
0.01U_0402_25V7K TPS51219RTER_QFN16_3X3 1
3 10 DL _ 1.05VS _ VCCP
GSNS DL +

4
4 9 2 3
VSNS V5 +5VALW

PC107
PR114
1 2 PC108
<9> VCCIO_SENSE 1 2 1U_0603_10V6K
0.01U_0402_25V7K
A A
10_0402_1%

PR117


Security Classification Title
1 2

10_0402_1%
2011/11/01 Deciphered Date 2012/12/31 1.8VSP/0.75VSP/1.05VS_VCCPP
PC110
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
1000P_0402_50V7K AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 57 of 65
5 4 3 2 1
 8 7 6 5 4 3 2 1

+VGA_CORE Under VGA Core GB4-128 package

H H

+VGA_B+
+3VS PL801
HCB2012KF-121T50_0805
1 2
B+
PL802
PR831 HCB2012KF-121T50_0805
10K_0402_5% 1 2
@
PD801
RB751V-40_SOD323-2
2 1
NVDD_PWR_EN <18>
PR803
120K_0402_5% PR832
G 1 2 10K_0402_5% G

PC855
+VGA_CORE Near VGA Core + 3 V S_VGA
.1U_0402_16V7K
1 2
S TR FDMS36 64S 2N POW ER56-8 S TR FDMS3664S 2N POW ER56-8

PR822 PQ801 PQ802

0_0402_5%
2 1 UGATE1 _2 _VGA 1 1
1
PL803
+VGA_CORE
0.24UH_FDUE0630J-H-R24M-P3_22A_20%
7 7 1 2
2
6 6

PC 858 PR820
@ 10P _ 0402 _ 50V8J @
2 1 4.7_1206_5% 1 1 1
1 1
F PR824 PR823 GPU_VID + + + F
20K_0402_1% 20K_0402_1% UGATE1_VGA PR821 PC838
VREF 2 1 2 1VIDBUF 0_0603_5% 0.22U_0603_10V7K
2 2 BOOT1 _2 _ VGA 2 1 1 2 2 2 2
@ PC859
2 700P_0402_50V7-K PR829
2K_0402_1% PC835
PR825 PR826 @ 680P_0402_50V7K
0_0402_5% 18K_0402_1%
2 1 2 1

2 1 PC856 7 24 PHASE1 _VGA

REFIN PH1
PR805 = 45.3K ==>Fsw = 450KHz 1 2
PC854 2200P_0402_50V7K
23 LGATE1 _VGA
PR805 VREF 8 PU801
VREF LG1 +VGA_B+
0.01U_0603 _50V7K 36.5K_0402_1%
2 1 FS 9 NCP81172MNTWG_QFN24_4X4 22 PR811 0_0402_5% P R834 @
PR806 0_0402_5% FS PGND
2. 2_0402_5%
1 2 VSS _ SEN 10 21 PVCC _ VGA 1 2
<24> VSSSENSE_VGA FBRTN PVCC +5VS
E E
PC852 PR809 FB _VGA 11 20 PC839 4.7U_0603_10V6K
FB LG2
PC853 47P_0402_50V8J 51_0402_1% PC850 10P_0402_50V8J
1000P_0402_50V7K 1 2FB1_VGA1 2 1 2 COMP_VGA 12 19 1 2
COMP PH2
PR808
10K_0402_1%
1 2 VCC _ SEN 1 2 1 2FB2_VGA1 2
<24> VCCSENSE_VGA

PR807 0_0402_5% PC851 PR810

100P_0402_50V8J 82K_0402_1% S TR FDMS3664S 2N POW ER56-8 S TR FDMS3664S 2N POW ER56-8

BOOT2 _ VGA PR818 PQ803 PQ804

0_0402_5%
UGATE2_VGA 2 1 UGATE2 _2 _VGA 1 1

DGPU_PWROK <19,27,55> PL804

+VGA_CORE
0.24UH_FDUE0630J-H-R24M-P3_22A_20%
PR816 10K _ 0402_ 5% 7 7 1 2
PC849 2 1 +3VS
D .1U_0402_16V7K 6 6 D
PR815 2.2_0402_5% @
2 1 +5VS
PR819
4.7_1206_5% 1 1

Thermistor near MOSFET PR817 PC847 + +

0_0603_5% 0.22U_0603_10V7K
trigger point 97 degree C. 2 1 BOOT2 _2 _VGA 1 2
2 2
@

PC844

N14P-GT 35W N14P-GS 25W 680P_0402_50V7K

Ipeak=50A Ipeak=36A PR813 10K_0402_5% PHASE2 _ VGA

2 1 +3VS

C
Imax=35A Imax=25A C

Iocp=64.8A Iocp=64.8A LGATE2 _VGA

Fsw=450KHz Fsw=450KHz
bulk cap 330uF 9m *5 bulk cap 330uF 9m *3 MDU1512, Rdson(max)=5mohm

B B

A A
LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 VGA_COREP

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEP T AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER. Y400-LA8691P
Date: Monday , January 14, 2013 Sheet 58 of 65
8 7 6 5 4 3 2 1
 5 4 3 2 1

PR190
PR192

PR186 PC174
10_0402_1% 0.033u_0402_16V7K PC175 GFX@ GFX@
1 2 FBA3 1 2 GFX@ 0_0402_1% 1 2
D GFX@ SLI@
.1U_0402_16V7K
GFX@ PUT COLSE 0_0402_1%
SLI@
D

PR188 PR189 1 PR190 2 TO GT

TRBSTA# 1 2 FBA1 1 2
GFX@ PH4 Inductor GFX@ GFX@

8.06K_0402_1% 806_0402_1% GFX@

2P: 24K 24K_0402_1%
GFX@ 220K_040 2 _5%_ERTJ0EV224J CSCOMPA 1
PR192
2
PC179
CSREFA
DROOPA 1 2
GFX@ 1P: 24.9K GFX@
GFX@
GFX@ PR193 PC180 PC181 GFX@ 2 PR194 1 NTC_PH203 1.65K_0402_1% 1000P_0402_50V7K
1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1% GFX@ 2P: 1.65K
GFX@ 560P_0402_50V7K PR196 10P_0402_50V8J PC182 PR198 2P: install 1P: 1K
1 PR1952 1 2 COMPA1 1 2 1 2 SW N2A
GFX@ GFX@ 1P: @
1K_0402_1% 5.11K_0402_1% 2200P_0402_50V7K 91K _ 0603 _ 1% CSREFA
GFX@ 1 2 PC183 TSENSEA
GFX@
0 _ 0402 _ 5% 1 PR2002 SW N1A 0.047U_0402_16V7K
SLI@ PR199 GFX@
2P: 21.5K 91K_0603_1% GFX@
CSP1A
GFX@ PR201
1
5.49K_0402_1%
2
1P: 15.8K PC185 GFX@
SW N1A <60>
1000P_0402_50V7K
<10> VCC_AXG_SENSE
1PR202 2 2 PR204 1 CSREFA
PC184 0_0402_5% 0_0402_5% SLI@ 2P: install PH5
1000P_0402_50V7K SLI@
2 PR205 1
CSREFA <60 >
PC186 1P: @ 100K_0402_1%_TSM0B104F4251RZ
<10> VSS_AXG_SENSE 0.047U_0402_16V7K
PR207 0_0402_5% SLI@
+3VS GFX@ 1 SLI@ 2 2 PR208 1 SLI@ CSP2A 1 2
0_0402_5%
+5VS SW N2A <60>
0_0402_5% PR209
1 2 GFX@ GFX@ 5.49K_0402_1% G F X@
PC187 @
GFX@
PR210 .1U_0402_16V7K
10K_0402_1% PR212 2P: 36K
2 PR211 1 1 2
1P: 26.1K PUT COLSE
VR _ RDYA 0_0402_5% 36K_0402_1%
+5VS 1 PR2132 PU14 SLI@ TO V_GT
C
2_0603_5% GFX @ 6132_PW MA <60>
HOT SPOT C
+1.05VS PC188
1 2 6132 _VCC
1 45 PR214 PC189
2.2U_0603_10V7K 2 VCC PW MA 44 1 2 BSTA1 _12 1
BSTA1
PR217 VR_RDYA 3 VDDBP BSTA 43 2.2_0603_5% GFX@ +5VS
VRDYA HGA HG1A <60>
1 2VR _ON _ CPU 4 42 GFX@ 0.22U _ 0603 _ 10V7K
<45> VR_ON EN SW A SW 1A <60>
PC190 PC191 0_0402_5% VR _ SVID _ DAT1 5 41 PC192
SDIO LGA LG1A <60>
PR219
VR_SVID_ALRT# 6
ALERT# BST2
40 BST2 1 PR2182 BST2_1 2 1 2Phase: @
PR221 VR _ SVID _ CLK 7 39 4.7_0603_5%
0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 SCLK HG2 38
HG2 <60>
0.22U _ 0603 _ 10V7K Option for 1Phase: install
VBOOT SW 2 SW 2 <60>
<9> VR_SVID_DAT
1 PR220 2VR_SVID_DAT1 1 2 10K _0402 _ 1% ROSC _CPU 9
ROSC
NCP6132AMNR2G_QFN60_7X7
LG2
37
LG2 <60> 1 phase GFX
<9> VR_SVID_ALRT# CPU_B+ 1 2 VRMP 10
VRMP PVCC
36 6132P _VCCP 1 PR2232 2 1
VR _ HOT# 11 35 0_0402_5%
<9> VR_SVID_CLK VRHOT# PGND
PR222 1K_0402_1% VGATE 12 34 PC193
13 VRDY LG1 33
LG1 <60>
2.2U _ 0603 _ 10V7K +5VS CSP2A
+1.05VS VSN SW 1 SW 1 <60>
PC194 14 32
+3VS VSP HG1 HG1 <60>
DIFF _CPU 15 31 BST1 1 PR2252 BST1_1 2 1
DIFF BST1 4.7_0603_5%
PC195 0.22U_0603_10V7K

PR227 PC200 +5VS

PC196 @ 10K_0402_5% PR228
43P_0402_50V7K 3P: 73.2K
1 2 10P_0402_50V8J 1 PR2282
<45> VR_HOT#
CPU2@ 73.2K_0402_1% 2P: 41.2K 41.2K_0402_1% Option for 3Phase: @
<16> VGATE
PR229
CPU3@
CPU2@ 2 phase CPU 2Phase: install
<9> VSSSENSE
1 2 VSN 3P: 22p 6132_PW M <60>
0_0402_5% CPU3@
PC197 2P: 10p
1000P_0402_50V7K DRVEN <60>
PR232 CSP3 1 PR2312 CSP3
SW N3 <60>
1 2 VSP PC198 6.98K_0402_1%
<9> VCCSENSE
0_0402_5% 1 2
.1U_0402_16V7K
PC199
0.047U_0402_16V7K
3P: install
B 2P: @ B
CPU3@ PC200 CSP1 PR233 CSREF TSENSE
1 PR234 2 2 1 CSP2 PC208
1K_0402_1% CSP3 CSP2 1 PR2352
SW N2 <60>
22P_0402_50V8J 6.98K_0402_1%
PC201

1
PR236
2FB _CPU1 1
PC202
2 2
PR237
1COMP _CPU1 2
PC203
1
3P: 21K 12.4K_0402_1%
0.047U_0402_16V7K

PR238 PC204 49.9_0402_1% 6.04K_0402_1% 2P: 12.4K CPU2@ 1200P_0402_50V7K CSRE F

1 2FB_CPU3 1 2 470P_0402_50V7 K 2200P_0402_5 0 V7K CPU2@
10_0402_1%
CSREF <60>
0.033u_0402_16V7K CSP1 1 PR2392 PH6
SW N1 <60>
PR241 PR242 PC205 6.98K_0402_1%
TRBST# 1 2 FB _ CPU2 1 2 1000P_0402_50V7K
3P: 1500p PC206
0.047U_0402_16V7K
100K_0402_1%_TSM0B104F4251RZ

8.06K_0402_1% 806_0402_1% 2P: 1200p

PC207 CSREF
CSSUM
@
CPU3@ PC208 CPU3@
PR244 1 2 1 PR2432 SW N1
1500P_0402_50V7K 130K_0603_1% PUT COLSE
PC969@QC TO VCORE
3P: 23.7K 1 2 PC210
1 PR2452
130K _ 0603 _ 1%
SW N2
HOT SPOT
2P: 24.9K 330P_0402_50V7K
24.9K_0402_1% 1 PR2462 SW N3

CPU3@ PR247 PC212

CPU2@
1 2 PC211
130K_0603_1%
2012/05/07
CPU3@
CSCOMP 1 2 DROOP 1 2 CSREF 330P_0402_50V7K
3P: install change PR240, PR206 from 8.25Kohm to 15Kohm
PUT COLSE 2P: @
PR247 806_0402_1% 1000P_0402_50V7K PR248 PR249
<45> IMVP_IMON TO VCORE
3P: 806 Phase 1
1 2 _PH201
NTC 1 2
75K_0402_1%
2P: 1K Inductor 165K_0402_1%
A A
PH7

1K_0402_1% 2 1
CPU2@
220K _04 02_5%_ERTJ0EV224J

Security Classification LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTO DY OF THE COMPETENT DIVISION OF R & DSize Document Number Rev
C ustom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 59 of 65
5 4 3 2 1
 5 4 3 2 1

CPU_B+ CPU_B+

B+
PL14
PQ27 HCB4532KF-800T90_1812 PQ28
1 2
CPU_B+

1 1
4 4
<59> HG1 <59> HG2
+ +
+VCC_CORE +VCC_CORE
A ON6428L_DFN8-5 AON6428L_DFN8-5
PL15 2 2
D D
0.36UH_VMPI1004AR-R36M-Z03_30A_20% PL16
<BOM Structure > 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1 4 1 4
<59> SW 1 <59> SW 2
2 3 2 3

PR250 PR251
4.7_1206_5% 4.7_1206_5%
PQ29 PQ30
AON6504 1N D FN PR252 AON6504 1N D FN
4 V1N _ CPU2 1 4 V2N_CPU 2 PR253 1 CSREF
<59> LG1 CSREF <59> <59> LG2
10_0402_1%
10_0402_1%

SW N1 <59> SW N2 <59>
PC226

680P_0402_50V7K
PC227

680P_0402_50V7K

CPU_B+
PR254
BS T3 1 2 BST3 _1
4.7_0603_5%

CPU3@
PQ31
PC228
0.22U_0603_10V7K
CPU3@
4
PU15 CPU3@ CPU3@ CPU3@ CPU3@ +VCC_CORE
1 9
BST FLAG
C AON6428L_DFN8-5 C
CPU3@ 2 8 HG3 PL17
<59> 6132_PW M PW M DRVH
7
CPU3@ CPU3@ QC 45W CPU DC 35W CPU
2 PR255 1EN_CPU3 3 SW3 1 4
< 5 9> DRVEN
2K_0402_1% EN SW VID1=0.9V VID1=1.05V
+5VS 2 1VCC _CPU3 4
VCC GND
6 2 3 IccMax=94A IccMax=53A
PR256 0.36UH_VMPI1004AR-R36M-Z03_30A_20% Icc_Dyn=66A Icc_Dyn=43A
0_0402_5% CPU3@ 5 LG3 PR257
DRVL
PQ32 4.7_1206_5% Icc_TDC=52A Icc_TDC=36A
PC233 NCP5911MNTBG_DFN8_2X2 CPU3@ R_LL=1.9m ohm R_LL=1.9m ohm
2.2U_0603_10V7K AON6504 1N DFN
CPU3@
4 V3N_CPU 2 PR258 1 CSREF
OCP~110A OCP~65A
CPU3@
10_0402_1%
CPU3@
SW N3 <59>
CPU3@

PC234

680P_0402_50V7K
3Phase: install CPU3@
2Phase:: @

CPU_B+ CPU_B+

2Phase: install
B 1Phase:: @ B

BSTA2 1 PR259 2 BSTA2_1

PQ33 GFX@ GFX@ GFX@ GFX@ PQ34 GFX@ GFX@ GFX@ GFX@
2.2_0603_5%
PC240
GFX@
0.22U_0603_10V7K
4 4
<59> HG1A GFX@

PU16
AON6428L_DFN8-5 1 9 AON6428L_DFN8-5
+VCC_GFXCORE_AXG BST FLAG
PL18 2 8 HG2A GFX@ PL19
<59> 6132_PWMA PW M DRVH
0.36UH 20% PDME064T-R36MS1R405 24A GFX@ 0.36UH 20% PDME064T-R36MS1R405 24A
1 2 DRVEN 2 PR260 1EN_GFX2 3 7 SW2A 1 2 +VCC_GFXCORE_AXG
<59> SW 1A EN SW
2K_0402_1% GFX@
+5VS 2 1VCC _GFX2 4
VCC GND
6
PR262 GFX@
0_0402_5% 5 PQ36
DRVL
PQ35
GFX@
NCP5911MNTBG_DFN8_2X2 AON6504 1N DFN PR263 @
AON6504 1N DFN PC244 GFX@ 4.7_1206_5% PR266
4 2.2U_0603_10V7K LG2A 4 2 1 CSREFA
<59> LG1A
10_0402_1%

G F X@ G F X@
GFX@
2 PR267 1
CSREFA <59>
SW N2A < 5 9>
10_0402_1%

PC246 @
SW N1A <59>
680P_0402_50V7K
A A

QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A LC Future Center Secret Data Title


Icc_TDC=38A Icc_TDC=21.5A
R_LL=3.9m ohm R_LL=3.9m ohm Issued Date 2011/11/01 Deciphered Date 2012/12/31 CPU_CORE
OCP~55A OCP~40A THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14, 2013 Sheet 60 of 65
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+CPU_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 µF (0805)
PC247
Socket Bottom 5 x (0805) no-stuff
10U_0805_6.3VAM
PC248
10U_0805_6.3VAM
PC249
10U_0805_6.3VAM
PC250
10U_0805_6.3VAM
PC251
10U_0805_6.3VAM
+VCC_GFXCORE_AXG sites
2 2 2 2 2

D
7 x 22 µF (0805) D
Socket Top 2 x (0805) no-stuff
1 1 1 1 1 1
1 1 1 1 1 1 1 1
sites
PC252 PC253 PC254 PC255 PC256 PC257
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 2 2 2 2 2 2 2 2
2 2 2 2 2 2
GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@
+1.05VS
+VCC_CORE +1.05VS
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1
PC266 PC267 PC268 PC269 PC270 1 1 1 1 1 1 1 1
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2

2 2 2 2 2 2 2 2

GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@ GFX@

1 1 1 1 1 1 1 1
1 1 1 1 1
PC290 PC291 PC292 PC293 PC294
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2
2 2 2 2 2 1 1 1
+ + +

C C
2 3 2 3 2 3
PC59@DC 1 1
1 1 1 1 1 GFX@ GFX@ GFX@
+ +
PC306 PC307 PC308 PC309 PC310
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 3 2 3

PC38,PC39,PC40,PC41

1 1 1 1
PC313 PC314 PC315 PC316
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2
PC32,PC49,PC54,PC55,PC56
+VCC_CORE
PC8,PC21,PC22,PC63
PC38,PC39,PC40,PC41
1 1 1 1 1 1
+ + + + + +

B 2 3 2 3 2 3 2 3 2 3 2 B

@
CPU3@

DC:PC73,PC74,PC75,PC76,PC77,PC78(330uF/9m)
QC:PC76,PC78(470uF/4.5m),PC73,PC74,PC75(330uF/9m)

A A

Security Classification Title

2011/11/01 Deciphered Date 2012/12/31 CPU_CORE1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 61 of 65
5 4 3 2 1
 5 4 3 2 1

Charge Option() bit[8]=1

P3
B+
P2

PQ37 PQ38
AO4423L 1P SO8 AO4423L 1P SO8
8 1 1 8 PR268
VIN 7 2 2 7 0.01_1206_1% PL20 CHG_B+
6 3 3 6 1UH_PCMB061H-1R0MS_7A_20%
5 5 1 4 1 2 PQ39
AO4423L 1P SO8
2 3 1 8
D D
2 7
PC323
SH00000AA00 3 6
PQ40 2200P_0402_50V7K 5
1 2

DTA144EUA_SC70-3 DISCHG _G
1 2
PR271
PC329 @ 47K_0402_1%
2 0.1U_0603_25V7K 1 2
ACN VIN

ACP PR272
10K_0402_1%

P2-1 PR273
2 200K_0402_1%
PQ41 PQ42
PC333 PC334 DTC115EUA_SC70-3
DTC115EUA_SC70-3 +3VALW P
PR274 <54> ACPRN 1 2 2 1 PD6
5.1K_0402_5% 1SS355_SO D323-2
0.1U_0603_25V7K 2 1 2

PQ44A PC335
PQ43A 2N7002KDW -2N_SOT363-6
2 2N7002KDW -2N_SOT363-6 0.1U_0603_ 2 5V7K
2 PQ45A
BATT_OUT <53>
150K_0402_1% 2 1 2N7002KDW -2N_SO T363-6
VIN PR278 @ PR279 @
C C
2 1 1 2 2 PACIN
4.7M_0603_1% P2 PQ46
39.2K_0402_1% AON7408L_DFN8-5

PR282
10_1206_5%
PR281 PR283 <45,53> ADP_I 1 2
47K_0402_1% 64.9K_0603_1% 21 4
PACIN 1 2 5 1 2 6 TP
ACDET PC339
20 1 2
SH000005Y80
PC337 .1U_06 03_25V7K PC338
2 1 1 2 7 VCC PL21
PR284 IOUT PR285
PQ47 100P_0603_50V8 19 1U_0603_25V6 4.7UH_KJ0730-4R7M_5.5A_20% 0.01_1206_1%
0_0402_5%
PHASE
DTC115EUA_SC70-3 <45,49,53> EC_SMB_DA1 1 2 8
SDA
PU17 BATT+
PR287 BQ24737RGRR_VQFN20_3P5X3P5 LX_ CHG 1 2 CHG
1 4
PR286 0_0402_5% 18 DH_CHG
1 2ACOFF-12 <45,49,53> EC_SMB_CK1 1 2 9 HIDRV 2 3
<45> ACOFF SCL
10K_0402_5% PR288 PC340 PQ48
PR289 2.2_0603_5% 0.047U_0603_16V7K AON7702L_DFN8-5
1 2 10 17 BST _ CHG 1 2 2 1
+3VALW P ILIM BTST
PR291 147K_0402_1% PD7
0_0402_5 % 2012/02/29 PR292 16
RB751V-40_SOD 323-2
2 1
4

Add PC337 0.1uF 100K_0402_1% REGN

BQ24737_VDD

PC344
BATT _ OUT 5 1U_0603_25V6
B B

PC345 DL _ CHG
0.1U_0603_ 25V7K
2 1

PC346
0.1U_0603_25V7K
+3VS
BQ24737_VDD

PR298
10K_0402_1%
1 2
ACIN <45>
PR297
PR296 10K_0402_1%
47K_0402_1%

PACIN

PR299

ACPRN 5 12K_0402_1%

A A

For disable pre-charge circuit.

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday, January 14, 2013 Sheet 62 of 65
5 4 3 2 1
 5 4 3 2 1

D D

PCH_PWR_EN# 2

AC A1 U14,+3VALW_PCH
MODE VIN
QH4,+5VALW_PCH
A2 A3 B5
PU2 B+ PU3 A5 2
+3VALW_PCH
+3VALW B7 2 3
+5VALW_PCH
BATT BATT
MODE
B1
B2
B+ B4 V
V 4 SYS_PWROK
EC
13
PQ2 PCH_RSMRST# PM_DRAM_PWRGD
PCH
B3 A5 B7 5 14
PBTN_OUT# H_CPUPWRGD
EC_ON
CPU
51ON#
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 15
C
PM_SLP_S5# C

PM_SLP_A#
A4 B6 PM_SLP_SUS# 6

ON/OFF

SYSON 7 SYSON# +1.5V

PU5
DGPU_PWR_EN 8a (DIS) VGA_ON
+3VSDGPU
Q6 11
8
SUSP#,SUSP U49
+5VS VGATE
+1.5VSDGPU
U40
U20
+3VS +1.8VSDGPU VGA
U37
B B
U13
+1.5VS +1.0VSDGPU
PU28
PU8
+0.75V +VGA_CORE
VCCPPWRGOOD PU998
PU9 PU7
+1.05VS_VCCP +VCCSA
VGA_PWROK 8b (DIS)

U47
CK505
VR_ON 9 PU1000
+CPU_CORE 10

A A

LC Future Center Secret Data Title

Issued Date 2011/11/01 Deciphered Date 2012/12/31 Power sequence

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHO RIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y400S-NM-A141
Date: Monday , January 14 , 2013 Sheet 63 of 65
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

1 For NV suggest 58 Add (reserve parts ) PC859

D D

2 For TI suggest 58 Add (reserve parts ) PR834

7
8

C C

10

11

12

13

14

B B

15

16

17
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/10/11 Deciphered Date 2014/07/01 PIR (PWR)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cust om 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Monday, January 14, 2013 Sheet 64 of 65
5 4 3 2 1
 5 4 3 2 1

QIWY5 HW PIR List

D D

C C

B B

A A

LC Future Center Secret Data Title

Issued Date 2012/10/11 Deciphered Date 2014/07/01 PIR (HW)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cust om 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Monday, January 14, 2013 Sheet 65 of 65
5 4 1