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determined by the delay of each
inverter in the chain. The number of
Sequence stages in the ring oscillator affects its
frequency.
Generator
2. 3-Bit Counter: This counter organizes
the timing of the sequence generation.
It increments through binary numbers
Using CMOS in a specific sequence.
Combinational Logic: This logic, represented
Technology by equations like F = I2 + I1 × (I0 + 1) + 1 and
G = I2 + (I1 + 1) × (I0 + 1), processes the
inputs from the counter to generate the desired
sequence. It's designed using techniques like
Karnaugh maps.
3. Multiplexer Circuits: These circuits
Abstract— Sequence generators play a crucial
choose between the outputs of the
role in digital electronics by facilitating the
combinational logic based on a control
generation of successive integer numbers
signal. They can select either the F or
within a data flow. This article outlines the
G part of the sequence.
layout and components of a sequence
generator, which comprises four main parts: a 4. LEDs: Finally, the result of the
ring oscillator, a counter, combinational logic sequence generation is represented
circuits, and a multiplexer. The ring oscillator visually using LEDs. Depending on
produces square wave outputs utilized by the the mode of the multiplexer switch,
counter, while a 3-bit counter circuit identifies they display either the F or G part of
sequences and directs them to the the sequence.
combinational circuits. These circuits then
divide the signal based on their respective Overall, the sequence generator takes inputs
equations. Finally, the multiplexer selects from the counter, processes them through
either the F or G switch part, representing the combinational logic, selects the appropriate
signal through LEDs. output using a multiplexer, and displays the
result using LEDs.
Keywords—MOSFET, oscillator, inverter,
transistor, Karnaugh Map, Truth Table,
multiplexer, Ring Oscillator
Introduction In the context of the project, the CMOS ring
oscillator is crucial for generating the binary
signals (1s and 0s) needed for the subsequent
logic circuits. This oscillator functions by
arranging CMOS inverters in an odd number
and connecting them in series. By doing so, it
creates a square wave with a frequency within
a specific range.
To control and stabilize the oscillation
frequency, resistors and capacitors are
employed in the CMOS ring oscillator. These
components play essential roles:
In simpler terms, the sequence generator
consists of five main components:
1. Resistors: Resistors are used to
control the current flow within the
1. sbuilt using inverters connected in a oscillator circuit. By carefully
circular chain. They create a repetitive selecting resistor values, the overall
waveform with a frequency
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resistance in the circuit can be signal processing, and digital data storage
adjusted, influencing the charging and devices.
discharging rates of the capacitors
connected to the inverters. This, in In this particular project, the counter is
turn, affects the oscillation frequency implemented using flip-flops, which are basic
of the ring oscillator. building blocks of digital circuits. Flip-flops
2. Capacitors: Capacitors are store binary data and can be used to create
responsible for storing and releasing sequential circuits like counters.
electrical energy in the oscillator
circuit. They interact with the resistors There are two main types of counters based on
to determine the time constant of the their working principles:
circuit, which directly affects the
oscillation frequency. By adjusting
capacitor values, the time taken for the 1. Up Counter: This type of counter
capacitors to charge and discharge can increments its count value with each
be modified, allowing precise control clock pulse. In other words, it counts
over the oscillator frequency. upwards from a starting value to an
ending value.
2. Down Counter: Conversely, a down
Together, resistors and capacitors help fine- counter decrements its count value
tune the characteristics of the CMOS ring with each clock pulse. It counts
oscillator, ensuring it operates within the downwards from a starting value to an
desired frequency range and providing stable ending value.
binary signals for the subsequent logic circuits
in the project.
In this project, the circuit design focuses on
performing sequencing operations rather than
Circuit Diagram
simply counting up or down. The specific
sequence used in the project is: 000 -> 100 ->
101 -> 111 -> 110 -> 010 -> 011 -> 001 ->
Using LTspice for circuit simulation is a smart (repeat).
move—it allows you to verify your design
before actual implementation. When
The counter circuit facilitates this sequencing
simulating circuits with MOSFETs, it's crucial
operation by transitioning through the
to accurately input their parameters for reliable
specified binary states in the prescribed order.
results. These parameters can indeed be found
This sequential behavior is essential for
in datasheets or online resources like
controlling the logic circuits downstream and
LTwiki.com.
generating the desired output sequence.
Output Waveform and Simulation Results
Determination Of Equations
There is a 3-bit sequence that repeats in a
specific
order. First, this series was placed in the truth
table. J and
K pins on the flip-flop will be signals and their
3-bit Counter
equations
will be determined in this way. This was the
The counter in this project is a fundamental first step.
electronic component designed to facilitate Secondly, the next step of each trio was
timing, sequencing, and counting operations written in front of
within the circuit. Counters are versatile and them. In this way, J and K values were found
find applications in various fields such as with the help
automatic control systems, computer memory, of the x equation.
Page 3
since a NOT gate (74HC04) is
available, the combination of an XOR
gate and a NOT gate can be used to
perform the XNOR operation if
needed.
Table 1 : Truth Table and Excitation Table Additionally, flip-flops are required to store
One K-Map according to the K value in the and synchronize the state of the circuit. The
Truth table. At this stage, J equations and K 74LS73N chip is chosen for this purpose, as it
equations can be written. Then, for the contains dual JK flip-flops that can be
simplest equation, the X values were given a configured to suit the sequencing operation
value of 1 as shown in Table 2. Thus, the specified in the project.
equations took their final form.
By integrating these logic gates and flip-flops
into the circuit according to the generated
equations, the circuit can perform the desired
logic operations and sequencing as required by
the project specifications.
Table 2 : K-Maps and Equations for flip-flop
Equations
Designing The Counter It seems like you're describing how the
equations generated for the circuit are being
Integrating the generated equations into the translated into the actual circuit design. Let's
circuit involves implementing the logic break it down step by step:
operations specified in the equations using
appropriate logic gates. Based on the equations 1. Analysis of Equation J1: The
provided and the desired operations, the equation for J1 involves the inputs I2
following types of logic gates are identified for and I0, indicating that the output will
integration into the circuit: depend on the logical AND operation
between these two inputs. This means
1. AND Gates: Since there are four two- that when both I2 and I0 are high (1),
input AND gates required, the the output J1 will be high (1).
74HC08 chip, which contains four 2. Selection of Logic Gate: Since the
AND gates with two inputs each, is operation between I2 and I0 is an
chosen for this purpose. These gates AND operation, a two-input AND gate
will perform the logical AND is chosen to implement this logic. The
operation between the input signals as output of this AND gate will be
specified in the equations. connected to the J input of the second
2. XOR Gate: The equation mentions flip-flop.
the need for one XOR gate. The 3. Implementation for Other
74HC86 chip contains four XOR Equations: Similarly, the remaining
gates, so one of these gates can be equations are analyzed, and
utilized for this purpose. XOR gates appropriate logic gates are selected
perform the exclusive OR operation based on the operations specified in
between the input signals. each equation. For example, if an
3. XNOR Gate: Although not explicitly equation involves an OR operation, an
mentioned, an XNOR gate can be OR gate would be used, and so on.
constructed from an XOR gate 4. Connecting Outputs to Flip-Flops:
followed by a NOT gate. However, The outputs of these logic gates are
Page 4
then connected to the appropriate
inputs (J, K, etc.) of the flip-flops It seems like you're describing the process of
based on the equation requirements. obtaining new signals F and G by substituting
the 3-bit I sequence from the counter circuit
By following this process for all six equations, into two different equations. This process
the entire circuit is constructed, ensuring that likely involves evaluating the equations for F
each flip-flop receives the correct inputs based and G using all possible combinations of the 3-
on the logic operations defined by the bit sequence.
equations. This systematic approach ensures
that the circuit accurately reflects the desired Here's how this process might unfold:
behavior specified by the equations.
1. Understanding the Equations:
The Circuit and Schematic Firstly, you'll need to understand the
equations provided for F and G. These
equations likely depend on the values
of the 3-bit sequence, denoted as I2,
I1, and I0.
2. Substituting the Sequence: With the
equations in hand, you'll substitute
each of the 8 possible combinations of
I2, I1, and I0 into the equations to
determine the corresponding values of
F and G.
3. Obtaining New Signals: After
substituting all possible combinations,
you'll obtain new values for F and G
for each combination of the 3-bit
sequence.
4. Applying the New Signals: These
new values for F and G will then be
applied in the circuit, likely
Simulation Results influencing the behavior of subsequent
logic operations or determining the
states of other components in the
system.
By systematically substituting the 3-bit
sequence into the equations and evaluating
them, you'll obtain new signals F and G that
reflect the desired behavior of the circuit based
on the input sequence. This process ensures
that the circuit responds appropriately to the
changing input states from the counter circuit.
There are 3 LEDs in the
circuit diagram drawn on Proteus. In Picture 2, Determination of Equation
you can see which signal these LEDs belong
to. According to the desired order, which LED It seems like you've already solved the
will turn on also be controlled from the equations for F and G based on the truth tables
adjacent table (R: red, Y: yellow, G: green). provided, and you've converted the results into
You can access the video showing the binary format. Let's summarize the process
simulation results from the link below. and the results:
Combinational Logic Circuits
1. Equations:
Page 5
F = I2 + I1 × (I0 + 1) + 1
G = I2 + (I1 + 1) × (I0 + 1)
2. Truth Tables:
You've likely created truth
tables for F and G, listing all
possible combinations of I2,
I1, and I0, and determined the
corresponding values of F and
G based on the equations.
3. Results:
The results column in the
adjacent table likely shows the
values of F and G obtained
from the truth tables.
4. Conversion to Binary:
You converted the decimal
values obtained for F and G
into binary format to represent
them in the table.
5. Interpretation:
By analyzing the results in the
table, you can determine under
which conditions the signals F
and G are active or inactive.
This provides insight into how
the circuit behaves based on Truth Table – Combi_F is Top.
the input conditions. Combi_G is Bottom.
6. Boolean Equations:
From the process, you've It sounds like you and your group have
derived Boolean equations for efficiently optimized the circuit design by
F, G, and potentially other simplifying the Boolean equations using
signals in the circuit. These Karnaugh maps (K-maps) and eliminating the
equations represent the logical need for inverters. Let's summarize the process
relationships between the and its benefits:
input signals and the output
signals, allowing you to 1. Simplification with K-Maps:
understand and manipulate the K-maps are powerful tools for
behavior of the circuit. simplifying Boolean equations
by identifying and grouping
By following this process, you've successfully adjacent minterms to
determined the conditions under which the minimize the number of terms
signals F and G work, allowing you to in the equations.
effectively design and implement the logic By using K-maps, you were
circuit based on these conditions. able to reduce the complexity
of the Boolean equations for
the signals, leading to simpler
circuit designs.
2. Removal of Inverters:
Since the output of the circuit
needed to be the inverse of the
signal, you initially considered
using inverters.
However, instead of using
inverters, you and your group
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designed the circuit based on
the inverse of the signal itself.
By designing the circuit in this
way, you eliminated the need
for inverters altogether,
resulting in a more
streamlined and efficient
design. M inimization for Combi_G.
3. Transistor Savings:
Circuit Diagrams
By removing the need for
inverters, you saved a According to CMOS Configuration, PMOSs
significant number of are connected in parallel for multiplication and
transistors in the circuit. in series for addition. NMOSs are connected in
Specifically, you saved 12
series for multiplication and in parallel for
transistors for each signal that
required an inverter, resulting addition. Also, Source of PMOS is connected
in a total saving of 12 × 6 = 72 to VDD, Source ofNMOS is connected to
transistors. GND. In picture 1 and picture 2 above, it is
Additionally, by simplifying possible to see according to which equations
the Boolean equations using the circuits are designed. This design inverts
K-maps, you further reduced the Boolean Equation for which it was
the number of transistors designed. This is why our equations are
required in the circuit by 64 designed according to the inverse.
transistors.
4. Overall Efficiency:
By optimizing the circuit
design through simplification
with K-maps and eliminating
inverters, you achieved a more
efficient use of resources,
reducing both the complexity
and the transistor count of the
circuit.
This approach demonstrates effective problem-
solving and optimization techniques, leading
to a more streamlined and cost-effective circuit
design. Well done! circuits of F’ Signals
Minimization for Combi_F
signals.
Circuits of G’ Signals
Simulation Results
For better understanding, the signal values
were
Page 7
written as 0 and 1. As can be seen, an exact VCC pin is connected to the
match with the truth table h as been achieved. positive supply voltage
The period of our signal was 80ms so that after (usually 5V).
the first period it repeats itself accordingly. GND pin is connected to
This shows that the circuits are working. ground (0V).
2. Enable Connection:
The enable pin is connected to
ground to enable the operation
of the multiplexer.
3. Input Signal Connections:
For the 3-bit signal, pins 1, 2,
and 3 on the chip are used.
F signals (F1, F2, F3) are
connected to the "A" pins of
Comparison of Truth Table and Simulation of the multiplexer.
Combi_F F2 is connected to the
1st pin.
F1 is connected to the
2nd pin.
F0 is connected to the
3rd pin.
G signals (G1, G2, G3) are
connected to the "B" pins of
the multiplexer.
G2 is connected to the
1st pin.
Comparison of Truth Table and Simulation of
G1 is connected to the
Combi_G
2nd pin.
G0 is connected to the
Multiplexer
3rd pin.
In this section, it was the subject of showing
only
one of two different signals as output using By making these connections, you've
MUX. The generated F and G signals are configured the multiplexer chip to select
transmitted to the LEDs according to the between the F and G signals based on the
position of the switch. The switch has 3 pins. control input. This setup allows you to choose
The middle pin is connected to the switch pin which signal is transmitted to the output of the
on the chip, one of the other two pins is multiplexer, which is then displayed on the
connected to ground for s' and the other to a 5v LEDs based on the position of the switch.
source for s. The IC Chip used is 74HC157N. The Multiplexer was first set up according to
the
Design of The Circuit CMOS configuration. The IC Chip model was
preferred during the assembly phase of the
circuits.
The Pinout of MUX Chip Spice Model of The Circuit
1. Power and Ground Connections: Simulation Procedures and Truth Table
Page 8
Conclusion
You
In our sequence generator project, we first
learned how to design a CMOS circuit using
NMOS and PMOS, and to establish a ring
oscillator circuit by calculating frequency
Circuit Diagram of The Transistor Level MUX using CMOS. In this way, we converted our
signal into a square wave. In the ring oscillator
section, we had some problems due to the
breakdown of our transistors and lack of
contact. We also had the opportunity to see the
difference between the calculated value and
the actual value. In the 3bit counter section, we
learned how to put our signal in an order.
Using K-map and other applications, we
designed it with IC chips according to the
sequence given in the task. In the flip flop
section, we fed our chip with the CLK signal
from the ring oscillator. We created our
combinational f and combinational g parts by
using the I2 I1 and I0 signals we obtained in
the counter section in the F and G equations
Simulation Waveform given in the counter section. We set up this
part first with the transistor in task 3 and then
In Picture 16, the V (green signal) is the with the chip in the final part. We had loose
switch. contact problems here too. Some of our cables
V_a represents the F signal. V_b represents the and chips were broken, which affected our
G signal.The equation of this 2to1 Multiplexer, circuit. Then, in our circuit, we decided to
which consists of two AND Gates and one OR switch with a multiplexer part and use this
Gate, circuit to get the signal and sequence of the
combinational f or combinational g circuit.
Lastly, we showed this result with LEDs.
While building this circuit, we learned to set
up logic circuits in general, to k-map, and to
put our signals in an order. One of the most
important parts for us was to control the chips
we had before installing the circuit.
References
[1] “What is a Sequence Generator and Its
Working”
https://www.elprocus.com/what-is-a-sequence-
generator-and-its-
working/
[2] Rabaey, J. M., Chandrakasan, A. and
Nikolic, B. (2004)., Digital integrated
circuits- A design perspective, Prentice Hall.
[3] Mandal,M. K., Sarkar,B. C.,2010 Ring
oscillators: Characteristics and
Page 9
Applications,https://www.researchgate.net/
publication/234046858_
Ring_oscillators_Characteristics_and_applicati
ons
[4] Rajmohan,V.,Ranganathan, V.,2011
Design Of Counters Using Reversible
Logic,https://doi.org/10.1109/
ICECTECH.2011.5941973
[5] Mano, M. M., Ciletti, M. D.,(2019),
Digital Design With an Introduction to the
Verilog HDL, VHDL, and SystemVerilog , 6th
Edition, Pearson Education.
[6] Hudson, W.B., Beasley, J.S., Steelman,
J.E., (1995), A CMOS combinational circuit-
design method using mixed logic concepts,
https://doi.org/10.1109/13.406505
[7] “74HC157 Quad 2×1 Multiplexer IC
Pinout Diagram”
https://microcontrollerslab.com/74hc157-
quad-2x1-multiplexer-ic/
