TM

82C52 Programmable UART

Application Note March 1997 AN108.1

PAGE
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.0 GLOSSARY OF DATA COMMUNICATION TERMS . . . . . . . . . . . . . . . . . . . . . 4
1.1 Clear to Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Data Set Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Data Terminal Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Framing Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Interrupt Driven I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 I/O Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.7 Overrun Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.8 Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.9 Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.10 Percentage Error in Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.11 Request to Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.0 CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 UART Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Baud Rate Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.0 STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 UART Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Modem Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.0 TRANSMIT/RECEIVE BUFFER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Receiver Buffer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Transmitter Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.0 I/O MAPPED ADDRESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 I/O Mapped Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Memory Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 I/O Addressing for the 82C52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.0 RESET OF THE 82C52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.0 PROGRAMMING THE 82C52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1 1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2001. All Rights Reserved
 Application Note 108

Introduction 1.3 Data Terminal Ready (DTR):

The 82C52 CMOS Programmable UART can be utilized for This is an output signal generated by the 82C52. Its purpose
serial communications at data rates from DC to 1M baud is to inform the target (i.e. modem) that it is ready for
using clock speeds in the range of 0-16MHz. In addition, the communications.
device provides an internal baud rate generator. 1.4 Framing Error:
In the following discussion, we will look at the functional Each time the 82C52 receives a character of data, it will
capabilities of the 82C52, and give information on how the check for 3 types of errors: (1) Parity error, (2) Framing error,
device can be programmed. The following topics will be and (3) Overrun error.
discussed:
When reading characters through the Serial Data In (SDI)
(1) Glossary of communications terms pin, the 82C52 will first encounter a start bit. This start bit is a
(2) Control registers logical zero, and is detected by the first falling edge of the
signal on SDI. Next, the 82C52 will see a specified number
(3) Status registers of data bits followed by the parity bit. The parity bit is
(4) Transmit/Receive Buffer Registers checked for a parity error (see 1.8 and 1.9). The stop bits are
then checked for a framing error.
(5) I/O Addressing methods
A framing error occurs when an incorrect stop bit is found, or
(6) Reset of the 82C52 if there are too few stop bits. This happens most often when
the baud rates between the communicating devices differ.
(7) Programming the 82C52
The data will have a tendency to become skewed. For
information on this skewing problem, see 1.10.
1.0 Glossary of Data Communication
1.5 Interrupt Driven I/O:
Terms
This is a method of handling interaction between a CPU and
1.1 Clear to Send (CTS):
an I/O device. In this scheme, the I/O device will issue an
Clear-to-send is an input signal to the 82C52. It is provided interrupt to the CPU when it requires attention.
by the device with which the 82C52 is communicating, such
With the 82C52, an interrupt might occur when (1) the device
as a modem. When this signal is in its active state (active
receives a character on its SDI pin, (2) the device completes
low), the 82C52 is being told that the modem will accept data
transmission of a character, (3) an error is found in a
sent to it from the 82C52 Serial Data Out (SDO) pin.
received character, or (4) a change was detected in one of
The CTS signal is specified in the RS-232C protocol and is the modem control lines.
used in conjunction with the Request to Send (RTS) signal. After the interrupt is recognized by the CPU, it (the CPU) will
This signal is used mainly in half-duplex systems. In a half- go to the corresponding Interrupt Service Routine(ISR). This
duplex system communications can be performed in both routine decides how the interrupt should be serviced, and
directions, but in only one direction at a time. then services it. Upon completion of the ISR, execution of
To illustrate this: Suppose we are using the 82C52 to the user’s software will resume at the point where the
communicate over an RS-232C link to a modem. In half- interrupt occurred.
duplex operation the UART tells the modem that it wishes to 1.6 I/O Polling:
transmit a character by putting RTS into its active state
(active low for the 82C52). The modem, if ready for the data, A second method for handling interaction between a CPU
will respond by driving the 82C52’s CTS line to its active and an I/O device. Rather than waiting for an I/O device to
state (low). When the 82C52 recognizes this, it will then interrupt the CPU, the software assumes the responsibility of
begin data transmission. checking to see if an I/O device needs servicing.

1.2 Data Set Ready (DSR): When the system software needs to output to the 82C52, it
will poll (look at) the device to see if it is ready to accept
This is also an input signal to the 82C52. When in its active data. Similarly, in order to receive data from the 82C52, the
state, it signifies that the device with which it is to communi- software will poll to see if there is any data waiting to be read
cate is powered on and ready for communications. When in. Once read, the software must test the status of the 82C52
using a modem, an active state for this signal indicates that to see if any errors were detected in the data received. The
the modem is also connected to a communications line (is software must also look for status changes in the modem
on line). control lines.

2
 Application Note 108

1.7 Overrun Error:

(EVEN) (ODD)
With the 82C52, data is received on the SDI pin. From there CHARACTER SENT PARITY BIT PARITY BIT
it is shifted serially into the Receiver Register. Once in this 01101110 1 0
register, it will be shifted (in parallel) into the Receive Buffer
Register (RBR) should this register be empty. Should it not 11111010 0 1
be empty, the data cannot be shifted into the RBR. However, FIGURE 1. PARITY
subsequent data coming in on the SDI pin will be shifted into
the Receiver Register, overwriting the data already there. 1.9 Parity Error:
This causes the 82C52 to flag an overrun error. This is caused by an invalid parity bit being detected in a
character received. The condition occurs when (A) even par-
To clear the RBR, data must be read from it by the CPU. This
ity is specified and an odd number of ‘one’ bits are detected
data must be read faster than the data is being received on
in the character, or (B) odd parity is specified and an even
SDI and written to the Receiver Register. In most cases, this
number of ‘one’ bits are detected.
problem must be dealt with in software: (1) Either the
receive data routine must be optimized for better perfor- For example, if the character 6EH (01101110 b) is received
mance, or (2) The baud rate must be lowered to compensate by the device, and the parity bit read in is a 1, a parity error
for the data loss. would be flagged if parity was defined to be ODD. Should
parity be set to EVEN and the parity bit is a 1 for this same
1.8 Parity:
character, a parity error will not be flagged.
Parity is a form of error detection commonly used in serial
1.10 Percentage Error in Baud Rate Generation:
communications. In parity checking, the sending device gen-
erates and sends an extra bit with each character transmit- When exchanging data between two systems through serial
ted. The state of this bit (0 or 1) is determined by (1) the links (i.e., RS-232C) it is important that the baud rates of the
number of 1 bits in the character transmitted, and (2) by two systems be as equal as possible. Roughly speaking,
whether parity was defined to be even or odd. these baud rates should not differ by more than 2%. For
example, if system X is using an 82C52 to generate 1200
With even parity, the parity bit is generated such that the
bits per second (bps), and system Y with which it is commu-
number of one’ bits in the character (including the parity bit)
nicating is generating 1244bps, there is a 3.67% difference
is an even number. For example, if a word has 5-bits that are
in the baud rates. Errors may occur when data is received by
ones, the parity bit must be set to a one so that the total
system X.
number of ‘one’ bits is an even number. If a character being
sent has 6-bits set to a one, the parity bit will be zero. This The 82C52 samples the data being received on the SDI pin
still gives an even number of one bits in the character. beginning from when the receiver detects a start bit. This is
denoted by a high-to-low transition on the SDI pin. Based on
Conversely, in odd parity, the parity bit is generated such that
the specified baud rate, the 82C52 will count and sample
the total number of 1 bits (including the parity bit) is an odd
such that each bit is read at the center of a bit period.
number. For a character having 5 one bits, the parity bit gen-
Figure 2 shows a character generated at 1200bps, and sam-
erated is a zero. For a character having 6 one bits, the parity
pled for 10-bit periods (S0 - S10). The character is 1B Hex
bit is set to one
with even parity.

(A)
>1200bps

START DATA PARITY STOP

BIT BITS BIT BIT(S)

1200bps LSB MSB

<1200bps

S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10

START BIT
DETECTED HERE

FIGURE 2. PERCENTAGE ERROR

3
 Application Note 108

Assume that system X is configured to transmit and receive to be transmitted or received. The format of these characters
at 1200bps. The system we are communicating with is are made up of (1) a specific word length, (2) parity informa-
running slightly faster as stated above (1244bps). Our tion, and (3) a selected number of stop bits, used to indicate
sampling rate will still be based upon 1200bps, but the transmission of that character is completed.
sampling of the incoming signal will be off by a short time
period. With each sample this error accumulates. Thus, the D7 D6 D5 D4 D3 D2 D1 D0
skewing to the right becomes greater over time. By the time
STOP BIT 0 = 1 STOP BIT
we normally would be sampling the parity bit (S9), the stop SELECT 1 = 1.5 STOP BITS (TX) AND
bit(s) would be coming in over the SDI pin (see Figure 2A). 1 STOP BIT (RX) IF 5 DATA
In this case, the 82C52 thinks it is sampling the parity bit BITS SELECTED
when in fact, what it is seeing is really the stop bit. This could PARITY 000 = TX AND RX EVEN
CONTROL 001 = TX AND RX ODD
cause a parity error to be flagged. 010 = TX EVEN, RX ODD
011 = TX ODD, RX EVEN
Conversely, if data is being received at a baud rate slightly 100 = TX EVEN, RX CHECK
less than our specified baud rate, we would get a skewing of DISABLED
the received data in the opposite direction. From Figure 2C, 101 = TX ODD, RX CHECK
DISABLED
we see that at S10 we are checking the stop bit, but system 11X = GENERATION AND
Y is still transmitting the parity bit. Therefore, the Framing CHECK DISABLED
error will be flagged. WORD 00 = 5-BITS
LENGTH 01 = 6-BITS
1.11 Request To Send (RTS): SELECT 10 = 7-BITS
11 = 8-BITS
This signal is an output of the 82C52. It is used to inform a RESERVED SET TO 00 FOR FUTURE
modem or remote system that it wishes to transmit data. The PRODUCT UPGRADE
modem (remote system) would then respond by activating COMPATIBILITY

the CTS signal. As with the CTS, this signal is of most value FIGURE 3. UCR FORMAT
in half-duplex communications.
D0 – Stop Bit Select. This bit is used to select the number
of stop bits that the 82C52 will insert into a character to be
2.0 Control Registers transmitted, and the number to look for in received charac-
In order for the 82C52 to properly operate in a system, it ters. The stop bit(s) denote where the end of a character
must be configured for the desired form of operation. The occurs. The external device must be configured with the
user must decide how the device will be used in the system, same number of stop bits as the 82C52. The setting(s) for
and know the communications protocol of the device it will this bit are as follows:
be communicating with. For example, in a system communi- 0 – If this bit is set to zero, then a single stop bit will be gen-
cating with a modem we would need to utilize the modem erated and checked for.
control lines. When using the 82C52 in a local area network
these modem control lines may be of no use to us. 1 – Setting this bit to a one will cause either of two configura-
tions. If we select a character length of 5 data bits, the
The 82C52 is initialized and configured by writing a series of 82C52 will generate 1.5 stop bits during transmission,
control words from the CPU to various control registers in and will look for a single stop bit when receiving data. If a
the device. These registers include the UART Control Regis- character length of 6, 7, or 8 data bits is selected, then
ter (UCR), the Baud Rate Selector Register(BRSR), and the two (2) stop bits will be generated and checked for.
Modem Control Register (MCR).
D3, D2 and D1 – Parity Control. These three bits are used
UCR: Defines the format of characters being transmitted. to control the generation and checking of the parity bit. The
The format of the characters includes the number of 82C52 can be configured to perform this function one of
data bits, parity control, and the number of stop bits. seven ways. These are:
BRSR: Used in setting up the internal baud rate generator in 000 – Even parity is generated for transmitting data, and
the 82C52 for a specific baud rate. It will also be will be checked for when receiving data.
used to specify what the CO output is to be.
001 – Odd parity is generated for transmitting data, and
MCR: Defines which interrupts will be enabled, and will also checked for during data reception.
set the modem control output lines (RTS and DTR).
In addition, the MCR allows the user to select one of 010 – Even parity is generated for data transmission, and
four modes of communications (normal mode, echo odd parity will be checked for during data reception.
mode, transmit break, and loop test mode).
011 – Odd parity is generated for data transmission, and
2.1 UART Control Register even parity will be checked for during data reception.
The UART Control Register (UCR) is a write-only register. 100 –Even parity is generated for data transmission, how-
Writing a command word to the UCR configures the trans- ever, the 82C52 will do no parity checking on data that has
mission and reception circuitry of the 82C52. The command been received.
word essentially describes the format of characters that are

4
 Application Note 108

101 – Odd parity is generated for data transmission. The The 16X clock speed can be output to the CO pin of the
82C52 will not check parity on data received. device through the CO Select function of the BRSR. If CO
select is not selected, the output of the CO pin will reflect the
11X – The generation of a parity bit is disabled. Also, the
crystal frequency input by the part on the IX pin. Note, this
82C52 will not check for parity on incoming data. D1
output (CO) is a buffered version of the IX input or 16X baud
is not used therefore, it can be either a 0 or a 1.
rate.
TABLE 1. PARITY SELECTION
D7 D6 D5 D4 D3 D2 D1 D0
TRANSMITTER RECEIVER

000 Even Even PRESCALER 00 = ÷ 1

SELECT 01 = ÷ 3
001 Odd Odd 10 = ÷ 4
11 = ÷ 5
010 Even Odd DIVISOR 00000 = ÷ 2
SELECT 00001 = ÷ 4
011 Odd Even 00010 = ÷ 16/3
00011 = ÷ 8
100 Even Disabled 00100 = ÷ 32/3
00101 = ÷ 16
101 Odd Disabled 00110 = ÷ 58/3
00111 = ÷ 22
11X Disabled Disabled 01000 = ÷ 32
01001 = ÷ 64
01010 = ÷ 128
D5, D4 – Word Length Select. The state of these bits deter- 01011 = ÷ 192
01100 = ÷ 256
mines the number of bits that are transmitted as a data word.
01101 = ÷ 288
The word length can be 5, 6, 7, or 8-bits long. 01110 = ÷ 352
01111 = ÷ 512
TABLE 2. WORD LENGTH SELECTION 10000 = ÷ 768
11111 = ÷ EXTERNAL (÷ 1)
D5 D4 WORD LENGTH
CO SELECT 0 = IX OUTPUT
0 0 5-Bits 1 = BRG OUTPUT

0 1 6-Bits
FIGURE 4. BRSR FORMAT
1 0 7-Bits
D1 and D0 – Prescaler Select. This allows the user to
1 1 8-Bits
choose one of four values that the input clock frequency (IX)
will be divided by.

D7, D6 – Reserved. These bits have been reserved for TABLE 3. PRESCALER SELECTION
future product upgrade compatibility. To insure that the future
upgrades of the 82C52 will operate with existing software, PRESCALER
D1 D0 DIVISOR
these bits must both be set to zero (00).
2.2 Baud Rate Select Register 0 0 ÷1

The Baud Rate Select Register (BRSR) is a write-only 0 1 ÷3

register used to set the internal 82C52 baud rate generator
to the desired data transfer rate. Essentially, this baud rate 1 0 ÷4
will depend upon the clock speed of the crystal being used
with the device. However, to provide more flexibility, the 1 1 ÷5
82C52 provides two separate counters for selecting a divide
ratio to fit the user’s needs.
These two counters are the Prescaler, and the Divisor
select. The Prescaler allows the input clock rate to be
divided by one of four values: 1, 3, 4, and 5. This new data
rate can then be further divided by using the values available
with the Divisor select. This final clock speed will be 16 times
the actual baud rate used by the 82C52.

5
 Application Note 108

D6, D5, D4, D3, and D2 – Divisor Select. The state of these NOTE: All baud rates are exact except for:
bits determines the value of the Divisor select. The possible
values are as follows in Table 4: TABLE 6. PERCENT DIFFERENTIAL

TABLE 4. DIVISOR SELECTION BAUD RATE ACTUAL % DIFFERENCE

D6 - D2 DIVISOR 2000 1986.2 0.69%
00000 ÷2
800 1745.45 3.03%
00001 ÷4
134.5 133.33 0.87%
00010 ÷16/3
110 109.09 0.83%
00011 ÷8
00100 ÷32/3
To illustrate how a baud rate can be determined, let us look
00101 ÷16 at the following example:
00110 ÷58/3
EXAMPLE 2.1:
00111 ÷22
01000 ÷32
Assume that we are using a clock frequency of 2.4576MHz
with the 82C52, and we wish to configure the device to run at
01001 ÷64 a baud rate of 9600 bits per second (bps). First, select a
01010 ÷128 prescaler of divide-by-four. Therefore, bits D1 and D0 will be
01011 ÷192 set to 1 and 0. This will give an effective clock frequency of
614,400Hz.
01100 ÷256
01101 ÷288 Next, look at Table 5 to determine which divisor is needed to
generate 9600 bps. The divisor is four (4). Bits 6 through 2
01110 ÷352
will be set to 0 0 0 0 and 1. The 614,400Hz clock has then
01111 ÷512 been divided by 4 to give the appropriate 16X clock, which is
10000 ÷768 153,600HZ (16 x 9600).
11111 ÷1 To determine what the actual baud rate is, take 153,600Hz
and divide it by 16. This will give us our 9600 bits per second
y using a crystal or external frequency with one of the
(bps). A 16X clock rate is required by the internal circuitry of
common crystal frequencies (1.8432MHz, 2.4576MHz, or
the 82C52. That is why the prescaler and divisor are
3.072MHz) and a prescaler of divide by 3, 4, or 5 respec-
selected to yield a clock rate that is 16 times the desired
tively, standard baud rates can easily be generated by
baud rate.
selecting the Divisor as shown in Table 5 below:
TABLE 5. STANDARD DIVISORS Finally, set the CO Select bit to 1 so that the CO output will
be the same as the BRG output. This is the 16X frequency
BAUD RATE DIVISOR calculated above (153,600Hz).
38.4K External
The command word written to the BRSR will be:
19.2K 2
10000110 or 86 Hex
9600 4
7200 16/3 D7 – CO Select. This tells the 82C52 what the source will be
for the output pin CO.
4800 8
3600 32/3 0 – The output on CO will be a buffered version of the clock
input (IX) to the device. The frequency of this signal will
2400 16
be the actual crystal frequency (or external frequency)
2000* 58/3 used to run the 82C52.
1800* 22
1 – The output of CO will be a buffered version of a clock
1200 32 rate that is 16 times the actual baud rate generated by
600 64 the 82C52. This signal is suitable for driving a second
300 128
82C52 or UART in a system.

200 192 2.3 Modem Control Register

150 256 The Modem Control Register (MCR) is a general purpose
134.5* 288 register controlling various operation parameters within the
device. These parameters include: (1) setting modem control
110* 352
lines RTS and DTR, (2) Enabling the interrupt structure of
75 512 the device, (3) enabling the receiver on the device, and (4)
50 768 selecting one of four operating modes in the device

6
 Application Note 108

back in any form or fashion between the serial data

D7 D6 D5 D4 D3 D2 D1 D0
input pin and the serial data output pin (see Figure 6A).
REQUEST TO 0 = RTS OUTPUT HIGH 01 – Transmit break - Selecting this mode of operation will
SEND (RTS) 1 = RTS OUTPUT LOW cause the transmitter to transmit break characters only.
DATA 0 = DTR OUTPUT HIGH A break character is composed of all logical zeros for
TERMINAL 1 = DTR OUTPUT LOW the start, data, parity, and stop bits.
READY
(DTR) 10 – Echo mode - When this is selected, the 82C52 will
retransmit data received on the SDI pin out to the SDO
INTERRUPT 0 = INTERRUPTS ENABLED
ENABLE 1 = INTERRUPTS DISABLED pin. In this mode of operation, any data written to the
(INTEN) Transmitter Buffer Register will not be sent out on the
MODE SELECT 00 = NORMAL
SDO pin (See Figure 6B).
01 = TRANSMIT BREAK 11 – Loop Test mode - If this mode is selected, the data that
10 = ECHO MODE
normally would be transmitted is internally routed back
11 = LOOP TEST MODE
to the receiver circuitry. The transmitted data will not
RECEIVER 0 = NOT ENABLED appear at the SDO pin. Also, data that is received on
ENABLE (REN) 1 = ENABLED
the SDI pin will be ignored by the device. This mode of
MODEM 0 = NOT ENABLED operation is useful for performing self test(s) on the
INTERRUPT 1 = ENABLED device (see Figure 6C).
ENABLE (MIEN)

MUST BE SET TO A LOGIC 0 82C52

FOR NORMAL 82C52 OPERATION
SERIAL DATA FROM
FIGURE 5. MCR FORMAT TRANSMITTER REGISTER SD0
D0 – Request to Send. This bit allows the user to set the
state of the RTS output pin. This pin is used as a modem
control line in the RS-232C interface protocol. It is important SERIAL DATA TO
SD1
RECEIVE REGISTER
to remember that the RTS output pin is active low.
0 – Setting this bit to a zero causes a one (1) to be output on
the RTS pin. In effect, this is setting the pin to its logical FIGURE 6A. NORMAL MODE
false state.
82C52
1 – If this bit is set to a one, the RTS pin will be forced to a
zero (0). This puts the RTS signal in its logical true state. SD0

D1 – Data Terminal Ready. This is a modem control line for

an RS-232C- like interface. It is an output pin and is also SERIAL DATA TO
active low. RECEIVE REGISTER SD1

0 – A zero in bit D1 causes DTR pin to be put in a logical

FIGURE 6B. ECHO MODE
false state. The DTR pin outputs a one (1).
1 – By writing a one to this bit, the 82C52 DTR output pin is 82C52
set to its logical true state (zero).
SERIAL DATA FROM
SD0
D2 – Interrupt Enable (INTEN). This bit is an overall control TRANSMITTER REGISTER
for the INTR pin on the 82C52. With it, all 82C52 interrupts to
the processor can either be enabled or disabled. When D2 is
SERIAL DATA TO
reset to disable interrupts, no status changes including RECEIVE REGISTER SD1
modem status changes can cause an interrupt to the
processor.
FIGURE 6C. LOOP TEST MODE
0 – Interrupts are disabled. The INTR pin will be held in a
FIGURE 6. OPERATING MODES
false state (low) so that no interrupt requests to the
processor are generated. D5 – Receiver Enable (REN). Controls the reception of data
1 – Interrupts are enabled. Interrupts will be discussed in through the SDI pin into the Receiver Register. Disabling the
more detail later. receiver is useful when performing a software reset on the
device. This locks out any errant data from being received.
D4 and D3 – Mode Select. These two bits allow the user to This would also prevent interrupts from occurring due to data
select one of the four possible operating modes for the reception. Other possible reasons for disabling the receiver
82C52. These are: might be so that sections of software can execute without
00 – Normal mode - The 82C52 is configured for normal full interruption, so that software only accepts data when ready
or half duplex communications. Data will not be looped for it, or so that a software reset/reconfiguration can be
performed.

7
 Application Note 108

0 - A zero for this bit prevents the device from recognizing

D7 D6 D5 D4 D3 D2 D1 D0
data sent to the SDI pin. The receive circuitry will remain
in an idle state. PARITY ERROR 0 = NO ERROR
(PE) 1 = ERROR
1 - Writing a one to this bit enables the receiver. Data will
then be recognized at the SDI pin. FRAMING 0 = NO ERROR
ERROR (FE) 1 = ERROR
D6 – Modem Interrupt Enable. Enabling this bit will allow OVERRUN 0 = NO ERROR
any change in the modem status line inputs (CTS and DSR) ERROR (OE) 1 = ERROR
to cause an interrupt. The Modem Status register (MSR) will
RECEIVED 0 = NO BREAK
contain information pertaining to which condition(s) caused BREAK (RBRK) 1 = BREAK
the interrupt.
MODEM 0 = NO STATUS CHANGE
0 - Modem interrupts not enabled. STATUS (MS) 1 = STATUS CHANGE

TRANSMISSION 0 = NOT COMPLETE

1 - Modem interrupts enabled.
COMPLETE (TC) 1 = COMPLETE
D7 – This bit must always be set to a logic zero to insure TRANSMITTER 0 = NOT EMPTY
device compatibility for future product upgrades. Should this BUFFER 1 = EMPTY
bit be set to a one (1) during initialization, the device will not REGISTER
EMPTY (TBRE)
respond to any data at the SDI pin, and no data will be
transmitted from the Transmitter Register to the SDO pin. DATA READY (DR) 0 = NOT READY
1 = READY

3.0 Status Registers FIGURE 7. USR FORMAT

In addition to the various Control registers, the 82C52 has 0 – No error detected.
two read only status registers that can be accessed by the
CPU to determine the status of the device at any given time. 1 – Parity error detected.
These are the UART Status Register (USR), and the Modem D1 – Framing error (FE). A one in this bit indicates that the
Status Register (MSR). The registers are used for keeping last character received contained an improper number of
track of any changes in (1) the modem lines on the device stop bits. This might be caused by no stop bits being sent, or
(2) the status of data transmission or reception, and (3) by the length of the stop bits being too short.
whether any error(s) were detected in received data.
0 – No framing error.
The USR deals with the different types of data errors, the
status of data transmission, as well as data waiting to be 1 – Framing error detected.
read. The MSR, on the other hand, reflects the status of the D2 – Overrun error (OE). When this status bit is set to a
various modem control lines in the device (i.e. CTS and one, it indicates that data in the RBR is not being read by the
DSR). CPU fast enough to permit data in the Receiver Buffer to be
Normally, in an interrupt-driven system, after an interrupt shifted to the RBR before the next character comes in on the
occurs, the user’s software would check the status SDI pin. Data is then lost because it is overwritten by
register(s) to determine what caused the interrupt. The incoming characters.
software then should deal with the various types of interrupts 0 – No overrun error detected.
in an appropriate manner.
1 – Overrun error detected.
3.1 UART Status Register
D3 – Received Break (RBRK). This status bit indicates that
The UART Status Register (USR) contains information the last character received was a break character. A break
pertaining to the status of the 82C52 operation. The character consists of all logic zeros including the parity and
information that is kept in the USR includes: data reception stop bits. The most common usage of this character is to
error information, modem status, and the status of data indicate a special condition in the communications taking
transmission. This register will normally be the first 82C52 place. For example, the device sending information to the
register read when servicing an 82C52 interrupt, or when 82C52 might send a break character to it to indicate that it
polling the device. has completed transmitting its stream of data.
NOTE: The USR will be cleared upon reading its contents.
0 – No break.
After reading and clearing the status register, the bits will
remain as zeros until a status change occurs to set the 1 – Break detected.
proper bit(s). D4 – Modem Status (MS). This bit indicates whether or not
D0 – Parity error (PE). This bit indicates whether a parity there has been a change in the states of any of the modem
error was detected in the last character read into the control lines on the device. These lines include: CTS and
Receive Buffer Register. If parity is disabled, this bit will DSR. To determine which of these lines has changed, the
always be a zero. user can read the Modem Status Register (MSR).

8
 Application Note 108

Also, should both the MIEN and INTEN bits be set in the A change in any of the status bits will cause an interrupt if
MCR register, an interrupt will be generated when the MS bit the INTEN and MIEN bits of the MCR are enabled.
gets set.
D7 D6 D5 D4 D3 D2 D1 D0
0 – No status change.
1 – Status change detected. CLEAR TO SEND (CTS) 0 = FALSE
1 = TRUE
D5 – Transmission Complete (TC). When a character is
DATA SET READY (DSR) 0 = FALSE
written to the 82C52 Transmitter Buffer Register (TBR), it will 1 = TRUE
be transferred to the Transmitter Register before actually
being shifted out serially through the SDO pin. When the 0

character has finally been transmitted on SDO, and both the 0

TBR and Transmitter Registers are empty, the TC bit will be
UNDEFINED
set.
FIGURE 8. MSR FORMAT
NOTE: The TC bit getting set does not always mean that an end of
transmission has occurred. It indicates that both the TBR and the D0 – Clear to Send (CTS). This is both a status and control
Transmitter Register are empty. For instance, if we are running the signal from the modem. It tells the 82C52 that the modem is
82C52 at a high baud rate, it could transmit data faster than the us-
ready to receive data from the 82C52 transmitter output
er’s software can write characters to the device. In this case, the TC
bit could get set between each character being transmitted.
(SDO). If this line is inhibited (false), then the 82C52 will not
be able to begin transmission of data. Should this line go
Assertion of this bit will cause an interrupt when the INTEN false in the middle of a transmission, the UART will only be
bit of the MCR has been set. able to finish transmission of the current character.
0 – Not complete. 0 – CTS in false state.
1 – Transmission complete. 1 – CTS is true.
D6 – Transmitter Buffer Register Empty (TBRE). When a D1 – Data Set Ready (DSR). This is a status indicator from
character written to the TBR has been transferred to the the modem to the 82C52 indicating that the modem is ready
Transmitter Register and the TBR is ready for another to provide data to the 82C52.
character, this bit will get set.
0 – DSR in false state.
The user should check the TBRE bit before writing another
character to the Transmitter Buffer Register. This insures 1 – DSR is true.
that the previous character written to the TBR no longer
resides there, but is being shifted out on the SDO pin. 4.0 Transmit/Receive Buffer Registers
0 – Not empty. In addition to the control and status registers, the 82C52 has
1 – Empty. two buffer registers that allow for the actual serial
communications to be performed. These registers are used
D7 – Data Ready (DR). Is set when the Receive Buffer for sending characters out to the SDO pin, and for reading
Register (RBR) has been loaded with a received character data from the SDI pin.
through the SDI pin. The CPU can access this data by
reading the RBR. For example, if the user wishes to see if 4.1 Receiver Buffer Register
there is any data waiting to be read from the Receiver The Receiver Buffer Register (RBR) is a read-only register
Register, this bit can be checked. which contains the character received via the SDI pin. When
0 – No data ready. data is received by the 82C52, it is read serially into the
Receiver Register from the SDI pin, and then transferred to
1 – Data ready in RBR. the RBR for the CPU’s access. This double buffering allows
NOTE: In an interrupt driven system, interrupts caused by the DR for higher transmission rates without loss of data. However,
signal should have a higher priority than those caused by the TBRE should additional characters be received by the 82C52
signal. This will guard the software against Overrun errors. You have before this register is read, then the Receiver Register will
no control over the information being sent to you, but you can control be overwritten with the subsequent characters. This will
how and when you are transmitting data. cause the Overrun Error (OE) flag to be asserted.
3.2 Modem Status Register The RBR is 8-bits long and can accept data lengths of 5 to 8-
The Modem Status Register (MSR), a read-only register, bits. The data will be right justified in the register. When
allows the user to determine the status of the Modem Status selecting data lengths of less than 8-bits, the 82C52 will
pins. The status of these pins is reflected by the correspond- insert zeros (0) into the RBR for the unused (most signifi-
ing bit(s) being set to a one if the state of the pin is in its true cant) bits. For example, if the 82C52 is configured for 6 data
state (low), and by being set to a zero if the pin is in its false bits, and the character 31H is received, the RBR will look as
state (high). This will apply regardless of whether the pin is follows when read:
set up to be active high or active low.

9
 Application Note 108

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
= 31H
0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1

FIGURE 9. RECEIVED DATA FIGURE 11. TRANSMITTED DATA

Bits D7 and D6 are automatically zeroed out by the 82C52. The two most significant bits are zeroed out automatically by
the 82C52.

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

BIT 0 BIT 0

BIT 1 BIT 1
5-BIT 5-BIT
BIT 2 6-BIT BIT 2 6-BIT
WORD WORD
WORD 7-BIT WORD 7-BIT
BIT 3 8-BIT BIT 3 8-BIT
WORD WORD
BIT 4 WORD BIT 4 WORD

BIT 5 BIT 5

BIT 6 BIT 6

BIT 7 BIT 7

NOTE: THE LSB, BIT 0 IS THE FIRST SERIAL DATA BIT RECEIVED NOTE: THE LSB, BIT 0 IS THE FIRST SERIAL DATA BIT TRANSMITTED

FIGURE 10. RBR FORMAT FIGURE 12. TBR FORMAT

4.2 Transmitter Buffer Register 5.0 I/O Addressing Methods

The Transmitter Buffer Register (TBR) is a write only register To utilize the 82C52 in a microprocessor based system, it is
used for sending characters out through the SDO pin. necessary for the system to be designed such that we can
Characters to be transmitted should only be written to this easily access (address) the device. In the following
register when it is empty. This condition can be checked for discussion, we will look at two I/O device addressing
by reading the UART Status Register (USR) TBRE bit, or schemes that can be applied to the 82C52:
waiting for an interrupt to signal this condition.
- I/O Mapped Addressing, and
Like the Receiver circuitry, the Transmitter also uses double
buffering. Here, we are taking advantage of the double - Memory Mapped I/O Addressing
buffering to increase throughput with the 82C52. The user We will look at these two modes as they apply to an
would first write a character to the TBR. From here it is 80C86/80C88-based system.
shifted (in parallel) into a second register known as the
5.1 I/O Mapped Addressing
Transmit Register. After this transfer has been completed,
the TBRE bit is set. In this scheme of I/O addressing, the microprocessor uses
The character shifted into the Transmit Register is then one set of instructions for accessing memory, and a different
shifted serially out onto the SDO pin. Meanwhile, because set for accessing I/O devices. The CPU will generate
the TBR is empty, another character can be written by the different control signals (IO/M) to select either memory or I/O
CPU to the TBR. In effect, the transmitter circuitry is then based upon the type of instruction it is executing. Because of
performing two operations simultaneously. This double this, the system needs two sets of control logic for accessing
buffering technique allows continuous data flow memory and I/O. As we can see in Figure 13, the control
transmission. logic for each is essentially the same.

The Transmit Buffer Register is also 8-bits wide. Because we When addressing I/O, we would use either the IN instruction
can specify data lengths as being from 5 to 8-bits wide, the or the OUT instruction. The port address specified in the
82C52 right justifies the data when it is written to the TBR, instruction is placed on the address bus, and the IO/M signal
and fills the unused bits with zero’s. In other words, unused selects and activates the control logic for I/O. If we used one
(most significant) bits are truncated. For example, if we set of the memory commands (MOV, CMP, TEST, etc.), the IO/M
up the device so that 6 data bits are specified and we write signal would activate the control logic for the system
the character 71H (01110001 b) to the TBR, we will memory.
effectively be transmitting the character:

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

10
 Application Note 108

MEMORY 5.2 Memory Mapped I/O

A0 RD Memory Mapped I/O uses the same control logic for
WR accessing both memory and I/O devices within a system.
This is illustrated in Figure 14. Because we are using one set
A10 of control logic, we reduce the number of devices in the
CS DATA
system, and save board space.
HPL-82C338
80C86 When I/O devices are placed within the Memory Space of a
OR A Y0 OTHER
80C88 ADDRESS B MEMORY system, it is possible to take advantage of the memory
CPU BUS
C instruction set. This would now allow us to utilize the full
IO/M G1 Y7 register set in I/O operations, as opposed to only being able
to use the accumulator (AX/AL) for the I/O instructions. Also,
HPL-82C338 conditional testing can be applied to the I/O devices (i.e.
A Y0 TEST, CMP). When using memory mapped I/O, it should be
B noted that the I/O devices can no longer be accessed
C
through the I/O instructions (IN and OUT). There are
IO/M G1 Y7
disadvantages to using memory mapped I/O as well:
CS RD
- The I/O devices are treated as memory, therefore the
DATA BUS WR
amount of available memory in the system is reduced.
I/O DEVICE
(82C52) - Memory instructions will execute slower than the I/O
FIGURE 13. I/O MAPPED ADDRESSING
commands (IN and OUT). In certain situations (i.e. I/O
polling), this could lead to loss of data during communica-
tions (overrun errors).
5.3 I/O Addressing For The 82C52
MEMORY
The actual addressing of the 82C52 internal registers takes
RD
place through the address pins A0 and A1. These two sig-
WR
CS nals are taken from the address bus. In the following exam-
74XX138 ple(s), address lines AD0 and AD1 from the 80C86/88 drive
A0 and A1, respectively, on the 82C52. Control logic will
80C86 Y0
OR A OTHER decode the remaining address lines from the CPU to gener-
80C88 ADDRESS B MEMORY ate a ‘chip select’ for enabling the 82C52. The control logic
CPU BUS C OTHER I/O consists of a 74XX138 Chip Select Decoder.
DEVICES
Y7 The addresses for the 82C52 set up as described above are
shown in Table 7.
CS RD
TABLE 7. EXAMPLE ADDRESSES
DATA BUS WR
REGISTER ADDRESS REGISTER TYPE
82C52
MEMORY MAP Transmit Buffer Register 10H Write only register
0K
Receiver Buffer Register 10H Read only register
UART Control Register 11H Write only register
UART Status Register 11H Read only register

MEMORY Modem Control Register 12H Write/Read register

Baud Rate Selector Register 13H Write only register
Modem Status Register 13H Read only register

I/O
6.0 Reset Of The 82C52
There are two distinct ways in which the 82C52 can be reset
MEMORY to a known initial state: (1) By applying a reset pulse for at
1024K* least two clock cycles on the RST pin, or (2) through soft-
ware.
* ~ IN 80C86 SYSTEM
A hardware reset is accomplished by forcing the RST pin to
FIGURE 14. MEMORY MAPPED I/O ADDRESSING a high state for a minimum of two clock cycles. This should
be for two cycles of the 82C52’s IX clock input as opposed to

11
 Application Note 108

the system clock. This reset will cause the UART Status Addressing of the internal registers on the 82C52 occurs by
Register (USR) to be set to 60H (TC and TBRE bits will be using the address lines A1 and A0, as well as the WR and
set), and the Modem Control Register(MCR) will be cleared. RD lines. A more complete description of this is shown in
Any lines associated with the bits in the USR and MCR will Table 8.
be cleared or disabled.
82C52 Polling Operation
During the reset of the device, the Baud Rate Select Regis-
When utilizing a polling scheme for communications with the
ter (BRSR) and the UART Control Register (UCR) will not be
82C52, it is important to note that the UART status register
affected. However, if the reset comes due to power on, these
will be cleared of its contents when it is read by the proces-
registers will have an indeterminate value associated with
sor. Therefore, subsequent reads of this register will show
them. After this reset, the 82C52 will remain in an idle state
the contents to be 00H unless the status of the device has
until programmed to its desired configuration.
changed between reads. Because of this, it would be neces-
A second method of resetting the 82C52 is through a soft- sary for a copy of the status to be saved so that the proper
ware reset. This will allow the device to be set to a known status can be seen.
state. The procedure for performing a software reset is out-
Interrupt Driven Operation
lined below:
(1) MCR = 00H. Write a zero to the MCR. This will disable In this example, the 82C59A Interrupt Controller is being
the receiver as well as the modem control lines, and used to handle interrupts generated by the 82C52. The
interrupts. 82C59A then communicates this interrupt information to the
CPU so that it may be properly serviced. An example of how
(2) Read the RBR to clear out any residual data.
the 82C59A and 82C52 are interfaced to the CPU is shown
(3) Read the USR to reset status, thus keeping status lines in Figure 15.
from causing possible interrupts to the CPU.
(4) Reconfigure the device for the desired mode of opera-
tion. AD0 A0 D0 -D7

AD2 A Y6 CS
7.0 Programming The 82C52 IR2
AD3 B Y4
In order to configure the 82C52 for proper operation, three AD4 C 82C59A
separate command words need to be written to the com-
mand (control) registers that were specified earlier. 74XX138 CS
INTR
These registers include (1) the UART Control Register, (2) AD0 A0
the Baud Rate Select Register, and (3) the Modem Control AD1 A0
Register. When programming the device, these registers can
be written to in any order. It is advisable to initialize the D0 -D7
Modem Control Register last because it controls the 82C52
enabling of interrupts, and the receiver circuitry. Once initial-
ized, the 82C52 can be reconfigured at any time by writing
new command word(s) to the control registers. However, the 80C88 80C88
ADDRESS BUS DATA BUS
device should not be actively transmitting or receiving data
when reconfiguring the control registers. FIGURE 15. INTERRUPT DRIVEN SYSTEM

TABLE 8. ADDRESSING THE 82C52

ALE CSO CS1 A1 A0 WR RD OPERATION

1 or 0 1 0 0 1 Data bus TBR

1 or 0 1 0 0 1 RBR Data bus

1 or 0 1 0 1 1 Data bus UCR

1 or 0 1 0 1 1 USR Data bus

1 or 0 1 1 0 1 Data bus MCR

1 or 0 1 1 0 1 MCR Data bus

1 or 0 1 1 1 1 Data bus BRSR

1 or 0 1 1 1 1 MSR Data bus

12