Chapter Seven

Memories: Review

• SRAM:
– value is stored on a pair of inverting gates
– very fast but takes up more space than DRAM (4 to 6 transistors)

• DRAM:
– value is stored as a charge on capacitor (must be refreshed)
– very small but slower than SRAM (factor of 5 to 10)

2
Exploiting Memory Hierarchy

• Users want large and fast memories!

SRAM access times are 2 - 25ns at cost of $100 to $250 per Mbyte.
DRAM access times are 60-120ns at cost of $5 to $10 per Mbyte. 1997
Disk access times are 10 to 20 million ns at cost of $.10 to $.20 per Mbyte.

• Try and give it to them anyway

– build a memory hierarchy CPU

Increasing distance
Level 1
from the CPU in
access time

Levels in the Level 2

memory hierarchy

Level n

Size of the memory at each level

3

Locality

• A principle that makes having a memory hierarchy a good idea

• If an item is referenced,

temporal locality: it will tend to be referenced again soon

spatial locality: nearby items will tend to be referenced soon.

Why does code have locality?

• Our initial focus: two levels (upper, lower)

– block: minimum unit of data
– hit: data requested is in the upper level
– miss: data requested is not in the upper level

4
Cache

• Two issues:
– How do we know if a data item is in the cache?
– If it is, how do we find it?
• Our first example:
– block size is one word of data
– "direct mapped"

For each item of data at the lower level,

there is exactly one location in the cache where it might be.

e.g., lots of items at the lower level share locations in the upper level

Direct Mapped Cache

• Mapping: address is modulo the number of blocks in the cache

C a ch e
000
001
010
011

111
100
101
110

00 00 1 0 01 01 01 00 1 0 11 01 10 00 1 1 01 01 1 1 00 1 11 1 01

M e m ory

6
Direct Mapped Cache

• For MIPS: A d dre ss (sh ow ing b it p os itio ns)

3 1 30 1 3 12 11 2 1 0
By te
o ffse t
20 10
H it D ata
Tag
Ind ex

In de x V alid T ag D a ta
0
1
2

10 21
10 22
10 23
20 32

What kind of locality are we taking advantage of?

7

Direct Mapped Cache

• Taking advantage of spatial locality:

Address (showing bit positions)
31 16 15 4 32 1 0

16 12 2 Byte
Hit Tag Data
offset
Index Block offset
16 bits 128 bits
V Tag Data

4K
entries

16 32 32 32 32

Mux
32

8
Hits vs. Misses

• Read hits
– this is what we want!

• Read misses
– stall the CPU, fetch block from memory, deliver to cache, restart

• Write hits:
– can replace data in cache and memory (write-through)
– write the data only into the cache (write-back the cache later)

• Write misses:
– read the entire block into the cache, then write the word

Hardware Issues

• Make reading multiple words easier by using banks of memory

CPU CPU C PU

M ultiplexor
Cache Cache
Cache

B us Bus Bus

M emory M em ory M emory M em ory

M em ory
bank 0 bank 1 bank 2 bank 3

M emory b. Wide mem ory organization c. Interleaved m emory organization

a. O ne- word -wide

memory organization

• It can get a lot more complicated...

10
Performance

• Increasing the block size tends to decrease miss rate:

40%

35%

30%

25%

Miss rate
20%

15%

10%

5%

0%
4 16 64 256
Block size (bytes) 1 KB
8 KB
16 KB
64 KB
256 KB

• Use split caches because there is more spatial locality in code:

Block size in Instruction Data miss Effective combined

Program words miss rate rate miss rate
gcc 1 6.1% 2.1% 5.4%
4 2.0% 1.7% 1.9%
spice 1 1.2% 1.3% 1.2%
4 0.3% 0.6% 0.4% 11

Performance

• Simplified model:

execution time = (execution cycles + stall cycles) × cycle time

stall cycles = # of instructions × miss ratio × miss penalty

• Two ways of improving performance:

– decreasing the miss ratio
– decreasing the miss penalty

What happens if we increase block size?

12
Set Associative Caches

• Basic Idea: a memory block can be mapped to more than one

location in the cache
• Cache is divided into sets
• Each memory block is mapped to a particular set
• Each set can have more than one block
– Number of blocks in set = associativity of cache
– If a set has only one block, then it is a direct-mapped cache
• I.e. direct mapped caches have a set associativity of 1
• Each memory block can be placed in any of the blocks of the set to
which it maps

13

Direct mapped cache: block N maps to ( N mod num of blocks

in cache)
Set associative cache: block N maps to set (N mod num of sets in
cache)

Example below shows placement of block whose address is 12

Direct mapped Set associative Fully associative
Block # 0 1 2 3 4 5 6 7 Set # 0 1 2 3

Data Data Data

1 1 1
Tag Tag Tag
2 2 2

Search Search Search

14
Decreasing miss ratio with associativity
One-way set associative
(direct mapped)
Block Tag Data
0
Two-way set associative
1
Set Tag Data Tag Data
2
3 0

4 1

5 2

6 3

Four-way set associative

Set Tag Data Tag Data Tag Data Tag Data
0
1

Eight-way set associative (fully associative)

Tag Data Tag Data Tag Data Tag Data Tag Data Tag Data Tag Data Tag Data

Compared to direct mapped, give a series of references that:

– results in a lower miss ratio using a 2-way set associative cache
– results in a higher miss ratio using a 2-way set associative cache
assuming we use the “least recently used” replacement strategy 15

An implementation
A d dress
31 30 12 11 10 9 8 3 2 1 0

22 8

Ind ex V Tag D a ta V Tag D a ta V T ag D a ta V T ag D a ta

0
1
2

253
254
255
22 32

4 - to - 1 m u ltip le x o r

H it D a ta

16
Performance

15%

12%

9%
Miss rate

6%

3%

0%
One-way Two-way Four-way Eight-way
Associativity 1 KB 16 KB
2 KB 32 KB
4 KB 64 KB
8 KB 128 KB

17

Set Associative Caches

• Advantages:
– Miss ratio decreases as associativity increases
• Disadvantages
– Extra memory needed for extra tag bits in cache
– Extra time for associative search

18
Block Replacement Policies

• What block to replace on a cache miss?

– We have multiple candidates (unlike direct mapped
caches)
– Random
– FIFO (First In First Out)
– LRU (Least Recently Used)
• Typically, cpus use Random or Approximate LRU
because easier to implement in hardware

19

Example
Cache size = 4 one word blocks
Replacement Policy = LRU
Sequence of memory references 0,8,0,6,8
Set associativity = 4 (Fully Associative); Number of Sets = 1

Address Hit/Miss Set 0 Set 0 Set 0 Set 0

0 M 0

8 M 0 8

0 H 0 8

6 M 0 8 6

8 H 0 8 6

20
Example cont’d
Cache size = 4 one word blocks
Replacement Policy = LRU
Sequence of memory references 0,8,0,6,8
Set associativity = 2 ; Number of Sets = 2

Address Hit/Miss Set 0 Set 0 Set 1 Set 1

0 M 0

8 M 0 8

0 H 0 8

6 M 0 6

8 M 8 6

21

Example cont’d
Cache size = 4 one word blocks
Replacement Policy = LRU
Sequence of memory references 0,8,0,6,8
Set associativity = 1 (Direct Mapped Cache)

Address Hit/Miss 0 1 2 3

0 M 0

8 M 8

0 M 0

6 M 0 6

8 M 8 6

22
Decreasing miss penalty with multilevel caches

• Add a second level cache:

– often primary cache is on the same chip as the processor
– use SRAMs to add another cache above primary memory (DRAM)
– miss penalty goes down if data is in 2nd level cache

• Example:
– CPI of 1.0 on a 500Mhz machine with a 5% miss rate, 200ns DRAM access
– Adding 2nd level cache with 20ns access time decreases miss rate to 2%

• Using multilevel caches:

– try and optimize the hit time on the 1st level cache
– try and optimize the miss rate on the 2nd level cache

23

100
Im p r o v e m e n t f a c t o r

10

1
0 2
8 8 84 86 8
8
9
0
9
2 94 9
6
19 19 19 19 19 19 19 19 19

Year C P U ( fa s t)

C P U ( s lo w )

DRAM

24
 14%

12%

10%
Miss rate per type

8%

6%

4%

2% Capacity

0%
1 2 4 8 16 32 64 128

Cache size (KB) One-way Four-way

Two-way Eight-way

25

Virtual Memory

• Main memory can act as a cache for the secondary storage (disk)

Virtual addresses Physical addresses

Address translation

Disk addresses

• Advantages:
– illusion of having more physical memory
– program relocation
– protection
26
Recall: Each MIPS program has an address
space of size 232 bytes
$sp 7fff ffff hex Stack

Dynamic data

$gp 1000 8000 Static data

hex

1000 0000 hex

Text
pc 0040 0000 hex
Reserved
0

27

Pages: virtual memory blocks

• Page faults: the data is not in memory, retrieve it from disk

– huge miss penalty, thus pages should be fairly large (e.g., 4KB)
– reducing page faults is important (LRU is worth the price)
– can handle the faults in software instead of hardware
– using write-through is too expensive so we use writeback

Virtual address
31 30 29 28 27 15 14 13 12 11 10 9 8 3210

Virtual page number Page offset

Translation

29 28 27 15 14 13 12 11 10 9 8 3210

Physical page number Page offset

Physical address

28
Page Tables

Virtual page
number
Page table
Physical memory
Physical page or
Valid disk address

1
1
1
1
0
1
1
0
1 Disk storage
1
0
1

29

Page Tables

Page table register

Virtual address

31 30 29 28 27 15 14 13 12 11 10 9 8 3 2 1 0

Virtual page number Page offset

20 12

Valid Physical page number

Page table

18
If 0 then page is not
present in memory

29 28 27 15 14 13 12 11 10 9 8 3 2 1 0

Physical page number Page offset

Physical address

30
Making Address Translation Fast

• A cache for address translations: translation lookaside buffer

TLB
Virtual page Physical page
number Valid Tag address

1
1 Physical memory
1
1
0
1

Page table
Physical page
Valid or disk address

1
1
1 Disk storage
1
0
1
1
0
1
1
0
1

31

TLBs and caches

Virtual addre ss

TLB acce ss

TLB miss No Y es
TLB hit?
exception Ph ysical a ddre ss

No Y es
W rite ?

Try to read da ta
from cache No Write a cc ess Y es
bit on?

Write prote ctio n

ex cep tio n Write data into ca che,
No Y es update the tag , and put
Ca ch e miss stall Cache hit? the data and the addre ss
in to the w rite bu ffer

Deliver da ta
to the C PU

32
Modern Systems
• Very complicated memory systems:
Characteristic Intel Pentium Pro PowerPC 604
Virtual address 32 bits 52 bits
Physical address 32 bits 32 bits
Page size 4 KB, 4 MB 4 KB, selectable, and 256 MB
TLB organization A TLB for instructions and a TLB for data A TLB for instructions and a TLB for data
Both four-way set associative Both two-way set associative
Pseudo-LRU replacement LRU replacement
Instruction TLB: 32 entries Instruction TLB: 128 entries
Data TLB: 64 entries Data TLB: 128 entries
TLB misses handled in hardware TLB misses handled in hardware

Characteristic Intel Pentium Pro PowerPC 604

Cache organization Split instruction and data caches Split intruction and data caches
Cache size 8 KB each for instructions/data 16 KB each for instructions/data
Cache associativity Four-way set associative Four-way set associative
Replacement Approximated LRU replacement LRU replacement
Block size 32 bytes 32 bytes 33
Write policy Write-back Write-back or write-through

Some Issues

• Processor speeds continue to increase very fast

— much faster than either DRAM or disk access times

• Design challenge: dealing with this growing disparity

• Trends:
– synchronous SRAMs (provide a burst of data)
– redesign DRAM chips to provide higher bandwidth or processing
– restructure code to increase locality
– use prefetching (make cache visible to ISA)

34