Field-Effect Transistors

FET

FETs (Field-Effect Transistors) are much like BJTs (Bipolar Junction Transistors).

Similarities:
• Amplifiers
• Switching devices
• Impedance matching circuits

Differences:
• FETs are voltage controlled devices whereas BJTs are current controlled
devices.
• FETs also have a higher input impedance, but BJTs have higher gains.
• FETs are less sensitive to temperature variations and because of their
construction they are more easily integrated on ICs.
• FETs are also generally more static sensitive than BJTs.
 FET Types

•JFET–– Junction Field-Effect Transistor

•MOSFET –– Metal-Oxide Semiconductor Field-Effect Transistor

D-MOSFET –– Depletion MOSFET

E-MOSFET –– Enhancement MOSFET
 JFET Construction
There are two types of JFETs

•n-channel
•p-channel

The n-channel is more widely used.

There are three terminals.

•Drain (D) and source (S) are connected to the n-channel

•Gate (G) is connected to the p-type material
 Basic Operation of a JFET

JFET operation can be compared to a water spigot.

The source of water pressure is the

accumulation of electrons at the
negative pole of the drain-source
voltage.

The drain of water is the electron

deficiency (or holes) at the positive
pole of the applied voltage.

The control of flow of water is the

gate voltage that controls the width
of the n-channel and, therefore, the
flow of charges from source to
drain.
 JFET Operating Characteristics

There are three basic operating conditions for a JFET:

• VGS = 0, VDS increasing to some positive value

• VGS < 0, VDS at some positive value
• Voltage-controlled resistor
 JFET Operating Characteristics
VGS = 0, VDS increasing to some positive value
Three things happen when VGS = 0 and VDS is increased from 0 to a more positive
voltage
• The depletion region between p-gate
and n-channel increases as electrons
from n-channel combine with holes
from p-gate.

• Increasing the depletion region,

decreases the size of the n-channel
which increases the resistance of the
n-channel.

• Even though the n-channel resistance

is increasing, the current (ID) from
source to drain through the n-
channel is increasing. This is because
VDS is increasing.
 JFET Operating Characteristics
VGS = 0, VDS increasing to some positive value: Pinch Off

If VGS = 0 and VDS is further increased to

a more positive voltage, then the
depletion zone gets so large that it
pinches off the n-channel.

This suggests that the current in the n-

channel (ID) would drop to 0A, but it does
just the opposite–as VDS increases, so does
ID.
 JFET Operating Characteristics
VGS = 0, VDS increasing to some positive value: Saturation

At the pinch-off point:

• Any further increase in VGS does not

produce any increase in ID. VGS at
pinch-off is denoted as Vp.

• ID is at saturation or maximum. It is
referred to as IDSS.

• The ohmic value of the channel is

maximum.
 JFET Operating Characteristics
VGS < 0, VDS at some positive value

As VGS becomes more negative, the

depletion region increases.
 JFET Operating Characteristics
VGS < 0, VDS at some positive value: ID < IDSS

As VGS becomes more negative:

• The JFET experiences

pinch-off at a lower voltage
(Vp).

• ID decreases (ID < IDSS) even

though VDS is increased.

• Eventually ID reaches 0A.

VGS at this point is called Vp
or VGS(off)..

Also note that at high levels of VDS the JFET reaches a breakdown situation. ID
increases uncontrollably if VDS > VDSmax.
 JFET Operating Characteristics
Voltage-Controlled Resistor

The region to the left of the

pinch-off point is called the
ohmic region.

The JFET can be used as a

variable resistor, where VGS
controls the drain-source
resistance (rd). As VGS becomes
more negative, the resistance
(rd) increases.
ro
rd 
2
 V 
 1  GS 
 VP 
 p-Channel JFETS

The p-channel JFET behaves the

same as the n-channel JFET,
except the polarities and currents
are reversed.
 p-Channel JFET Characteristics

As VGS increases more positively

• The depletion zone

increases
• ID decreases (ID < IDSS)
• Eventually ID = 0A

Also note that at high levels of VDS the JFET reaches a breakdown situation—ID
increases uncontrollably if VDS > VDSmax.
JFET Symbol
 JFET Transfer Characteristics

The transfer characteristic of input-to-output is not as straightforward in

a JFET as it is in a BJT.

In a BJT,  indicates the relationship between IB (input) and IC (output).

In a JFET, the relationship of VGS (input) and ID (output) is a little more

complicated:

2
 V 
I D  I DSS  1  GS 

 VP
 
 JFET Transfer Curve

This graph shows the

value of ID for a
given value of VGS.
 Plotting the JFET Transfer Curve

Using IDSS and Vp (VGS(off)) values found in a specification sheet, the transfer
curve can be plotted according to these three steps:

Step 1
2
 V 
I D  I DSS  1  GS 
 VP 
Solving for VGS = 0V ID = IDSS

Step 2
2
 V 
I D  I DSS  1  GS 
 VP 
Solving for VGS = Vp (VGS(off)) ID = 0A

Step 3
2
 V 
Solving for VGS = 0V to Vp I D  I DSS  1  GS 
 VP 
JFET Specifications Sheet

Electrical Characteristics
Maximum Ratings

more…
JFET Case Construction and Terminal Identification
 Testing JFETs

• Curve Tracer
A curve tracer displays the ID versus VDS graph for various
levels of VGS.

• Specialized FET Testers

These testers show IDSS for the JFET under test.
 MOSFETs

MOSFETs have characteristics similar to JFETs and additional

characteristics that make then very useful.

There are two types of MOSFETs:

• Depletion-Type
• Enhancement-Type
 Depletion-Type MOSFET Construction

The drain (D) and source (S) connect to

the to n-doped regions. These n-doped
regions are connected via an n-channel.
This n-channel is connected to the gate
(G) via a thin insulating layer of SiO2.

The n-doped material lies on a p-doped

substrate that may have an additional
terminal connection called substrate
(SS).
 Basic MOSFET Operation

A depletion-type MOSFET can operate in two modes:

• Depletion mode
• Enhancement mode
 Depletion-Type MOSFET in Depletion Mode

Depletion Mode

The characteristics are similar

to a JFET.

• When VGS = 0V, ID = IDSS

• When VGS < 0V, ID < IDSS
• The formula used to plot the transfer
curve still applies:
2
 V 
I D  I DSS  1  GS 
 VP 
 Depletion-Type MOSFET in Enhancement Mode

Enhancement Mode

• VGS > 0V
• ID increases above IDSS
• The formula used to plot
the transfer curve still
applies: 2
 V 
I D  I DSS  1  GS 
 VP 

Note that VGS is now a positive polarity

p-Channel Depletion-Type MOSFET
Specification Sheet

Electrical Characteristics

Maximum Ratings

more…
 Enhancement-Type MOSFET Construction

• The drain (D) and source (S) connect

to the to n-doped regions. These n-
doped regions are connected via an n-
channel

• The gate (G) connects to the p-doped

substrate via a thin insulating layer of
SiO2

• There is no channel

• The n-doped material lies on a p-doped

substrate that may have an additional
terminal connection called the
substrate (SS)
 Basic Operation of the Enhancement-Type MOSFET

The enhancement-type MOSFET only operates in the enhancement mode.

• VGS is always positive

• As VGS increases, ID
increases

• As VGS is kept constant

and VDS is increased,
then ID saturates (IDSS)
and the saturation level,
VDSsat is reached
 Enhancement-Type MOSFET Transfer Curve

To determine ID given VGS:

I D  k ( VGS  VT ) 2

Where:
VT = threshold voltage
or voltage at which the
MOSFET turns on

k = constant found in
the specification sheet

k can also be determined by using values at a VDSsat can be calculated by:

specific point and the formula:
VDsat  VGS  VT
I D(ON)
k
(VGS(ON)  VT) 2
 p-Channel Enhancement-Type MOSFETs

The p-channel enhancement-type MOSFET is similar to the n-channel,

except that the voltage polarities and current directions are reversed.
MOSFET Symbols
Specification Sheet

Electrical Characteristics
Maximum Ratings

more…
 Handling MOSFETs

MOSFETs are very static sensitive. Because of the very thin SiO2 layer
between the external terminals and the layers of the device, any small
electrical discharge can create an unwanted conduction.

Protection

• Always transport in a static sensitive bag

• Always wear a static strap when handling MOSFETS

•
• Apply voltage limiting devices between the gate and source, such as
back-to-back Zeners to limit any transient voltage.
 VMOS Devices

VMOS (vertical MOSFET)

increases the surface area of
the device.

Advantages

• VMOS devices handle

higher currents by
providing more surface
area to dissipate the heat.

• VMOS devices also have

faster switching times.
 CMOS Devices

CMOS (complementary
MOSFET) uses a p-channel
and n-channel MOSFET on
the same substrate.

Advantages

• Useful in logic circuit designs

• Higher input impedance
• Faster switching speeds
• Lower operating power levels
Summary Table
FET Biasing
Common FET Biasing Circuits

JFET
• Fixed – Bias
• Self-Bias
• Voltage-Divider Bias

Depletion-Type MOSFET
•Self-Bias
•Voltage-Divider Bias

Enhancement-Type MOSFET
•Feedback Configuration
•Voltage-Divider Bias
 General Relationships

For all FETs:

I G  0A
ID  IS

For JFETS and depletion-type MOSFETs:

2
 V 
I D  I DSS  1  GS 
 VP 

For enhancement-type MOSFETs:

I D  k ( VGS  VT ) 2
 JFETs

JFETs differ from BJTs

• Nonlinear relationship between input (VGS) and output (ID)

• JFETs are voltage controlled devices, whereas BJTs are current

controlled
 Fixed-Bias Configuration

VDS  VDD  I D RD
VS  0V
VD  VDS
VG  VGS
VGS  VGG
Self-Bias Configuration
 Self-Bias Calculations
For the indicated loop, VGS  I D R S
To solve this equation:
• Select an ID < IDSS and use the component value
for RS

• Plot this point: ID and VGS and draw a line from

the origin of the axis to this point

• Plot the transfer curve using IDSS and

VP (VP = VGSoff in specification sheets) and a few
points such as ID = IDSS / 4 and ID = IDSS / 2 etc.

The Q-point is located where the first line

intersects the transfer curve. Use the value
of ID at the Q-point (IDQ) to solve for the
other voltages:
VDS  VDD  I D ( R S  R D )
VS  I D R S
VD  VDS  VS  VDD  VRD
 Voltage-Divider Bias

IG = 0A

Unlike BJTs—where IB
affected IC—in FETs it is
VGS that controls ID.
 Voltage-Divider Bias Calculations

VG is equal to the voltage across

divider resistor R2:
R 2 VDD
VG 
R1  R 2

Using Kirchhoff’s Law:

VGS  VG  I D R S

The Q point is established by plotting

a line that intersects the transfer
curve.
 Voltage-Divider Q-point

Step 1
Plot the line by plotting two points:
•VGS = VG, ID =0
•VGS = 0, ID = VG / RS

Step 2
Plot the transfer curve by plotting
IDSS, VP and the calculated values
of ID
Step 3
The Q-point is located where the
line intersects the transfer curve
 Voltage-Divider Bias Calculations

Using the value of ID at the Q-point, solve for the other variables in the voltage-
divider bias circuit:

VDS  VDD  I D ( R D  R S )
VD  VDD  I D R D
VS  I D R S

VDD
I R1  I R2 
R1  R 2
 Depletion-Type MOSFETs

Depletion-type MOSFET bias

circuits are similar to JFETs.
The only difference is that
depletion-type MOSFETs can
operate with positive values of
VGS and with ID values that
exceed IDSS.
 Self-Bias

Step 1
Plot line for
•VGS = VG, ID = 0
•ID = VG/RS, VGS = 0

Step 2
Plot the transfer curve by plotting IDSS, VP
and calculated values of ID

Step 3
The Q-point is located where the line
intersects the transfer curve. Use the ID at
the Q-point to solve for the other variables
in the voltage-divider bias circuit.

These are the same calculations used for JFET circuits.

 Voltage-Divider Bias

Step 1
Plot the line for
•VGS = VG, ID = 0
•ID = VG/RS, VGS = 0

Step 2
Plot the transfer curve by plotting IDSS, VP and
calculated values of ID.

Step 3
The Q-point is located where the line
intersects the transfer curve is. Use the ID at
the Q-point to solve for the other variables in
the voltage-divider bias circuit.

These are the same calculations as used for

JFET circuits.
 Enhancement-Type MOSFET

The transfer characteristic for

the enhancement-type
MOSFET is very different from
that of a simple JFET or the
depletion-type MOSFET.
 Feedback Biasing Arrangement

IG = 0A, VRG = 0V

So VDS = VGS

And VGS = VDD – IDRD

 Feedback Bias Q-Point
Step 1
Plot the line using
•VGS = VDD, ID = 0
•ID = VDD / RD , VGS = 0

Step 2
Using values from the specification
sheet, plot the transfer curve with
•VGSTh , ID = 0
•VGS(on), ID(on)

Step 3
The Q-point is located where the line
and the transfer curve intersect

Step 4
Using the value of ID at the Q-point,
solve for the other variables in the
bias circuit
 Voltage-Divider Biasing

Plot the line and the transfer curve to find the

Q-point. Use these equations:

R 2 VDD
VG 
R1  R 2
VGS  VG  I D R S
VDS  VDD  I D ( R S  R D )
 Voltage-Divider Q-Point

Step 1
Plot the line using
•VGS = VG = (R2VDD) / (R1 + R2), ID = 0
•ID = VG/RS , VGS = 0

Step 2
Using values from the specification sheet, plot the transfer curve
with
•VGSTh, ID = 0
•VGS(on) , ID(on)

Step 3
Where the line and the transfer curve intersect is the Q-point.

Step 4
Using the value of ID at the Q-point, solve for the other variables in
the bias circuit.
 p-Channel FETs

For p-channel FETs the same calculations and graphs are used, except that
the voltage polarities and current directions are the opposite. The graphs will
be mirrors of the n-channel graphs.
 Practical Applications

• Voltage-controlled resistor
• JFET voltmeter
• Timer network
• Fiber optic circuitry
• MOSFET relay driver