8.5 Chip Level and System Level Test £& 8.5.1 Boundary Scan Check * Boundary scan check is a test technique which uses scan methodology involving shift registers. The shift register control monitors signal at each input and output pins that are connected in serial fashion to form a chain of data register called Boundary Scan Registers. * Printed circuit boards are becoming more dense and complex with use of Surface Mount Devices (SMD). Hence most test system does not guarantee good fault coverage. Boundary scan check technique involves scan path and self tests which resolves above problems. 8.5.1.1 Merits of Boundary Scan Check Boundary scan check has following advantages over other testing methods. ° 1. Increased fault coverage in system.yisi Design 8-13 CMOS Testi ing 2, The boundary scan check is much m i bs wee aon mete EY ls ten De ae re time efficient. ie. time required is 3, The process of boundary scan check is very simple 4, In built scan path and self test makes it more accurate and efficient. 85.1.2 Boundary Scan Standards + Several standards are specified for boundary scan check testing. Their prime objective is to ensure testing and development less costly and efficient. Some boundary scan standards are mentioned - 1, Joint Test Action Group [JTAG 1988] 2. Element Test and Maintenance [ETM VHSIC] 3. VHSIC Test and Maintenance [TM] Bus Standard. 4. Testability Bus Standard [IEEE 1989] / [IEEE 1149.1] 8.5.2 Boundary Scan Test Methodology « The boundary scan shift register prevents output from rippling as data is shifted through the shift register during scan operation. Input Boundary scan register [Boundary [scan register internal I circuitry Boundary Boundary scan register scan register V. Tristate pin Scan out Boundary scan register Output [Boundary |scan register Bidirectional pin Fig. 8.5.1 Boundary scan test methodology i i in 6 The test set is’scanned into Boundary Scan Registers (BSR) by using 2 ae port with test stimuli input: The response of the circuit is captured? by BSRs in series and scanned out through scan out port. |mh CMOS Testing 8- chain around the border of the visi Design interconnected to form a eg . It indicates All the Bais Me a as single path as shown in Fig. 8.5.2. It in the circuit so as architecture of IEEE 1149 boundary scan. vo Pads, Boundary scan cells, Serial data Serial data output input Boundary scan path, Fig. 8.5.2 Boundary scan architecture ‘The boundary scan path is having serial input output cells/pads and has appropriate clock pads. The cells or pads are provided for - a) Interconnections between chips. b) Internal self test. Various tests that carried out by the architecture IEEE 1149 are - a) Sampling and setting chip input/outputs. b) Connectivity test between components. ©) Distribution and collection of self test and built-in test results. 8.5.3 JTAG ¢ JTAG is IEEE 1149.1 standard for boundary. scan. JTAG is meant for verifying whether ‘the circuit has been mounted on circuit board. correctly. JTAG standard specifies method to test device functionality and interconnections through Test Access Port (TAP) and boundary scan. * JIAG has the capability to transform any’ multi i any’ multipl i ircuit board problem into a well structured prablemn Peet ee JTAG method i i i pate is employed for testing and quality assurance and also for ‘AG i . us ee bee a mode called Built-In-Self-Test (BIST). BIST mode is used t device ia Benet of vectors that need to be clocked through the scan path. A ‘ levi i: mode generates pseudo random test-vectors as stimuli compares internal outputs against expected results and indicates success or failures. « Use of JTAG to test internal outputs failures.Ee . . =a ysl pesigt 8-415 CMOS Testing . Use of JTAG to test internal circuitry is shown in Fig. 8.5.3. Test data in Test data out (To!) (TD0) Fig. 8.5.3 JTAG for testing internal circuitry 853.1 JTAG for External Testing + JTAG used for external testing of connections to other JTAG devices is shown in Fig. 85.4. [System “STAG control logic Tor JTAG-4 STAG -2 Fig. 8.5.4 JTAG for external testing of connections + Test Data Input (TDI) is applied to first JTAG. The test data output of first JTAG is connected to next JTAG TDI. 8.5.3.2 JTAG Architecture © JTAG architecture consists of following blocks. 1, Boundary Scan Register (BSR) 2. ID code register 3. User definable register 4, Instruction register 5. Test Access Port (TAP) Controller 6. Instruction decoder.CMOS Testin, 8-16 a VLSI Design ‘ cties g General JTAG architecture is shown in PE TDO Tol (Test data out) (Test data in) « 1 1 Se TMs IMS >| controller Fig. 8.5.5 JTAG architecture The instruction register is serially loaded-with the instruction. The operations to be performed are selected by these instructions. User defined data registers are set of shift registers. The stimuli needed for an operation are loaded serially into data registers. The results are shifted out after executing the operation. * Test Access Port (TAP) is a. general purpose port which provides access to control logic for operation of JTAG. These inputs are - TCK, TMS, TRST. + TAP controller is a finite state machine that responds to the control sequences through TAP, It generates control signals required for correcting operation. TCK — Test Clock Input TMS ~> Test Mode Select Input TDI > Test Data Input TDO — Test Data Output TRST ~ Test Reset Input, Instruction decoder 8.5.4 TAP Controller : ial eal 5 2 gynehonous finite state machine. It responds to changes it ie. TCK, TMS and TRST ; e sequence of operation of JTAG. 0 TAP and accordingly controls th, 8.5.5 Built-In-Self-Test (BIST) ¢ With the increasing complexity of VLSI. systems, test Seneration an application becomes an expensive and may not be an effective testing, Further the high speeds at which newer VLSI systems are designed to operate may not be possible to be simulated and this may create problems. These aspects can be well handled by incorporating BIST which is mainly focused at reducing - a. The volume of test data. b. Costs involved in test pattern generation. c. Test time. * All above points can be covered by integrating an automatic test system into the design of chip which is possible by different techniques. These test include 1. Linear Feedback Shift Register (LFSR) 2. Buif-In Logic Block Observer (BILBO) 3. Signature analysis.7 8-19 CMOS Testing wel Design 958! Advantages of BIST 4, Low cost. 2. High quality testing. 3, Faster fault detection. 4, Ease of diagnostics. 5. Reduced maintenance and repair costs. 6, Better fault coverage. 7. Capability to perform test outside the electrical testing envirenment. 85.5.2 Disadvantages of BIST 1. Additional silicon area and fabrication Processing requirements, 2. Reduced access time, 3. Additional hardware requirements, 4. On chip testing hardware itself can fail,