Memories - Materials, Devices, Circuits and Systems 5 (2023) 100062

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Memories - Materials, Devices, Circuits and Systems

journal homepage: www.elsevier.com/locate/memori

Special issue on in-memory computing: Circuits, system, architecture and verification

Kamalika Datta, Rolf Drechsler
Institute of Computer Science, University of Bremen/DFKI, Germany

1. Introduction hardware-software codesign, testing and verification. We provide a

comprehensive overview of this field with tutorials covering the broad
We have been witnessing a rapid paradigm shift in the way com- aspects of IMC for smart edge applications. Many vital areas ranging
puting is performed over the last few years. The Von Neumann model from neural networks, implementation of RISC-V architectures and se-
of computation gets restricted by the processor-memory speed gap, curity issues have been covered in this issue. A total of ten papers have
where both instructions and data are stored in memory. In spite of
been included that cover both digital and analog aspects of IMC. These
technological advances and developments in architecture, the speed
include works on computing for smart edge applications, performing
gap continues to increase. This is more pronounced in data intensive
in-memory Fast Fourier Transform and also exploiting attacks on
emerging applications like deep learning, big data analysis, neuromor-
ReRAM based neural networks. A brief summary of the papers is
phic computing, etc., where large volumes of data need to be processed.
In-Memory Computing (IMC) is a concept where the memory cells, in provided below.
addition to being used for data storage, can directly carry out logic 1. Tutorial on memristor-based computing for smart edge ap-
operations without the need to communicate with a central processor. plications – Anteneh Gebregiorgis, Abhairaj Singh, Amirreza Youse-
Among the various alternatives that have been explored, memristors
fzadeh, Dirk Wouters, Rajendra Bishnoi, Francky Catthoor, Said
or Resistive Random-Access Memories (ReRAM) have been found to be a
Hamdioui
suitable candidate for IMC [1,2].
This is a tutorial paper that discusses different aspects of
The Memristor is a two-terminal device whose resistance changes in
response to the voltage applied across its terminals, and this change is memristor-based Computation-In-Memory (CIM) architectures, in-
non-volatile in nature. It can be fabricated in a compact fashion using cluding classification, working principle, CIM potentials and CIM
a crossbar structure, and used as non-volatile resistive memory. The design flow. Some of the research challenges and future research
crossbar cells can store logic values in terms of resistances as well as directions in CIM are also discussed.
can perform logic operations directly in the crossbar [3,4]. Further, 2. Will computing in memory become a new dawn of associa-
several logic design styles have been proposed [4–6] for performing tive processors? – Leonid Yavits
logic operations on the crossbars. Also, various mapping techniques This paper discusses the design of associative processor archi-
exist using these logic design styles, where arbitrary Boolean func- tectures, where memory cells are used for data storage as well
tions are mapped to the crossbars and evaluated by applying suitable as processing. It is shown that associative processors can outper-
voltages to the rows and the columns in sequence [7–13]. Another form state-of-the-art computing platforms by up to almost two
important area where such crossbar has shown great potential is in
orders of magnitude in a variety of data-intensive workloads.
neuromorphic computing [14–18]. Due to the inherent analog na-
3. FourierPIM: High-throughput in-memory Fast Fourier Trans-
ture of the memristor devices, the crossbar is very well suited for
form and polynomial multiplication – Orian Leitersdorf, Yahav
performing vector matrix multiplication. Another important but less
Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky
explored area is the formal verification of programs generated for
execution on the crossbar. Some recent works have demonstrated how This paper presents a method to accelerate the FFT algorithm
to verify majority-based in-memory programs using formal verification using digital Processing-in-Memory (PIM) architectures that shift
techniques [19,20]; however, verification of other logic design styles computation into the memory by exploiting devices capable
remains unexplored. of both storage and logic operations. Two algorithms for FFT
The aim of this special issue is to address the various technolog- and polynomial multiplication are presented, with time com-
ical challenges of IMC, in particular those based on memristors or plexities of O(log(n)). Significant improvements in throughput
ReRAM, and to cover the aspects of device modeling and charac- and energy consumption over state-of-the-art GPUs have been
terization, design of circuits, systems, and architectural frameworks, demonstrated.

E-mail addresses: [email protected] (K. Datta), [email protected] (R. Drechsler).

https://doi.org/10.1016/j.memori.2023.100062

2773-0646/© 2023 Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
K. Datta and R. Drechsler Memories - Materials, Devices, Circuits and Systems 5 (2023) 100062

4. Design of a nonvolatile-register-embedded RISC-V CPU with 10. Exploiting device-level non-idealities for adversarial attacks
software controlled data retention and hardware accelera- on ReRAM-based neural networks – Tyler McLemore, Robert
tion functions – Masanori Natsui, Keisuke Sakamoto, Takahiro Sunbury, Seth Brodzik, Zachary Cronin, Elias Timmons, Dwaipayan
Hanyu Chakraborty
This paper describes the design of a nonvolatile CPU based on
In this paper, a framework to generate adversarial images in the
the open- source RISC-V architecture. The processor uses non-
hyper-volume between the two decision boundaries has been proposed,
volatile registers using Magnetic Tunnel Junction (MTJ) devices,
thereby leveraging non-ideal device behavior for performance detri-
as well as custom instructions specific to the control of these reg-
ment. The authors employ state-of-the-art tools in explainable artificial
isters, and also an accelerator module embedded into the CPU.
intelligence to characterize the adversarial image samples, and derive a
Power savings of about 57% over conventional architectures has
new metric to quantify susceptibility to adversarial attacks at the pixel
been demonstrated.
and device levels.
5. A subranging nonuniform sampling memristive neural
network-based analog-to-digital converter – Hao You, Amirali
2. Conclusion
Amirsoleimani, Jianxiong Xu, Mostafa Rahimi Azghadi, Roman
Genov
Memristors and resistive-memory technologies have changed the
The design of a 4-bit sub-ranging Non-Uniform Sampling (NUS)
way we look at computing. This is evident from the enormous amount
memristive neural network-based Analog-to-Digital Converter
of research that we have witnessed over last one and a half decade.
(ADC) is presented in this paper, with improved performance in
Having said this we are still way behind the issue of actually exploiting
speed, power, and area. The proposed design preserves the Ar-
this technology and applying the same in various areas. Efforts from
tificial Neural Network (ANN) calibration and utilizes a trainable
academia and industry are of paramount importance to bridge this gap.
memristor weight to be adjustable for the device mismatch in the
This special issue is a step forward in identifying the challenges in this
circuit to increase the accuracy. Area and power consumption
domain and discussing some of the possible solutions. While covering
are reduced through circuit sharing between different modules
the broad area of IMC using memristors or ReRAM devices, this issue
in the design.
includes tutorials as well as new ideas. A total of ten papers cover both
6. Efficient grouping approach for fault tolerant weight map-
digital and analog aspects of IMC.
ping in memristive crossbar array – Dev Narayan Yadav,
Phrangboklang Lyngton Thangkhiew, Sandip Chakraborty, Indranil
Declaration of competing interest
Sengupta
This paper discusses a mapping method to tolerate the effect
The authors declare that they have no known competing finan-
of defective memristors in a crossbar used for neuromorphic
cial interests or personal relationships that could have appeared to
applications. In order to reduce the impact of faulty memristors,
influence the work reported in this paper.
the mapping is done in a way that allows network weights to
compensate for the faulty memristors. Further, this work priori-
Acknowledgments
tizes the different faults based on their frequency of occurrence.
The mapping efficiency is found to increase significantly with
reduced power, area and latency overheads. We sincerely thank all the reviewers for helping us in reviewing
the papers in time. We also thank all the staff members of MEMORIES
7. An efficient read approach for memristive crossbar array
journal for their effortless support. Last but not the least we thank the
– Pravanjan Samanta, Dev Narayan Yadav, Partha Pratim Das,
Editor-in-Chief for his help and support throughout the entire process.
Indranil Sengupta
This work was supported by the German Research Foundation
Read operations in a memristive crossbar is a major concern as
(DFG) within the Project PLiM (DR 287/35-1, DR 287/35-2 and SH
they can lead to errors in the presence of sneak paths. This paper
1917/1-2).
presents a new approach for reading the cell values in a crossbar,
which is capable of avoiding erroneous read operations caused
by sneak-paths. It also supports parallel operations whereby References
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