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ACA Assignment

The document discusses several topics related to computer architecture: 1. Cache coherence and snoopy bus protocols which ensure consistency between caches and main memory through bus monitoring and updating or invalidating cache copies. 2. Arithmetic pipelining which applies instruction pipelining techniques to speed up repeated arithmetic operations on vectors and arrays through dedicated floating-point pipelines. 3. The "hot spot problem" which refers to contention for shared memory locations in parallel programs. 4. Vector processors which contain specialized instructions to perform operations on entire vectors or arrays of data in parallel through long pipelines and interleaved memory to reduce latency and branches.

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39 views

ACA Assignment

The document discusses several topics related to computer architecture: 1. Cache coherence and snoopy bus protocols which ensure consistency between caches and main memory through bus monitoring and updating or invalidating cache copies. 2. Arithmetic pipelining which applies instruction pipelining techniques to speed up repeated arithmetic operations on vectors and arrays through dedicated floating-point pipelines. 3. The "hot spot problem" which refers to contention for shared memory locations in parallel programs. 4. Vector processors which contain specialized instructions to perform operations on entire vectors or arrays of data in parallel through long pipelines and interleaved memory to reduce latency and branches.

Uploaded by

Typengineer Pacific
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as DOCX, PDF, TXT or read online on Scribd
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ACA ASSIGNMENT

Name: Prashant Kumar CLASS: CS 8 (X) Roll: 708 A2305208262 ACA Assignment for marks of VIVA

1.) What is cache coherence? Explain snoopy bus protocols?

In computing, cache coherence (also cache coherency) refers to the consistency of data stored in local caches of a shared resource. When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system. Referring to the "Multiple Caches of Shared Resource" figure, if the top client has a copy of a memory block from a previous read and the bottom client changes that memory block, the top client could be left with an invalid cache of memory without any notification of the change. Cache coherence is intended to manage such conflicts and maintain consistency between cache and memory.

Snoopy bus protocol: Cache consistency by bus watching mechanism Each cache watches bus for write operations Write through: forward write immediately to memory o Write-invalidate: cache copies are invalidated. o Write-update: cache copies are updated. o Disadvantage: high bus traffic. Copy back: write modified cache line only back if o Line needs to be replaced, or o Another processor reads data.

2.) Explain about arithmetic pipeline in detail. The pipeline structures used for instruction pipelining may be applied in some cases to other processing tasks. If pipelining is to be useful, however, we must be faced with the need to perform a long sequence of essentially similar tasks. Large numerical applications often make use of repeated arithmetic operations for processing the elements of vectors and arrays. Architectures specialized for applications if this type often provide pipelines to speed processing of floating-point arithmetic sequences. This type of pipelining is called arithmetic pipelining.

3.) What is hot spot problem?

4.) What are vector processors? A vector processor, or array processor, is a central processing unit (CPU) that implements an instruction set containing instructions that operate on one-dimensional arrays of data called vectors. Although Intel processors and their clones were designed initially as scalar, new models contain an increasing number of specialized vector instructions such as those supplied by the Advanced Vector Extensions set. Properties: Each result independent of previous result => long pipeline, compiler ensures no dependencies => high clock rate Vector instructions access memory with known pattern => highly interleaved memory => amortize memory latency of over 64 elements => no (data) caches required! (Do use instruction cache) Reduces branches and branch problems in pipelines Single vector instruction implies lots of work ( loop) => fewer instruction fetches

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