Introduction to Verilog HDL

Presented By
Anjaly Joseph T
(JRF)
What is Verilog?
● Verilog is a hardware description language.

● Used to design and model digital circuits.

● Developed in 1984.

● Verilog is used not only for design, but also for simulation and testing

● You can build testbenches to verify correctness before implementation

Structure of a verilog module
● A module is a block of verilog code that implements a certain functionality.
● Eg:
module module_name
(
input a,
output b);
// internal logic
Endmodule

● Concurrency is the core feature of Verilog, enabling parallel execution that software languages like C or
Python cannot natively achieve
 Valid Module Name Rules
• Must begin with a letter (A–Z or a–z)

• Can contain letters, digits, and underscores (_)

• Cannot contain spaces or special characters (like @, #, %)

• Should not be a Verilog reserved keyword (like module, input, always, etc.)

• Should be meaningful to describe the function (e.g., and_gate,

counter_4bit)
• Verilog modules use ports to communicate with the outside world —

similar to input/output pins on a chip.

Port Type Keyword Description

Input input Data flows into the module

Output output Data flows out of the module

Inout inout Bidirectional data (e.g., buses)

Values in Verilog

Values Definitions

0 Logical zero, False

1 Logical one, True

x Unknown value

z High impedance state

“assign” STATEMENT

• Used for continuous assignment

• LHS must be net

• RHS can be reg/net

• Typically used in combinational circuits

7
Numbers
● Binary : b or B
● Octal : o or O
● Decimal : d or D
● Hexadecimal : h or H
● Syntax : <size>’<base><number>.
● Example : 4’b0001, 4’d12
Data Types in Verilog
A storage format having a specific range or type is called data type. They can
be divided into two groups.

1. Nets
2. Registers / Variables
Common Net Types

Net Type Description Example

wire Standard net type wire a;

tri Tri-state net tri bus;

Wired AND connection

wand wand x;
(multi-driver)

wor Wired OR connection wor y;

supply0, supply1 Constant logic 0 or 1 supply0 gnd;

Nets
● Nets are used to connect between hardware entities like logic gates and
hence do not store any value of its own.
● Wire : most commonly used net data type.
Example : wire a,b,c;
wire [5:0] a;
● The default value of wire is z.
Variable Type Description Example
Holds value in
reg reg clk;
procedural blocks
integer 32-bit signed variable integer i;
64-bit floating-point
real real vout;
number
64-bit for simulation
time time delay;
time
Reg
● Reg is a variable which retains value till updated.

● The default value of reg is x.

● Used in sequntial circuits to store the value

● Example : reg y;
Vectors

● The nets or registers can be declared as vectors to represent multiple bit

widths.
● If bit width is not specified, it is a scalar.
● wire [5:0] a;
● reg [5:0] a;
 Inbuilt gate primitives

● In Verilog, you can instantiate inbuilt (primitive) logic gates directly without needing to define them
yourself.
● These gates are part of Verilog’s built-in library of gate-level primitives and are commonly used for
structural modeling
● Available Gate primitives are
1. and
2. or
3. not
4. nand
5. nor
6. xor
7. xnor
8. buf
Verilog Operators
1. Arithmetic Operators
2. Logical Operators
3. Equality Operators
4. Relational Operators
5. Bitwise Operators
6. Conditional Operators
7. Shift Operators
8. Reduction Operators
9. Concatenation Operators
10. Replication Operators
Arithmetic Operators
Operators Number of operands Description

+ 2 addition

- 2 subtraction

* 2 multiplication

/ 2 division

** 2 Raised to the power

% 2 Modulus provides remainder of division of 2 numbers

module adder (
input [7:0] a,
input [7:0] b,
output [7:0] sum
);

assign sum = a + b;
endmodule
 Logical Operators
• Operates on entire value
• Result is 1 bit value
• Commonly used in if , case, always etc

Operators Number of operand Description

! 1 Logical negation

&& 2 Logical and

|| 2 Logical or
Eg:-

if ((a > 0) && (a<3)) begin

count<=count+1’b1;
else
Count<=0;
end
Bitwise Operators

Operators Number of operands Description

& 2 Bitwise and

| 2 Bitwise or

~ 1 Bitwise not

^ 2 Bitwise xor

^~ or ~^ 2 Bitwise xnor

• Operates on a bit by bit

• Result is a vector
Example
module example(
input reg [3:0] a ,
Input
input reg [3:0] b , A=1100
output [3:0] and_result, or_result, B=1010
xor_result Output
);
and_result = 4'b1000 (8)
assign and_result = a & b; // bitwise and or_result = 4'b1110 (14)
xor_result = 4'b0110 (6)
assign or_result = a | b; // bitwise or
assign xor_result = a ^ b; // bitwise xor
endmodule
Equality Operators
Operators Number of operands Description

== 2 Equality

!= 2 Inequality

=== 2 Case equality

!== 2 Case inequality

● The equality and inequality operator compares two operands bit by bit and
results to 1 or 0 if true or false respectively. They will return value as ‘x’ if either
operand has x or z bits.
Relational Operators
Operators Number of operands Description

> 2 Greater than

>= 2 Greater than or equal to

< 2 Less than

<= 2 Less than or equal to

● The relational operation is performed on two operands to returns 1 if

the expression is true, otherwise returns 0 if the expression is false.
● The ‘z’ is treated as ‘x’ in a relational operation.
Conditional Operators

Operator Number of operand Description

?: 3 conditional

Syntax:

<result> = <conditional_expression> ? <true_expression> :

<false_expression>
Example
module example
(
input a,b,
output equal,less_than,greater_than
);

assign equal=(a==b)?1’b1:1’b0;
assign less_than =(a<b)?1’b1:1’b0;
assign greater_than =(a>b)?1’b1:1’b0;

endmodule
Shift Operators
Operators Number of operands Description

<< 2 Logical left shift

>> 2 Logical right shift

>>> 2 Arithmetic right shift

● Logical shift operators shift a vector to left or right by a specified number of bits and fill vacant bit positions
with zeros.
● Arithmetic shift operators shift a vector to right by a specified number of bits and fill vacant bit positions
with sign bit if an expression is signed, otherwise with zeros.
Example
module shift_4bit ( data_in = 4'b1010; // Decimal 10
input [3:0] data_in,
output [3:0] lshift,
output [3:0] rshift,
Operation Result Comment
output [3:0] arith_lshift,
output [3:0] arith_rshift data_in << 1 0100 (4) Left shift by 1 bit
); data_in >> 1 0101 (5) Right shift by 1 bit
data_in <<< 1 0100 (4) Same as <<
assign lshift = data_in << 1; Same as >> if
assign rshift = data_in >> 1; data_in >>> 1 0101 (5)
unsigned
assign arith_lshift = data_in <<< 1;
assign arith_rshift = data_in >>> 1;

endmodule
Reduction Operators
Operators Number of operands Description

& 1 Reduction and

| 1 Reduction or

^ 1 Reduction xor

~& 1 Reduction nand

~| 1 Reduction nor

~^ or ^~ 1 Reduction xnor

● The reduction operators give 1-bit output by performing the bitwise operation over
a single vector operand.
● Reduction operators work bit by bit from right to left.
Example
module reduction_example(
Input [3:0]a,
Output and_reduction, or_reduction, xor_reduction, nand_reduction, nor_reduction, xnor_reduction);
assign and_reduction = &a; // AND of all bits
assign or_reduction = |a; // OR of all bits
assign xor_reduction = ^a; // XOR of all bits
assign nand_reduction= ~&a; // NAND of all bits
Output
assign nor_reduction = ~|a; // NOR of all bits
and_reduction = 0
assign xnor_reduction= ~^a; // XNOR of all bits or_reduction = 1
endmodule xor_reduction = 1
nand_reduction = 1
nor_reduction = 0
xnor_reduction = 0
Concatenation Operator

Operator Number of operands Description

{} ‘N’ number concatenation

module example(
input [3:0] a,b, Output
output [7:0] concat_result ); a= 4'b1010;
b = 4'b0101
concat_result =
assign concat_result = {a, b}; 8'b10100101 (decimal
endmodule 165)
Replication Operator

Operator Number of operands Description

{{}} ‘N’ number replication

module example
( Output
Input reg [1:0]
result = 6'b101010
output [5:0] result); (decimal 42)
assign result = {3{a}};
endmodule
Comments
● There are two ways of writing comments in verilog.

● /* This is an example of multi-line comment

Hello everyone */
● //This is a single line comment.
Types of Modeling
● "modeling" refers to the style or abstraction level used to describe digital hardware behavior

and structure.

● Verilog supports multiple modeling styles, allowing you to describe a circuit in different ways

depending on your design stage, complexity, and purpose.

1. Structural (Gate-level) Modeling

2. Dataflow Modeling

3. Behavioral Modeling
Structural Modeling (Gate-level)
• Describes the circuit using gate-level components.

• Represents physical hardware with logic gates.

• Useful for very low-level design.

• Example:
and a1 (out1, in1, in2);
or o1 (out2, in1, in2);
module and_gate
(
input A, input B,
output Y,
);

and (Y, A, B); // Built-in AND gate

endmodule
Dataflow Modeling
• Focuses on how data flows through the system.

• Uses continuous assignments with 'assign'.

• Efficient for simple combinational logic.

• Example:

assign out = (a & b) | (~a & c);

module and_gate
(
input A, input B,
output Y
);
assign Y = A & B; // Bitwise AND
endmodule
Behavioral Modeling
• Describes what the circuit does (high-level logic).
• Uses always block.
• Best for describing sequential logic.
• Example:
always @(posedge clk) begin
if (reset)
q <= 0;
else
q <= d;
end
module and_gate
( input A, input B,
output reg Y
);
always @ (A or B) begin
Y = A & B;
end
endmodule
 What is Module Instantiation?
• Module instantiation is the process of including one Verilog module
inside another.
• The parent module becomes the top-level module and the included
module is known as the child or DUT (Device Under Test).
• This allows modular design and reusability of code.
 Syntax of Module Instantiation
module_name instance_name (
.port_name(signal_name),
.port_name(signal_name),
...
);

• module_name: Name of the design module.

• instance_name: Any user-defined name for the instance.
• port_name: Name of the port in the module.
• signal_name: Corresponding signal used in the parent module.
 Example: AND Gate Module
module and_gate (
input wire a,
input wire b,
output wire y
);
assign y = a & b;
endmodule
 Instantiating the AND Gate Module
module top_module;
reg a, b;
wire y;

and_gate uut (
.a(a),
.b(b),
.y(y)
);
endmodule

• 'uut' is the instance name (Unit Under Test).

 Types of Module Instantiation
• There are two types of module instantiation in Verilog:

1. Positional Port Mapping

2. Named Port Mapping
 Positional Port Mapping
module top_module;
reg a, b;
wire y;

and_gate uut (a, b, y);

endmodule

• Ports are mapped in the exact order as declared in the module

definition.
• Simple but error-prone if the order is incorrect.
 Named Port Mapping
module top_module;
reg a, b;
wire y;

and_gate uut (
.a(a),
.b(b),
.y(y)
);
endmodule

• Ports are explicitly mapped by name.

• Easier to read and maintain.
• Preferred method in larger designs.
 What is a Testbench?
• A testbench is a Verilog code used to simulate and
verify the functionality of a design module.
• It does not synthesize – used only for simulation.
• It mimics inputs and produces outputs.
 Purpose of a Testbench
• Validate that the module works as expected.
• Catch bugs early in the simulation phase.
• Ensure correct timing, logic, and edge cases.
 Signal Declaration in Testbench
• In a Verilog testbench, you don't define the
ports using input/output/inout like in a design
module.

• - Use `reg` for inputs going into the design (the

testbench drives these signals).
• - Use `wire` for outputs coming from the
design (the DUT drives these signals).
 Key Components of a Testbench
• 1. DUT Instantiation (Device Under Test)
• 2. Signal Declaration
• 3. Stimulus Generation
• 4. Monitoring/Display
• 5. Clock & Reset (if needed)
 Basic Testbench Structure
module testbench;
reg a, b; // Inputs to the DUT (and_gate)
wire y; // Output from the DUT

// Instantiate the Device Under Test (DUT)

and_gate uut ( .a(a), .b(b),.y(y) );
initial begin
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
initial begin
$monitor("Time = %0t | a = %b, b = %b, y = %b", $time, a, b, y);
end
endmodule
 Step-by-Step Explanation
• 1. Module Declaration – no ports.
• 2. Signal Declaration – match the DUT.
• 3. DUT Instantiation – map ports correctly.
• 4. Initial Block – apply different inputs.
• 5. $monitor/$display – observe outputs.
 Example – Clock Generator
reg clk;
initial begin
clk = 0;
end
always #5 clk = ~clk;