1) Design a 4-Bit Adder 2) 4-Bit Shift and 3)32-Bit ALU Supporting 4-Logical and 4-Arithmetic

// 4 bit Adder add Multiplier operations, using case and if statement forALU
module module module alu234(input [31:0] A,B, input [15:0]
Adder4bit(a,b,cin,sum,cout); shift(clk,rst,A,B,C); ALU_Sel,output [31:0] ALU_Out, output CarryOut );
input [3:0] a,b; parameter m=4, reg [31:0] ALU_Result;
input cin; n=4; assign ALU_Out = ALU_Result;
output [3:0]sum; integer i; always @(A,B,ALU_Sel)
output cout; input clk,rst; begin
assign {cout,sum}=a+b+cin; input[m-1:0]A; case(ALU_Sel)
endmodule input [n-1 : 0]B; 4'b0000: ALU_Result = A + B ;
module TestModule; output reg[m+n-1 4'b0001: ALU_Result = A - B ;
// Inputs :0]C; 4'b0010: ALU_Result = A * B;
reg [3:0] a; reg [m+n-1 :0]A1; 4'b0011: ALU_Result = ~A;
reg [3:0] b;` reg [n-1 :0] B1; 4'b0100: ALU_Result = A<<1;
reg cin; always@(posedge 4'b0101: ALU_Result = A>>1;
// Outputs clk or posedge rst) 4'b0110: ALU_Result = {A[2:0],A[3]};
wire [3:0] sum; begin 4'b0111: ALU_Result = {A[0],A[3:1]};
wire cout; if(rst) 4'b1000: ALU_Result = A & B;
// Instantiate the Unit Under Test begin 4'b1001: ALU_Result = A | B;
(UUT) C=0; 4'b1010: ALU_Result = A ^ B;
Adder4bit uut end 4'b1011: ALU_Result = ~(A | B);
(.a(a),.b(b),.cin(cin),.sum(sum),.cou else 4'b1100: ALU_Result = ~(A & B);
t(cout)); begin 4'b1101: ALU_Result = ~(A ^ B);
initial begin C=0; 4'b1110: ALU_Result = (A>B)?4'd1:4'd0 ;
// Initialize Inputs A1[m-1:0]=A; 4'b1111: ALU_Result = (A==B)?4'd1:4'd0 ;
a = 0; A1[m+n-1:m]=0; default: ALU_Result = A + B ;
b = 0; B1=B; endcase
cin = 0; for(i=0; i<n; i=i+1) end
// Wait 100 ns for global reset to begin endmodule
finish if (B1[i]==1'b0) alu testbench
#50; begin module alu234tb;
a = 2; C=C+0; reg [31:0] A;reg [31:0] B; reg [15:0] ALU_Sel;
b = 3; end wire [31:0] ALU_Out;wire CarryOut;
cin = 1; else if(B1[i]==1'b1) alu234 uut (.A(A),
#50; begin .B(B),.ALU_Sel(ALU_Sel),.ALU_Out(ALU_Out),.CarryOut(C
a = 5; C=C+(A1<<i); arryOut));
b = 3; end initial begin
cin = 0; end A = 2;
#20; end B = 3;
cin = 1;// Wait 100 ns for global end ALU_Sel = 0;
reset to finish endmodule #100;
#100; TEST BENCH A = 1;
end module sss_tb; B = 3;
endmodule // Inputs ALU_Sel = 1;
#100;
reg clk;
A = 5;
reg rst;
B = 7;
reg [3:0] A;
ALU_Sel = 8;
reg [3:0] B;
#100;
wire [7:0] C;
end
shift uut (.clk(clk),
endmodule
.rst(rst), .A(A),
.B(B), .C(C));
initialbegin
clk=1'b1;
forever #4 clk=~clk;
end
initial
begin
rst=1;
#2 rst =0;
A=4'b1111;
B=4'b1111;
#20
rst=1;
#2 rst =0;
A=4'b1011;
B=4'b1100;
end
endmodule
4) Flip-Flops ( D,SR and JK ) JK FLIPFLOP SR FLIPFLOP
D FLIPFLOP module jkff(input reset, input clk, module srff(input reset, input clk,
module dff(clk,rst,d,q,qb); input j, input k, output reg q, output input s, input r, output reg q, output
input clk, rst,d ; qnot); qnot);
output q; always @(posedge clk) always @(posedge clk)
output qb; if (reset) q<=1'b0; if (reset) q<=1'b0;
reg ff; else else
always@(posedge clk or posedge rst) case ({j, k}) case ({s,rk})
begin 2'b00: q<=q; 2'b00: q<=q;
if (rst) 2'b01: q<=1'b0; 2'b01: q<=1'b0;
begin 2'b10: q<=1'b1; 2'b10: q<=1'b1;
ff <= 0; 2'b11: q<= ~q; 2'b11: q<= 1’bz;
end endcase endcase
else assign qnot=~q; assign qnot=~q;
begin endmodule endmodule
ff <= d; test bench of jk test bench of srff
end module jktb1; module srtb1;
end reg reset;reg clk;reg j;reg k;wire reg reset;reg clk;reg sj;reg r;wire
assign q = ff; q;wire qnot;jkff uut (.reset(reset), q;wire qnot;
assign qb = ~ff; .clk(clk),.j(j),.k(k),.q(q),.qnot(qnot)); jkff uut (.reset(reset),
endmodule initial begin .clk(clk),.s(s),.r(r),.q(q),.qnot(qnot));
test bench of Dff clk=0; initial begin
module dfftb; forever #50 clk=~clk; clk=0;
reg d; reg clk;reg rst; end forever #50 clk=~clk;
wire q; wire qbar; initial begin end
dff uut reset = 1; initial begin
(.d(d),.clk(clk),.rst(rst),.q(q),.qbar(qbar)); j = 0; reset = 1;
initial begin k = 0; s = 0;
clk=0; #100; r = 0;
forever #50 clk=~clk; reset = 0; #100;
end j = 0; reset = 0;
initial begin k = 1; s = 0;
rst = 1; #100; r = 1;
d = 0; reset = 0; #100;
#100; j = 1; reset = 0;
rst = 0; k = 0; s = 1;
d = 0; #100; r = 0;
#100; reset = 0; #100;
rst = 0; j = 0; reset = 0;
d =1; k = 0; s = 0;
#100; #100; r = 0;
rst = 0; reset = 0; #100;
d = 0; j = 1; reset = 0;
#100; k = 1; s = 1;
end #100; r = 1;
endmodule end #100;
endmodule end
endmodule
5)Four bit Synchronous MOD-N counter with Asynchronous reset
module modN_ctr
#(parameter N = 10,
parameter WIDTH = 4)
( input clk,
input rstn,
output reg[WIDTH-1:0] out);
always @ (posedge clk) begin
if (!rstn) begin
out <= 0;
end else begin
if (out == N-1)
out <= 0;
else
out <= out + 1;
end
end
endmodule
Testbench
module tb;
parameter N = 10;
parameter WIDTH = 4;
reg clk;
reg rstn;
wire [WIDTH-1:0] out;
modN_ctr u0
(.clk(clk),
.rstn(rstn),
.out(out));
always #10 clk = ~clk;
initial begin
{clk, rstn} <= 0;
$monitor ("T=%0t rstn=%0b out=0x%0h", $time, rstn, out);
repeat(2) @ (posedge clk);
rstn <= 1;
repeat(20) @ (posedge clk);
$finish;
end
endmodule

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