Functional Components of a Computer

Computer: A computer is a combination of hardware and software resources which integrate

together and provides various functionalities to the user. Hardware are the physical components of
a computer like the processor, memory devices, monitor, keyboard etc. while software is the set of
programs or instructions that are required by the hardware resources to function properly.

There are a few basic components that aids the working-cycle of a computer i.e. the Input- Process-
Output Cycle and these are called as the functional components of a computer. It needs certain
input, processes that input and produces the desired output. The input unit takes the input, the
central processing unit does the processing of data and the output unit produces the output. The
memory unit holds the data and instructions during the processing.

• Input Unit :The input unit consists of input devices that are attached to
the computer. These devices take input and convert it into binary
language that the computer understands. Some of the common input
devices are keyboard, mouse, joystick, scanner etc.
• Central Processing Unit (CPU) : Once the information is entered into
the computer by the input device, the processor processes it. The CPU is
called the brain of the computer because it is the control center of the
 computer. It first fetches instructions from memory and then interprets
them so as to know what is to be done. If required, data is fetched from
memory or input device. Thereafter CPU executes or performs the
required computation and then either stores the output or displays on the
output device. The CPU has three main components which are
responsible for different functions – Arithmetic Logic Unit (ALU), Control
Unit (CU) and Memory registers
• Arithmetic and Logic Unit (ALU) : The ALU, as its name suggests
performs mathematical calculations and takes logical decisions.
Arithmetic calculations include addition, subtraction, multiplication and
division. Logical decisions involve comparison of two data items to see
which one is larger or smaller or equal.
• Control Unit : The Control unit coordinates and controls the data flow in
and out of CPU and also controls all the operations of ALU, memory
registers and also input/output units. It is also responsible for carrying out
all the instructions stored in the program. It decodes the fetched
instruction, interprets it and sends control signals to input/output devices
until the required operation is done properly by ALU and memory.
• Memory Registers : A register is a temporary unit of memory in the CPU.
These are used to store the data which is directly used by the processor.
Registers can be of different sizes(16 bit, 32 bit, 64 bit and so on) and
each register inside the CPU has a specific function like storing data,
storing an instruction, storing address of a location in memory etc. The
user registers can be used by an assembly language programmer for
storing operands, intermediate results etc. Accumulator (ACC) is the main
register in the ALU and contains one of the operands of an operation to
be performed in the ALU.
• Memory : Memory attached to the CPU is used for storage of data and
instructions and is called internal memory The internal memory is divided
into many storage locations, each of which can store data or instructions.
Each memory location is of the same size and has an address. With the
help of the address, the computer can read any memory location easily
without having to search the entire memory. when a program is executed,
it’s data is copied to the internal memory and is stored in the memory till
the end of the execution. The internal memory is also called the Primary
memory or Main memory. This memory is also called as RAM, i.e.
Random Access Memory. The time of access of data is independent of its
location in memory, therefore this memory is also called Random Access
memory (RAM).
• Output Unit : The output unit consists of output devices that are attached
with the computer. It converts the binary data coming from CPU to human
understandable form. The common output devices are monitor, printer,
plotter etc.
Introduction

What is CO(Computer Organization )?

➢ It is the study of internal working , structuring and implementation of a

computer system.

➢ Architecture in computer system refers to the externally visual

attributes of the system.

➢ Organization of computer system results in realization of architectural

specifications of a computer system.

Why study computer organization?

• Design better programs, including system software such as compilers,

operating systems, and device drivers.

• Optimize program behavior.

• Evaluate (benchmark) computer system performance.

• Understand time, space, and price tradeoffs.

Definition of Computer design

Computer design is the process of planning and creating the hardware and
software components of a computer system. This involves defining the
architecture and specifications of the system, as well as selecting and
implementing the appropriate technologies and components to meet the
desired goals and requirements. Computer design encompasses both the
functional and aesthetic aspects of a computer system, with the ultimate goal
of creating a functional, efficient, and user-friendly computing device.

computer design is important because it affects the performance, user

experience, and security of a computer system. A well-designed computer
system can provide optimal performance, a pleasant user experience, and
strong security, making ita valuable asset for individuals and organizations
alike
Definition of Computer Architecture

Computer architecture is a specification describing how computer software

and hardware connect and interact to create a computer network.

Computer Architecture is considered to be those attributes of a system that

are visible to the user like addressing techniques, instruction sets, and bits
used for data, and have a direct impact on the logic execution of a program,
It defines the system in an abstract manner, It deals with What does the
system do.

Computer Architecture can be divided into mainly three categories, which are
as follows −

• Instruction set Architecture or ISA − Whenever an instruction is given

to processor, its role is to read and act accordingly. It allocates memory
to instructions and also acts upon memory address mode (Direct
Addressing mode or Indirect Addressing mode).
• Micro Architecture − It describes how a particular processor will
handle and implement instructions from ISA.
• System design − It includes the other entire hardware component
within the system such as virtualization, multiprocessing.

Computer Architecture VS Computer Organization

Computer Computer
Architecture Organization

Concerned with the way hardware Concerned with the structure and
components are behaviour of a
connected together to form a computer system as seen by the
computer system. user.
Acts as the interface between Deals with the components of a
hardware and software. connection in a system.

Helps us to understand the Tells us how exactly all the units in

functionalities of a system. the system are arranged and
interconnected.
 A programmer can view Whereas Organization expresses
architecture in terms of the realization of
instructions, addressing modes architecture.
and registers.
While designing a computer An organization is done on the
system architecture is considered basis of architecture.
first.
Deals with high-level design issues. Deals with low-level design issues.

Architecture involves Logic Organization involves Physical

(Instruction sets, Addressing Components
modes, Data types, Cache (Circuit design, Adders, Signals,
optimization) Peripherals)

Instruction Set Architecture (ISA)

• An Instruction Set Architecture (ISA) defines how the CPU is controlled

by the software.

• The ISA acts as an interface between the hardware and the software,
specifying both what the processor is capable of doing as well as how
it gets done.

The 3 most common types of ISAs are:

1) Stack - The operands are implicitly on top of the stack.

2) Accumulator - One operand is implicitly the accumulator.

3) General Purpose Register (GPR) - All operands are explicitely

mentioned, they are either registers or memory locations.

Lets look at the assembly code of

C = A + B;

in all 3 architectures:
 Stack Accumulator GPR

• PUSH A LOAD A LOAD R1,A

• PUSH B ADD B ADD R1,B

• ADD STORE C STORE R1,C

• POP C - -

The different features that need to be considered when designing the

instruction set architecture are:

• Types of instructions (Operations in the Instruction set)

• Types and sizes of operands

• Addressing Modes

• Addressing Memory

• Encoding and Instruction Formats

• Compiler related issues

Register

A digital system is an interconnection of digital hardware module that

accomplish a specific information-processing task.

The internal hardware organization of a digital computer is best defined by

specifying:

– The set of registers it contains and their function.

– The sequence of microoperations performed on the binary

information stored in the registers.

– The control that initiates the sequence of microoperations

Registers are a type of computer memory used to quickly accept, store, and
transfer data and instructions that are being used immediately by the CPU.

The registers used by the CPU are often termed as Processor registers.

A processor register may hold an instruction, a storage address, or any data

(such as bit sequence or individual characters).
The computer needs processor registers for manipulating data and a register
for holding a memory address.

Computer registers are designated by capital letters (sometimes followed by

numerals) to denote the function of the register.

For example, the register that holds an address for the memory unit is
usually called a memory address register and is designated by the name
MAR

Micro operation

• The operations on data stored in registers are called micro-operations.

A microoperation is an elementary operation performed on the
information stored in one or more registers.

• The result of the operation may replace the previous binary information
of a register or may be transferred to another register.

• Examples of microoperations are shift, count, clear, and load.

Register transfer language (RTL)

• The symbolic notation used to describe the microoperation transfers

among registers is called a register transfer language.

Representation of register

• The most common way to represent a register is by

1. a rectangular box with the name of the register inside as shown in (a).
2. Register is numbered in a sequence of 0 to (n-1) as shown in (b).
3. The numbering of bits in a register can be marked on the top of the box
as shown in (c).
4. A 16-bit register PC is divided into 2 parts- Bits (0 to 7) are assigned with
lower byte of 16-bit address and bits (8 to 15) are assigned with higher
bytes of 16-bit address as shown in (d).
Basic symbols of RTL

Register Transfer

The term Register Transfer refers to the availability of hardware logic circuits that can
perform a given micro-operation and transfer the result of the operation to the same
or another register.

Data Transfer from one register to another register is represented in symbolic form by
means of replacement operator. For instance, the following statement denotes a
transfer of the data of register R1 into register R2.

R2 ← R1

Register Transfer Operations

The operation performed on the data stored in the registers are referred to as
register transfer operations.
There are different types of register transfer operations:

1. Simple Transfer – R2 <- R1

• The content of R1 are copied into R2 without affecting the content of R1. It
is an unconditional type of transfer operation.

2. Conditional Transfer – P: R2 ← R1

• Typically, most of the users want the transfer to occur only in a

predetermined control condition. This can be shown by following if-then
statement:
If (P=1) then (R2 ← R1);
• Here P is a control signal generated in the control section.
• It is more convenient to specify a control function (P) by separating the
control variables from the register transfer operation.
• For instance, the following statement defines the data transfer operation
under a specific control function (P).
P: R2 ← R1

• Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs
of the register R1 are connected to the 'n' inputs of register R2.
• A load input is activated by the control variable 'P' which is transferred to the
register R2.

3. Simultaneous Operations –
If 2 or more operations are to occur simultaneously then they are separated with
comma (,). If the control function P=1, then load the content of R1 into R2 and at
the same clock load the content of R2 into R1.

MICRO OPERATIONS

A micro operation is an elementary operation performed with the data stored in

registers. The microoperations most often encountered in digital computers are
classified into four categories:

1. Register transfer microoperations transfer binary information from one

register to another.

2. Arithmetic micro operations perform arithmetic operation on numeric data

stored in registers.

3. Logic micro operations perform bit manipulation operations on non-numeric

data stored in registers.

4. Shift microoperations perform shift operations on data stored in registers.

Types of MICRO OPERATIONS

ARITHMETIC MICRO OPERATIONS

The basic Arithmetic Micro-operations are classified in the following categories:

1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift

Some additional Arithmetic Micro-operations are classified as:

1. Add with carry

2. Subtract with borrow
3. Transfer/Load, etc.

The following table shows the symbolic representation of various Arithmetic

Micro-operations.
 Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred

to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are

transferred to R3.

R2 ← R2' Complement the contents of R2 (1's

complement)

R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2

(subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

The arithmetic microoperation defined by the statement R3 ← R1 + R2 specifies

an add microoperation. It states that the contents of register R1 are added to
the contents of register R2 and the sum transferred to register R3.

To implement this statement with hardware we need three registers and the
digital component that performs the addition operation.

Subtraction is most often implemented through complementation and addition.

Instead of using the minus operator, we can specify the subtraction by the following
statement: R3 ← R1 + R2 + 1. R2 is the symbol for the 1’s complement of R2.
Adding 1 to the 1’s complement produces the 2’s complement. Adding the contents
of R1 to the 2’s complement of R2 is equivalent to R1 – R2.
The increment and decrement micro-operations are symbolized by plus one and
minus-one operations, respectively. These micro-operations are performed with
a combinational circuit or with a binary up-down counter.

Binary adder

• A Binary Adder is a digital circuit that performs the arithmetic sum of two
binary numbers provided with any length.

• A Binary Adder is constructed using full-adder circuits connected in series,

with the output carry from one full-adder connected to the input carry of the
next full-adder.

• The following block diagram shows the interconnections of four full-adder

circuits to provide a 4-bit binary adder.

• The augend bits (A) and the addend bits (B) are designated by subscript
numbers from right to left, with subscript '0' denoting the low-order bit.

• The carry inputs starts from C0 to C3 connected in a chain through the full-
adders. C4 is the resultant output carry generated by the last full-adder
circuit.

• The output carry from each full-adder is connected to the input carry of the
next-high-order full-adder.
 • The sum outputs (S0 to S3) generates the required arithmetic sum of
augend and addend bits.

• The n data bits for the A and B inputs come from different source
registers. For instance, data bits for A input comes from source register R1
and data bits for B input comes from source register R2.

• The arithmetic sum of the data inputs of A and B can be transferred to a

third register or to one of the source registers (R1 or R2).

Binary Adder-Subtractor

• The Subtraction micro-operation can be done easily by taking the 2's

compliment of addend bits and adding it to the augend bits.

• Note: The 2's compliment can be obtained by taking the 1's compliment
and adding one to the least significant pair of bits. The 1's compliment can
be implemented with inverters, and one can be added to the sum through
the input carry.

• The Arithmetic micro-operations like addition and subtraction can be

combined into one common circuit by including an exclusive-OR gate with
each full adder.

• When the mode input (M) is at a low logic, i.e. '0', the circuit act as an
adder and when the mode input is at a high logic, i.e. '1', the circuit act as
a subtractor.
 • The exclusive-OR gate connected in series receives input M and one of
the inputs B.

• When M is at a low logic, we have B⊕ 0 = B.

The full-adders receive the value of B, the input carry is 0, and the circuit
performs A plus B.

• When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.

The B inputs are complemented, and a 1 is added through the input carry.
The circuit performs the operation A plus the 2's complement of B.

Binary Incrementer

• The increment micro-operation adds one binary value to the value of

binary variables stored in a register. For instance, a 4-bit register has a
binary value 0110, when incremented by one the value becomes 0111.

• The increment micro-operation is best implemented by a 4-bit

combinational circuit incrementer. A 4-bit combinational circuit incrementer
can be represented by the following block diagram.

• A logic-1 is applied to one of the inputs of least significant half-adder, and

the other input is connected to the least significant bit of the number to be
incremented.

• The output carry from one half-adder is connected to one of the inputs of
the next-higher-order half-adder.
 • The binary incrementer circuit receives the four bits from A0 through A3,
adds one to it, and generates the incremented output in S0 through S3.

• The output carry C4 will be 1 only after incrementing binary 1111.

Arithmetic circuit

Arithmetic circuits can perform seven different arithmetic operations using a

single composite circuit.
It uses a full adder (FA) to perform these operations. A multiplexer (MUX) is used
to provide different inputs to the circuit in order to obtain different arithmetic
operations as outputs.

Fig: 4.9 : 4- bit arithmetic circuit

Logical Micro operations
Shift micro-operations

• Shift micro-operations are those micro-operations that are used for serial
transfer of information.

• These are also used in conjunction with arithmetic micro-operation, logic

micro-operation, and other data-processing operations.

• There are three types of shifts micro-operations:

1. Logical
 2. Circular

3. Arithmetic

Symbolic Designation Description

R ← shl R Shift-left register R

R ← shr R Shift-right register R

R ← cil R Circular shift-left register R

R ← cir R Circular shift-right register R

R ← ashl R Arithmetic shift-left R

R ← ashr R Arithmetic shift-right R

Logical shifts micro-operations

2. Circular shifts micro-operations :
The circular shift circulates the bits in the sequence of the register around the
both ends without any loss of information. cil ad cir symbols are used for the
circular shift left and right.
3. Arithmetic shifts micro-operations
Hardware implementation of 4 bit combinational circuit shifter

Fig: 4-12 4 bit combinational circuit shifter

Arithmetic logic shift unit (ALU)
We can combine and make one ALU with common selection variables by
adding arithmetic, logic, and shift circuits. We can see the, One stage of an
arithmetic logic shift unit in the diagram below. Some particular micro
operations are selected through the inputs S1 and S0.

4 x 1 multiplexer at the output chooses between associate arithmetic output

between Di and a logic output in Ei. The data in the multiplexer are selected
through inputs S3 and S2 and the other two data inputs to the multiplexer
obtain the inputs Ai – 1 for the shr operation and Ai + 1 for he shl operation.
The circuit whose one stage is given in the above diagram provides 8
arithmetic operations, 4 logic operations, and 2 shift operations, and Each
operation is selected by the 5 variables S3, S2, S1, S0, and Cin.
Note: The output carry Ci + 1 of a specified arithmetic stage must be attached
to the input carry Ci of the next stage in the sequence.
The below table shows the 14 operations perform by the Arithmetic Logic
Unit:
1. The first 8 are arithmetic operations which are selected by S3 S2 =
00
2. The next 4 are logic operations which are selected by S3 S2 = 01
3. The last two are shift operations which are selected by S3 S2 = 10
& 11

Instruction Codes
Computer Registers

list of some of the most common registers used in a basic computer

Register Symbol Number of bits Function

Data register DR 16 Holds memory

operand

Address AR 12 Holds address

register for the memory

Accumulator AC 16 Processor
register

Instruction IR 16 Holds
register instruction code

Program PC 12 Holds address

counter of the
instruction

Temporary TR 16 Holds
register temporary data

Input register INPR 8 Carries input

character

Output register OUTR 8 Carries output

character
• The Memory unit has a capacity of 4096 words, and each word contains 16
bits.

• The Data Register (DR) contains 16 bits which hold the operand read from
the memory location.

• The Memory Address Register (MAR) contains 12 bits which hold the
address for the memory location.

• The Program Counter (PC) also contains 12 bits which hold the address of
the next instruction to be read from memory after the current instruction is
executed.

• The Accumulator (AC) register is a general purpose processing register.

• The instruction read from memory is placed in the Instruction register (IR).

• The Temporary Register (TR) is used for holding the temporary data during
the processing.

• The Input Registers (IR) holds the input characters given by the user.

• The Output Registers (OR) holds the output after processing the input data.
Common Bus System

• The basic computer has eight registers, a memory unit, and a control unit
Paths must be provided to transfer information from one register to another
and between memory and registers.
• The number of wires will be excessive if connections are made between the
outputs of each register and the inputs of the other registers.
• A more efficient scheme for transferring information in a system with many
registers is to use a common bus.
• The connection of the registers and memory of the basic computer to a
common bus system is shown in Fig. above. The outputs of seven registers
and memory are connected to the common bus.
• The specific output that is selected for the bus lines at any given time is
determined from the binary value of the selection variables S2, S1, and S0.
• The number along each output shows the decimal equivalent of the required
binary selection. For example, the number along the output of DR is 3.
• The 16-bit outputs of DR are placed on the bus lines when S2S1S0 = 011
since this is the binary value of decimal 3.
• The lines from the common bus are connected to the inputs of each register
and the data inputs of the memory. The particular register whose LD (load)
input is enabled receives the data from the bus during the next clock pulse
transition.
• The memory receives the contents of the bus when its write input is
activated. The memory places its 16-bit output onto the bus when the read
input is activated and S2S1S0 = 111.
• Four registers, DR, AC, IR, and TR, have 16 bits each. Two registers, AR
and PC, have 12 bits each since they hold a memory address. When the
contents of AR or PC are applied to the 16-bit common bus, the four most
significant bits are set to 0's.
• When AR or PC receive information from the bus, only the 12 least
significant bits are transferred into the register. The input register INPR and
the output register OUTR have 8 bits each and communicate with the eight
least significant bits in the bus.
• INPR is connected to provide information to the bus but OUTR can only
receive information from the bus.
• This is because INPR receives a character from an input device which is
then transferred to AC. OUTR receives a character from AC and delivers it
to an output device. There is no transfer from OUTR to any of the other
registers.
• The 16 lines of the common bus receive information from six registers and
the memory unit. The bus lines are connected to the inputs of six registers
and the memory. Five registers have three control inputs: LD (load), INR
(increment), and CLR (clear).
• This type of register is equivalent to a binary counter with parallel load and
synchronous clear. The increment operation is achieved by enabling the
count input of the counter. Two registers have only a LD input.
• The input data and output data of the memory are connected to the common
bus, but the memory address is connected to AR. Therefore, AR must
always be used to specify a memory address.
• By using a single register for the address, we eliminate the need for an
address bus that would have been needed otherwise. The content of any
register can be specified for the memory data input during a write operation.
 Similarly, any register can receive the data from memory after a read
operation except AC .
• The 16 inputs of AC come from an adder and logic circuit. This circuit has
three sets of inputs. One set of 16-bit inputs come from the outputs of AC .
They are used to implement register microoperations such as complement
AC and shift AC .
• Another set of 16-bit inputs come from the data register DR. The inputs from
DR and AC are used for arithmetic and logic rnlcrooperations, such as add
DR to AC or AND DR to AC.
• The result of an addition is transferred to AC and the end carry-out of the
addition is transferred to flip-flop E (extended AC bit). A third set of 8-bit
inputs come from the input register INPR.
• Note that the content of any register can be applied onto the bus and an
operation can be performed in the adder and logic circuit during the same
clock cycle. The clock transition at the end of the cycle transfers the content
of the bus into the designated destination register and the output of the
adder and logic circuit into AC.
• For example, the two microoperations
DR ← AC and AC ← DR
can be executed at the same time. This can be done by placing the content
of AC on the bus (with S2S1S0 = 100), enabling the LD (load) input of DR,
transferring the content of DR through the adder and logic circuit into AC,
and enabling the LD (load) input of AC, all during the same clock cycle.
• The two transfers occur upon the arrival of the clock pulse transition at the
end of the clock cycle.

Computer Instructions

A basic computer has three instruction code formats which are:

• Memory - reference instruction

• Register - reference instruction

• Input-Output instruction
Memory - reference instruction

In Memory-reference instruction, 12 bits of memory is used to specify an address

and one bit to specify the addressing mode 'I'.

I =0 for direct addressing and

I = 1 for indirect addressing

Register - reference instruction

The Register-reference instructions are represented by the Opcode 111 with a 0

in the leftmost bit (bit 15) of the instruction.

Note: The Operation code (Opcode) of an instruction refers to a group of bits that
define arithmetic and logic operations such as add, subtract, multiply, shift, and
compliment.

A Register-reference instruction specifies an operation on or a test of the AC

(Accumulator) register.

Input-Output instruction

Just like the Register-reference instruction, an Input-Output instruction does not

need a reference to memory and is recognized by the operation code 111 with a
1 in the leftmost bit of the instruction.
The remaining 12 bits are used to specify the type of the input-output operation
or test performed.

Note: The three operation code bits in positions 12 through 14 should be equal to
111. Otherwise, the instruction is a memory-reference type, and the bit in position
15 is taken as the addressing mode I.

When the three operation code bits are equal to 111, control unit inspects the bit
in position 15. If the bit is 0, the instruction is a register-reference type. Otherwise,
the instruction is an input-output type having bit 1 at position 15.
Timing and Control

There are two major types of control organization

➢ Hardwired Control

➢ Microprogrammed Control

• The Hardwired Control organization involves the control logic to be

implemented with gates, flip-flops, decoders, and other digital circuits.

• The Microprogrammed Control organization is implemented by using the

programming approach.
The block diagram of Timing and Control is shown in Fig

It consists of two decoders,a sequence counter, and a number of control logic

gates.

An instruction read from memory is placed in the instruction register (IR).position

of this register in the common bus system where it is divided into three parts:

1) the 1 bit,
2) the operation code, and
3) bits 0 through 11.

The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. The
eight outputs of the decoder are designated by the symbols D0 through D7.

The subscripted decimal number is equivalent to the binary value of the

corresponding operation code.

Bit 15 of the instruction is transferred to a flip-flop designated by the symbol I.

Bits 0 through 11 are applied to the control logic gates.

 The 4-bit sequence counter can count in binary from 0 through 15. The outputs of
the counter are decoded into 16 timing signals T0 through T15.

• The sequence counter SC can be incremented or cleared synchronously.

Most of the time, the counter is incremented to provide the sequence of
timing signals out of the 4 x 16 decoder. Once in a while, the counter is
cleared to 0, causing the next active timing signal to be T0.

• As an example, consider the case where SC is incremented to provide

timing signals T0, T1, T2, T3, and T4 in sequence.

• At time T4, SC is cleared to 0 if decoder output D3 is active. This is expressed

symbolically by the statement.

D3T4: SC <__ 0

• The sequence counter SC responds to the positive transition of the clock.

• Initially, the CLR input of SC is active. The first positive transition of the clock
clears SC to 0, which in tum activates the timing signal T 0 out of the decoder.

• T0 is active during one clock cycle. The positive clock transition

labeled T0 in the dagram will trigger only those registers whose control
inputs are transition, to timing signal T 0.
 • SC is incremented with every positive clock transition unless its CLR input
is active. This produces the sequence of timing signals T0, T1, T2, T3 ,T4 and
so on, as shown in the dagram.

• If SC is not cleared, the timing signals will continue with T5, T6 up to T15 and
back to T 0

• The last three waveforms in Fig show how SC is cleared when D 3T4 = 1.
Output D3 from the operation decoder becomes active at the end of timing
signal T2.

• When timing signal T 4 becomes active, the output of the AND gate that
implements the control function D 3T4 becomes active.

• This signal is applied to the CLR input of SC. On the next positive clock
transition (the one marked T4 in the diagram) the counter is cleared to 0.

• This causes the timing signal T 0 to become active instead of T 5 that would
have been active if SC were incremented instead of cleared.

• For example, the register transfer statement

T0: AR <__ PC

specifies a transfer of the content of PC into AR if timing signal T 0 is active. T0 is

active during an entire clock cycle intervaL During this time the content of PC is
placed onto the bus (with S2S1S0 = 010) and the LD (load) input of AR is enabled.
The actual transfer does not occur until the end of the clock cycle when the clock
goes through a positive transition.

This same positive clock transition increments the sequence counter SC from 0000
to 0001 . The next clock cycle has T 1 active and T0 inactive.

Instruction cycle

A program residing in the memory unit of a computer consists of a sequence of

instructions. These instructions are executed by the processor by going through a
cycle for each instruction.

• In a basic computer, each instruction cycle consists of the following phases:

1) Fetch instruction from memory.

2) Decode the instruction.

3) Read the effective address from memory.

4) Execute the instruction.
 decoding.

Decoder output D7 =1 if the opcode is equal to binary 111.

If D7=1 , the instruction must be a Register – reference or Input-Output type.

• If D7=1 and I=1 , we have Input-Output instruction

• If D7=1 and I=0 , we have Register - reference instruction

If D7=0, the opcode must be one of the other seven values 000 through 110,
specifying a memory reference instruction.

Control now inspects the value of flip-flop I.

• If D7=0 and I=1 , we have Memory - reference instruction with an indirect

address. It is then necessary to read the effective address from memory.

• If D7=0 and I=0 , we have Memory - reference instruction with direct

address. It is not necessary to do anything since the effective address is
already in AR
A basic computer has three instruction code formats which are:

• Memory - reference instruction

• Register - reference instruction

• Input-Output instruction

Memory Reference Instruction – These instructions refer to memory address as

an operand. Specifies 12-bit address, 3-bit opcode (other than 111) and 1-bit
addressing mode for direct and indirect addressing.

Register - reference instruction - These instructions perform operations on

registers rather than memory addresses. The IR(14 – 12) is 111 (differentiates it
from memory reference) and IR(15) is 0 (differentiates it from input/output
instructions). The rest 12 bits specify register operation.

Input-Output instruction - These instructions are for communication between

computer and outside environment. The IR(14 – 12) is 111 (differentiates it from
memory reference) and IR(15) is 1 (differentiates it from register reference
instructions). The rest 12 bits specify I/O operation.