2288 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO.

4, AUGUST 2007

Fast-Processing Modulation Strategy for the

Neutral-Point-Clamped Converter With Total
Elimination of Low-Frequency Voltage
Oscillations in the Neutral Point
Josep Pou, Member, IEEE, Jordi Zaragoza, Pedro Rodríguez, Member, IEEE, Salvador Ceballos,
Vicenç M. Sala, Rolando P. Burgos, Member, IEEE, and Dushan Boroyevich, Fellow, IEEE

Abstract—This paper presents a novel modulation strategy for

a neutral-point-clamped converter. This strategy overcomes one of
the main problems of this converter, which is the low-frequency
voltage oscillation that appears in the neutral point under some
operating conditions. The proposed modulation strategy can com-
pletely remove this oscillation for all the operating points and
for any kind of loads, even unbalanced and nonlinear loads. The
algorithm is based on a carrier-based pulsewidth modulation. Nev-
ertheless, it can generate the maximum output-voltage amplitudes
that are attainable under linear modulation, such as space-vector
modulation. Furthermore, this technique can be implemented
with a very simple algorithm and, hence, can be processed very
quickly. The only drawback of this strategy is that the switching
frequencies of the devices are one third higher than those of
standard sinusoidal pulsewidth modulation. A control loop for Fig. 1. Three-level diode-clamped converter (or NPC converter).
balancing the voltages on the dc-link capacitors is also proposed.
This balancing strategy is designed, so that it does not further
increase the switching frequencies of the devices when it is applied
to the converter. The proposed modulation technique is verified by I. I NTRODUCTION
simulation and experiment.
Index Terms—Modulation strategy, neutral-point-clamped
(NPC) converter, pulsewidth-modulated inverters, three-level
M ULTILEVEL converters can provide more than two
voltage levels at the outputs. Consequently, they can
generate better output-voltage spectra than the classical two-
converter, voltage balance.
level converter. Another advantage of multilevel converters is
that their devices only have to stand a portion of the maximum
voltage that is generated at the outputs. These two features
make the use of multilevel converters practical for high-power
applications, in which high voltages must be handled. More-
over, the improved voltage spectra allow for the reduction of
Manuscript received May 9, 2006; revised July 25, 2006. This work was
supported in part by the Departament d’Universitats, Recerca i Societat de
the switching frequencies of the devices. This is crucial in
la Informació of the Generalitat de Catalunya under Grant 2005BE00481, high-power applications not only because of the potential for
Grant 2004BE00105, and Grant 2004BE00060, and in part by the Ministerio reducing switching losses but also because of the intrinsic
de Ciencia y Tecnologia of Spain under Project ENE2004-07881-C03-02 and
Project ENE2004-07881-C03-03. This work made use of the Engineering
length of the ton and toff switching times of these devices.
Research Center Shared Facilities, which are supported in part by the National The multilevel converter topology that is most extensively
Science Foundation under NSF Award EEC-9731677 and in part by the CPES applied at present is the neutral-point-clamped (NPC) converter
Industry Partnership Program. Any opinions, findings, and conclusions or
recommendations expressed in this material are those of the authors and do
[1], which is a three-level converter (Fig. 1). For proper oper-
not necessarily reflect those of the National Science Foundation. This paper ation of this topology, the neutral-point (NP) voltage must be
was presented at the 31st Annual Conference of the IEEE Industrial Electronics kept at one half of the dc-link voltage. If there is no external
Society, Raleigh, NC, November 6–10, 2005.
J. Pou, J. Zaragoza, P. Rodríguez, and V. M. Sala are with the Power Quality control for the voltages on the capacitors, the modulation
and Renewable Energy (QuPER) Research Group, Department of Electronic strategy must be designed to achieve voltage balancing between
Engineering, Technical University of Catalonia (UPC), 08222 Terrassa, Spain the capacitors. A great deal of research has been focused
(e-mail: [email protected]).
S. Ceballos is with the Energy Unit, Robotiker–Tecnalia Research Centre, on this field [2]–[6]. Although the averaged NP voltage can
48170 Zamudio, Spain. be controlled, a low-frequency NP voltage oscillation appears
R. P. Burgos and D. Boroyevich are with the Center for Power Electronics under some operating conditions. This is a significant drawback
Systems, Department of Electrical and Computer Engineering, Virginia Poly-
technic Institute and State University, Blacksburg, VA 24061 USA. of this converter since the dc-link capacitors and the devices
Digital Object Identifier 10.1109/TIE.2007.894788 of the converter must be designed to stand this oscillation.
0278-0046/$25.00 © 2007 IEEE
POU et al.: MODULATION STRATEGY FOR NPC CONVERTER WITH ELIMINATION OF VOLTAGE OSCILLATION 2289

Furthermore, if the modulation algorithm does not take into The two modified modulation signals for each phase will be
account this NP voltage oscillation, the output voltages will obtained from these signals, which must accomplish
contain low-frequency distortion. The feedforward pulsewidth
va′ = vap + van


modulation (PWM) [7] can completely avoid such voltage
distortion at the output; however, the low-frequency NP voltage vb′ = vbp + vbn (2)
oscillation still remains. vc′ = vcp + vcn
In the case of two back-to-back-connected NPC converters,
where vip ≥ 0 and vin ≤ 0, with i = {a, b, c}. The signals with
the two converters can share the task of balancing voltages on p
subscript p will only cross the upper carrier vcarrier ∈ [0, 1],
the dc-link capacitors [8], [9]. Therefore, voltage balance is
and the signals with subscript n will only cross the lower one
usually improved compared with that of a single NPC converter. n
vcarrier [−1, 0]. In Section IV, the process that is implemented
However, such improvement strongly depends on the modu-
when comparing the modulation signals with the carriers is
lation indices and power factors of the two converters at the
explained. It is anticipated that the connection to the NP
operating point.
(“0” level) is produced when
In [10], an interesting modulation strategy that is able to
cancel low-frequency voltage oscillation in the NP is proposed.  p
vip > vcarrier n
and vin < vcarrier or
The analysis is based on the use of virtual vectors in space- p n (3)
vip ≤ vcarrier and vin ≥ vcarrier .
vector modulation (SVM). Nevertheless, the algorithm is finally
implemented using a carrier-based PWM. With this approach, The two inner transistors of a phase leg of the converter
however, one has to deal with angles and trigonometric func- (Fig. 1) are in the ON state when the corresponding NP control
tions, which complicates its application. While the algorithm variable si0 ∈ {0, 1}, for i = {a, b, c}, is activated. In other
can achieve an averaged NP current that is equal to zero, since words, when a variable si0 takes the unity value, the subsequent
the voltages on the capacitors are not naturally balanced, they output phase is connected to the NP; otherwise, it takes the
preserve any original imbalance from the startup of the system. value of zero. When one phase leg is clamped to the NP, its
Furthermore, since the voltages are not regulated, they may output current is injected to this point. Therefore, current i0 can
deviate without control. be expressed as follows:
The modulation algorithm that is proposed in this paper
can also enable the locally averaged NP current to be equal i0 = sa0 ia + sb0 ib + sc0 ic . (4)
to zero. However, the algorithm is based on a very simple
treatment of the modulation signals, which is spectacularly In order to preserve voltage balance, the locally averaged NP
easy to implement, even in a low-feature microprocessor. This current must be zero. Therefore, it is necessary to operate with
strategy makes use of two carrier waveforms, just as in a the averaged NP current instead of the instantaneous current.
standard SPWM for three-level inverters. This paper also pro- The averaged NP current is obtained by using the moving
poses an efficient voltage-balancing compensator that neither average operator
increases the switching frequencies of the devices nor distorts
the output voltages. This paper ends by showing the simulation t
1
and experimental results and drawing some conclusions. x(t) = x(τ )dτ (5)
Ts
t−Ts

II. B ASIS OF THE M ETHOD where Ts is the sampling or switching period. Applying this
In SPWM, each phase is controlled by one modulation operator to (4), one obtains the following:
signal. In some approaches (e.g., [11] and [12]), a zero-
i0 = da0 ia + db0 ib + dc0 ic (6)
sequence signal is added to provide NP current control, which
consequently helps achieve voltage balance. However, the
in which di0 = si0 for i = {a, b, c}. Assuming that the fre-
low-frequency NP voltage oscillations cannot be completely
quency of the carriers is much higher than the frequency of the
removed by means of these strategies. The modulation tech-
modulation signals, the duty cycles can be expressed as follows:
nique that is proposed here is based on the use of two modu-
lation signals for each phase of the converter. The process to  +1
di0 = vin

− vip  , where vin +1
= vin + 1. (7)
obtain these signals is described here.
First, the original modulation signals are modified to obtain Equation (7) is obtained from (3) and using the basic
SVM patterns in order to achieve the maximum range for linear trigonometry in Fig. 2. As a result,
operation mode as follows:
 +1   +1   +1 
i0 = van − vap  ia + vbn − vbp  ib + vcn − vcp  ic . (8)
va′ = va − v0


vb′ = vb − v0 (1) If
vc′ = vc − v0
van − vap = vbn − vbp = vcn − vcp = vx or
+1 +1 +1
where v0 = (max(va , vb , vc ) + min(va , vb , vc ))/2. van − vap = vbn − vbp = vcn − vcp = 1 + vx (9)
2290 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Fig. 3. Scheme for the generation of vip and vin from vi (i = {a, b, c}).

Fig. 2. Two possible situations for the calculation of the duty cycle di0 : the solution for vap is
+1 +1 +1
(a) vin < vip and (b) vin > vip , for vin = vin + 1.

for 0 ≤ ωt ≤ 2π/3,
then the averaged NP current would be √
vap = (va − vc )/2 = ( 3/2)mSPWM cos(ωt − π/6)
for 2π/3 ≤ ωt ≤ 4π/3, vap = 0
i0 = |1 + vx |(ia + ib + ic ). (10)
for 4π/3 ≤ ωt ≤ 2π,
√
Since the neutral of the load is open (Fig. 1) or is just vap = (va − vb )/2 = ( 3/2)mSPWM cos(ωt + π/6)
a triangle-connected load, there is no zero sequence in the (14)
current. Subsequently, the sum of the output currents is always
zero (ia + ib + ic = 0); hence, i0 becomes zero. and that for van is
In conclusion, the problem of maintaining the locally aver-
aged voltages on the dc-link capacitors constant is reduced to for 0 ≤ ωt ≤ π/3 and 5π/3 ≤ ωt ≤ 2π, van = 0
find a proper value for vx in (9). An infinite number of solutions
can be found; however, one particularly interesting solution can for π/3 ≤ ωt ≤ π,
√
achieve minimum switching frequencies in the devices of the

van = (va − vb )/2 = 3/2 mSPWM cos(ωt + π/6)
converter. This solution is found by forcing variables vip and
vin to be zero for the maximum time possible since, when these for π ≤ ωt ≤ 5π/3,
signals are zero, some of the transistors do not switch (none √ 
of the modulation signals cross a carrier signal). Regarding van = (va − vc )/2 = 3/2 mSPWM cos(ωt−π/6).
this restriction and relationships (1), (2), and (9), the following
solution is obtained: (15)

max(va , vb , vc ) − min(va , vb , vc ) Fig. 4 shows the waveforms for this example. The amplitude
vx = − . (11)
2 of the modulation signals mSPWM , which is also√ defined as the
modulation index, is adopted to be mSPWM = 2/ 3 = 1.1547.
The new modulation signals would be The modified modulation signals for phase b have the same

shape but with a 2π/3 phase-shift delay, and for phase c, the
vi −min(va ,vb ,vc )
vip = 2
modulation signals have a 2π/3 phase-shift advancement.
vi −max(va ,vb ,vc ) for i = {a, b, c}. (12) Note that the modified modulation signals are within the
vin = 2
range of [−1, 1], which means that the converter would operate
The algorithm can be easily implemented using the scheme under linear modulation. Therefore, this example shows that the
that is shown in Fig. 3. maximum modulation index that is achievable for the linear-
Under the assumption of sinusoidal modulation signals, modulation mode (mSPWM = 1.1547) can be achieved by this
such that method. This maximum value is also obtained by SVM or by
other carrier-based PWM strategies that make use of a proper

v = m
a SPWM cos ωt zero-sequence signal. However, the method that is proposed
vb = mSPWM cos(ωt − 2π/3) (13) here has the important advantage of maintaining equal voltages
vc = mSPWM cos(ωt + 2π/3) on the dc-link capacitors (disregarding switching ripples).
POU et al.: MODULATION STRATEGY FOR NPC CONVERTER WITH ELIMINATION OF VOLTAGE OSCILLATION 2291

they do not preserve any interval that is clamped to zero. As a

consequence, the switching frequencies of the devices increase.
Furthermore, the sign of the power flux in the system needs
to be known in order to provide a proper shift to the signals.
The balancing strategy that is proposed in this paper avoids
increasing the switching frequencies of the devices. Moreover,
it does not need to detect the direction of the power flux in the
system. This technique is explained here.
Regarding vap and van in Fig. 4(b), none of the signals
are clamped to zero throughout the intervals π/3 ≤ ωt ≤ 2π/3
and 4π/3 ≤ ωt ≤ 5π/3. Therefore, the modified modulation
signals of phase a can be shifted up or down during these
intervals without increasing the switching frequencies of the
devices. Similarly, there are other intervals for phases b and c in
which none of the associated modulation signals are clamped
to zero and, therefore, can be shifted. Although this strategy
preserves the switching frequency of the devices when the
compensator is activated, a significant drawback is the slow
voltage-balancing dynamics of the system. This occurs because
only the modified modulation signals that are associated to one
phase are shifted at any time. In order to improve the balancing
dynamics, the sign of the output currents should be sensed.
Furthermore, (2) must be preserved in order to avoid distortion
in the output voltages during the compensation. This occurs if
the offset that is applied to the modified modulations signals
have opposite signs. The offset that is applied to vip is

vi_off = kp |∆vC | · sign(∆vC ii ) · sign(vip −vin −1). (16)

The absolute value of the voltage imbalance is multiplied

by constant kp . The term sign(∆vC · ii ) defines a sign for the
compensation. Nevertheless, the final sign of the offset depends
+1
on sign(vip − vin − 1) or sign(vip − vin ), in accordance with
the two possible cases that are shown in Fig. 2.

IV. C ONTROL S IGNALS FOR THE T RANSISTORS

The output level that is activated at each phase of the con-
Fig. 4. Example for sinusoidal modulation signals: (a) original signals and verter is defined by a comparison of the modified modulation
(b) modified signal for phase a. signals with the carriers as follows:
p 
III. C OMPENSATION FOR I MBALANCES If vip > vcarrier , then xip = 1; otherwise, xip = 0
n
If vin < vcarrier , then xin = 1; otherwise, xin = 0
Using the proposed modulation technique, the locally aver-
aged NP current is kept to zero, and consequently, the locally xi = xip − xin , i ∈ {a, b, c} . (17)
averaged voltages on the dc-link capacitors are constant. How-
ever, this does not imply that these voltages are equal. In fact, These variables can take three values, i.e., xi ∈ {−1, 0, 1},
in theory, if the initial voltages on the capacitors were different, which are the possible output levels for each phase. In order
this modulation strategy would tend to preserve imbalance to obtain the control functions of the transistors, the following
because the locally averaged NP current is zero. In practice, relationships are needed:
the situation is even worse since dead times, different values 
si4 = 1, if xi =1
and behaviors of the components, etc., can make the voltages 

si3 = 1, if xi = 1 or xi = 0
drift slowly and without control. Thus, some compensation for (18)
voltage imbalances must be provided.  si2
 = 1, if xi = 0 or xi = −1
si1 = 1, if xi = −1.
A control method for voltage compensation can be simply
shifting the modified modulation signals in accordance to the If the preceding respective conditions are not met, then vari-
sign of the voltage error (∆vC = vC1 − vC2 ). An inconve- ables si1 , si2 , si3 , and si4 are correspondingly zero. These vari-
nience of this method is that when the signals are shifted, ables are associated to the ON and OFF states of the transistors
2292 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Fig. 6. Dynamics of the voltage compensator operating over a linear load.

Fig. 5. Experimental results (a) for standard SPWM and (b) for the proposed
modulation strategy.

Fig. 7. Dynamics of the voltage compensator operating over a nonlinear load

(on = 1 and off = 0), where two of them are always ON for (simulation results).
each of the valid 27 electrical states of this converter.
ulation technique is applied. In this case, the voltages on the
dc-link capacitors do not contain any low-frequency oscillation
V. E XPERIMENTAL R ESULTS
but only high-frequency ripples that are related to the switching
The proposed modulation technique has been verified by frequency. Note, however, that the switching frequencies of the
simulation and experiment. The values of the dc-link voltage devices increase compared to the former case since there are
and the capacitors are Vdc = 120 V and C = 1100 µF, re- intervals in which the line-to-line voltages commutate among
spectively. The converter operates over an R–L wye-connected three states of the converter, instead of two. This is produced
load, with L = 12 mH and R = 10 Ω. The frequency of the when neither of the two corresponding modified modulation
carriers is 5 kHz in all the results, and the modulation index is signals is clamped to zero.
mSPWM = 0.8 for Fig. 5 and mSPWM = 0.9 for Fig. 6. The balancing process is shown in Fig. 6, in which the initial
Fig. 5(a) shows the results that are obtained from the applica- voltages on the dc-link capacitors are unbalanced. Observe that
tion of a standard SPWM. The variables shown are a line-to-line the voltages become equal very quickly.
output voltage vab , the voltages on the dc-link capacitors vC1 Fig. 7 shows a simulation example in which a set of sec-
and vC2 , and the output currents ia , ib , and ic . Note that there ond and fourth current harmonics has been added to the load
are significant low-frequency voltage oscillations on the dc-link currents. These harmonics are very harmful for the standard
capacitors. The modulation frequency has been selected to be SPWM strategy since they may introduce instability to the NP
very low in this example (f = 20 Hz) in order to emphasize this voltage, which is also a problem when operating under standard
effect. Fig. 5(b) shows the same results when the proposed mod- SVM techniques [13]. However, when the proposed modulation
POU et al.: MODULATION STRATEGY FOR NPC CONVERTER WITH ELIMINATION OF VOLTAGE OSCILLATION 2293

strategy is applied, the voltages on the dc-link capacitors do not hensive neutral-point balancing in the three-level NPC inverter,” IEEE
show any negative effect, and the system is always stable. Power Electron. Lett., vol. 2, no. 1, pp. 11–15, Mar. 2004.
[11] C. Newton and M. Sumner, “Neutral point control for multi-level
inverters: Theory, design and operational limitations,” in Proc. IEEE IAS
Annu. Meeting, Jul. 1997, vol. 2, pp. 1336–1343.
VI. C ONCLUSION [12] J. Pou, P. Rodríguez, J. Zaragoza, V. Sala, C. Jaén, and
D. Boroyevich, “Enhancement of carrier-based modulation strategies for
The modulation technique that is proposed in this paper multilevel converters,” in Proc. IEEE PESC, Recife, Brazil, Jun. 12–16,
2005, pp. 2534–2539.
completely removes the low-frequency voltage oscillations that [13] J. Pou, R. Pindado, D. Boroyevich, and P. Rodríguez, “Effects of
appear in the NP of the three-level inverter for some operating imbalances and nonlinear loads on the voltage balance of a neutral-
conditions. This technique is also able to attain the maximum point-clamped inverter,” IEEE Trans. Power Electron., vol. 20, no. 1,
pp. 123–131, Jan. 2005.
amplitudes that are achievable under linear modulation, and its
algorithm is very simple and can therefore be quickly processed
in real time. Furthermore, unbalanced and nonlinear loads no
longer produce additional low-frequency voltage oscillations or
Josep Pou (S’97–M’03) received the B.S., M.S.,
instability to the NP. The only drawback of this strategy is that and Ph.D. degrees in electrical engineering from the
the switching frequencies of the devices are one third higher Technical University of Catalonia (UPC), Terrassa,
than those of a standard SPWM for any modulation index Spain, in 1989, 1996, and 2002, respectively.
In 1989, he was the Technical Director of
under linear-operation mode. The method that is proposed for Polylux S.A. In 1990, he joined the faculty of UPC
voltage compensation performs very well. It is able to preserve as an Assistant Professor and became an Associate
constant switching frequencies on the devices and introduces Professor in 1993. From February 2001 to January
2002 and from February 2005 to January 2006, he
no distortion in the output voltages. was a Researcher in the Center for Power Elec-
This strategy will help extend the use of the NPC converter tronics Systems, Virginia Polytechnic Institute and
to lower power applications. One reason for this is that the State University, Blacksburg. He is currently a member of the Power Quality
and Renewable Energy (QuPER) Research Group, Department of Electronic
modulation algorithm can be straightforwardly implemented Engineering, UPC. He has authored more than 50 published technical papers
in a very simple microprocessor. Furthermore, since there is and has been involved in several industrial projects and educational programs
no longer low-frequency voltage oscillation in the NP, the in the fields of power electronics and systems. His research interests include
modeling and control of power converters, multilevel converters, power quality,
values of the dc-link capacitors can be significantly reduced. renewable energy systems, and motor drives.
An interesting application could be the use of MOSFETs for Dr. Pou is a member of the IEEE Power Electronics, IEEE Industry Electron-
the synthesis of the NPC converter operating at about 600 V in ics, and IEEE Industrial Applications Societies.
the dc bus. Since the NP voltage never oscillates, the devices
would only have to support half of the dc-link voltage.
Jordi Zaragoza received the B.S. degree in elec-
R EFERENCES tronic engineering and the M.S. degree in automatic
and electronic industrial engineering from the Tech-
[1] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped nical University of Catalonia (UPC), Terrassa, Spain,
PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523, in 2001 and 2004, respectively. He is currently work-
Sep./Oct. 1981. ing toward the Ph.D. degree in the Department of
[2] H. L. Liu, N. S. Choi, and G. H. Cho, “DSP based space vector PWM Electronic Engineering, UPC.
for three-level inverter with DC-link voltage balancing,” in Proc. IEEE In 2003, he joined the faculty of UPC as an Assis-
IECON, Oct. 28–Nov. 1, 1991, vol. 1, pp. 197–203. tant Professor. From June to September 2006, he was
[3] N. Celanovic and D. Boroyevich, “A comprehensive study of neutral-point a Researcher in the Energy Unit, Robotiker–Tecnalia
voltage balancing problem in three-level neutral-point-clamped voltage Technologic Corporation, Zamudio, Spain. He is
source PWM inverters,” IEEE Trans. Power Electron., vol. 15, no. 2, currently a member of the Power Quality and Renewable Energy (QuPER)
pp. 242–249, Mar. 2000. Research Group, Department of Electronic Engineering, UPC. He has authored
[4] S.-K. Lim, J.-H. Kim, and K. Nam, “A DC-link voltage balancing algo- more than ten published technical paper. His research interests include mod-
rithm for 3-level converter using the zero sequence current,” in Proc. IEEE eling and control of power converters, multilevel converters, wind energy, and
PESC, Jun. 27–Jul. 1, 1999, vol. 2, pp. 1083–1088. power quality.
[5] R. M. Tallam, R. Naik, and T. A. Nondahl, “A carrier-based PWM scheme
for neutral-point voltage balancing in three-level inverters,” in Proc. IEEE
APEC, Feb. 22–26, 2004, vol. 3, pp. 1675–1681.
[6] A. Bendre, G. Venkataramanan, D. Rosene, and V. Srinivasan, “Modeling
and design of a neutral-point voltage regulator for a three-level diode- Pedro Rodríguez (S’99–M’04) received the B.S.
clamped inverter using multiple-carrier modulation,” IEEE Trans. Ind. degree in electrical engineering from the University
Electron., vol. 53, no. 3, pp. 718–726, Jun. 2006. of Granada, Granada, Spain, in 1989, and the M.S.
[7] J. Pou, D. Boroyevich, and R. Pindado, “New feedforward space-vector and Ph.D. degrees in electrical engineering from the
PWM method to obtain balanced AC output voltages in a three-level Technical University of Catalonia (UPC), Terrassa,
neutral-point-clamped converter,” IEEE Trans. Ind. Electron., vol. 49, Spain, in 1994 and 2004, respectively.
no. 5, pp. 1026–1034, Oct. 2002. In 1990, he joined the faculty of UPC as an Assis-
[8] J. Pou, R. Pindado, D. Boroyevich, and P. Rodríguez, “Limits of the tant Professor and became an Associate Professor in
neutral-point balance in back-to-back-connected three-level converters,” 1993. He was a Researcher in the Center for Power
IEEE Trans. Power Electron., vol. 19, no. 3, pp. 722–731, May 2004. Electronics Systems, Virginia Polytechnic Institute
[9] R. C. Portillo, M. A. Martín Prats, J. I. León, J. A. Sánchez, J. M. Carrasco, and State University, Blacksburg, in 2005 and in the
E. Galván, and L. Garcia Franquelo, “Modeling strategy for back-to-back Institute of Energy Technology, Aalborg University, Aalborg, Denmark, in
three-level converters applied to high-power wind turbines,” IEEE Trans. 2006. He is currently a member of the Power Quality and Renewable Energy
Ind. Electron., vol. 53, no. 5, pp. 1483–1491, Oct. 2006. (QuPER) Research Group, Department of Electronic Engineering, UPC. His
[10] S. Busquets-Monge, J. Bordonau, D. Boroyevich, and S. Somavilla, “The research interests include power conditioning, integration of distributed-energy
nearest three virtual space vector PWM—A modulation for the compre- systems, and control of power converters.
2294 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Salvador Ceballos was born in Santander, Spain, in Rolando P. Burgos (S’96–M’03) received the B.S.,
1978. He received the B.S. degree in physics from Electronics Engineering, M.S., and Ph.D. degrees
the University of Cantabria, Santander, in 2001, and from the University of Concepción, Concepción,
the B. Eng. degree in electronic engineering from Chile, in 1994, 1997, 1999, and 2002, respectively.
the University of the Basque Country, Bilbao, Spain, In 2002, he joined the Center for Power Electron-
in 2002. He is currently working toward the Ph.D. ics Systems, Department of Electrical and Computer
degree in the Faculty of Engineering, Department of Engineering, Virginia Polytechnic Institute and State
Electronics and Telecommunications, University of University, Blacksburg, as a Postdoctoral Fellow
the Basque Country. and became a Research Scientist in 2003 and a
Since 2002, he has been with the Robotiker– Research Assistant Professor in 2005. His research
Tecnalia Research Centre, Zamudio, Spain, where he interests include modeling, control, and synthesis of
is currently a Development Engineer in the Energy Unit. His research interests power electronics conversion systems for more electric aircraft and marine
include multilevel converters and fault-tolerant power electronics topologies. applications.

Dushan Boroyevich (S’81–M’86–SM’03–F’06)

received the Dipl.Ing. degree from the University
of Belgrade, Belgrade, Serbia, in 1976, the M.S.
Vicenç M. Sala received the B.S. and M.S. degrees degree from the University of Novi Sad, Novi Sad,
in electronic engineering from the Technical Univer- Serbia, in 1982, and the Ph.D. degree from Virginia
sity of Catalonia (UPC), Terrassa, Spain, in 2001 and Polytechnic Institute and State University (Virginia
2007, respectively. Tech), Blacksburg, in 1986.
In 2000, he was the responsible for the Department From 1986 to 1990, he was an Assistant Professor
of Electronic Engineering, Twistechnology SL. In and the Director of the Power and Industrial Elec-
2001, he joined the faculty of UPC as an Assistant tronics Research Program, Institute for Power and
Professor. He is currently a member of the Power Electronic Engineering, University of Novi Sad, and
Quality and Renewable Energy (QuPER) Research was later the Acting Head of the Institute. He then joined the Department of
Group, Department of Electronic Engineering, UPC. Electrical and Computer Engineering, Virginia Tech, as an Associate Professor,
He has authored more than ten technical papers. He and is currently the American Electric Power Professor in the department and a
is the holder of one patent. His research interests include modeling and control Codirector of the Center for Power Electronics Systems. His research interests
of power converters, multilevel converters, power quality, renewable energy include multiphase power conversion, power electronics systems modeling and
systems, motor drives, and class-D audio power amplifiers. control, and multidisciplinary design optimization.