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8086 Pin Description

The document provides a detailed description of the pin signals for the 8086 microprocessor in both maximum and minimum modes. It outlines the function of each pin, including clock, power supply, reset, address/data bus, and various control signals. Additionally, it explains the differences in signal usage between minimum and maximum modes, including how the processor interacts with memory and I/O operations.

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12 views3 pages

8086 Pin Description

The document provides a detailed description of the pin signals for the 8086 microprocessor in both maximum and minimum modes. It outlines the function of each pin, including clock, power supply, reset, address/data bus, and various control signals. Additionally, it explains the differences in signal usage between minimum and maximum modes, including how the processor interacts with memory and I/O operations.

Uploaded by

cryptomineunit01
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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8086 Pin Description.

Signal Description for Maximum and Minimum mode.


1. CLK(19): The 8086 requires a clock, signal from an external controlled Clock
Generator to synchronise its internal operations. The maximum clock frequency
ranges from 5-10 Mhz. This clock provides the basic timing for the processor and
Bus Controller. It is asymmetric with a 33% duty cycle to provide optimized internal
timing.
2. Vcc (40): +5 V power supply pin.
3. GND (1,20): GROUND.
4. RESET (21): RESET causes the processor to immediately terminate its present
activity. The signal must be active HIGH for atleast four clock cycles. When asserted
HIGH, 8086 resets DS, SS, ES, IP, CS and FLAG register. It then sets CS to FFFFH.
When RESET returns LOW, 8086 fetches its next instruction from physical address
FFFFØH.
5. ADO-AD15 (2-16,39) ADDR/DATA BUS : 8086 has a 20 bit address bus AO-A19
and a 16 bit Data bus. The lower 16 address lines ADO - AD15 are multiplexed with
Data bus. A_{0} is analogous to BHE for the lower order byte of the data bus pins D7
- DO \overline{BHE} is discussed in point No.7) It is low in the T_{1}state when a byte
is to be transferred on the lower portion of the Bus in Memory or I/O operations.
6. A_{19}/S_{6}, A_{18}/S_{5} A_{17}/S_{4} A_{16}/S_{3} (35-38) Address/Status :
The upper 4 bits of Address are sent on these lines for Memory operation. During I/O
operations, these lines are low. During Memory and I/O operations, status
information is available on these lines in T_{2} T3, T_{W} and T_{4} states. Status of
Interrupt flag is indicated by S_{5}.
7. BHE/S7, (34) BUS HIGH ENABLE/STATUS: During T₁ state, the BHE signal is
used, to enable data on the Most Significant half of the Data Bus pins D_{15} - D_{8}.
The S, Status information is available during T_{2}, T_{3}and T_{4} states.
8. RD (32) READ: RD is an active low signal. Read strobe indicates that the processor
is performing a memory or I/O read cycle, depending on S₂ pin.
9. READY (22): When asserted HIGH, 8086 carries out its normal operations. When
LOW, 8086 freezes its buses and enters a wait state.
10. INTR (18) INTERRUPT REQUEST: This is an active HIGH level triggered signal
sampled during the last clock cycle of each instruction. A signal on this input causes
8086 to interrupt the program it is executing and execute the specified Interrupt
Service Procedure. It can be internally masked by software resetting of Interrupt
Enable bit.
11. TEST (23): This input is examined by 8086 'wait' instruction. If the TEST input is
LOW, execution continues otherwise the processor waits in an "idle" state.
12. NMI (17) NON-MASKABLE INTERRUPT: An edge triggered signal on this pin
causes 8086 to COME interrupt the program it is executing and execute Interrupt
Service Procedure corresponding to Type 2 Interrupt. NMI is not maskable internally
by software. A transition from LOW to HIGH initiates the interrupt at the end of
current instruction.
13. MN/ MX (33) MINIMUM/MAXIMUM : This signal indicates the mode of the 8086
processor operates in. When MN/MX = HIGH, 8086 operates in MINIMUM MODE.
Here, the pins will have functions as shown in parantnesis. Minimum, mode is a
system where 8086 is the only processor in the system BUS. When MN/MX = LOW,
8086 operates in MAXIMUM MODE. Here, the pins

Signal Description for Minimum Pin Mode.


14. M/ IO (28) STATUS line: This signal is used to distinguish between a Memory
access and 1/0 access.
15. WR (29) WRITE: This signal indicates that the processor is performing a Memory
Write or an I/O Write cycle depending on the state of M/IO signal.
16. INTA (24) INTERRUPT ACKNOWLEDGE : It is used as an active-low interrupt
acknowledge signal. It is used as a read strobe for Interrupt Acknowledge Cycle.
17. ALE (25) ADDRESS LATCH ENABLE: ALE asserted HIGH by 8086 indicates
ADDR/DATA and ADDR/STATUS bus. It is used to latch the 20 bit address into
8282/8283 address latch. This is a HIGH pulse active during 9 state of any bus cycle.
18. DT/ R (27) DATA TRANSMIT/RECEIVE: This signal is used to control the direction of
data flow through transceivers 8286/8287.
○ When HIGH, the transcievers will transmit data from 8086 to RAMS or ports.
○ When LOW, the buffers if enabled by DEN will allow data to be received from
MEMORY/PORTS to 8086. 8086.
19. DEN (26) DATA ENABLE: This signal provides an output enable signal for
transceivers 8286/8287.
● This is active low signal, to indicate availability of valid data over AD_{0}-AD_{25}
Used to enable trans- receivers (bi-directional buffers) 8286 or 74LS245 to separate
data from multiplexed address/data signal.
20. HOLD, HLDA (31, 30): HOLD is an active HIGH signal indicating that another master
is requesting a local bus. request will issue HOLD ACKNOWLEDGE HLDA HIGH as
○ The processor after receiving an HOLD an acknowledgement in the middle of T_{1}
clock cycle. Simultaneously the processor floats the local bus and control lines.
○ When HOLD goes LOW, the processor lowers HLDA.

Signal Description of Pin for Maximum Mode:


21. S 2, S 1, S 1 (26 - 28) STATUS LINES: These status lines are used by-8288 Bus
controller to generate all Memory and I/O access control signals. These signals are
encoded as below.

22. RQ 0 , ¿ 0 , RQ 1,¿ 1 (30, 31) REQUEST/GRANT : These are bidirectional pins used by
other local bus masters to force the processor to release the local bus at the end of
processors current bus cycle. If the request is made while the CPU is performing a
Memory Cycle, it will release the local bus, provided, following conditions are met :
(a) Request occurs on or before T2.
(b) Current cycle is not the low byte of a word (or an odd address).
(C) Current cycle is not the first acknowledge of an Interrupt Acknowledge sequence.
(d) A locked instruction is not currently executing.
23. LOCK (29): This is an active low signal which indicates that other system bus
masters are not to gain control of the system bus while LOCK is active LOW.
LOCK is activated by LOCK prefix instruction and remains active until the completion of the
next instruction.
24. QS1, QSO (24, 25) QUEUE STATUS: QS1, QSO provide the Queue Status in order
to provide external tracking of internal 8086 Instruction Queue.

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