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The document outlines the design and testing of a flip-flop circuit using a master-slave configuration, including schematic design, symbol creation, and testbench setup for validation. It details the measurement of setup and hold times, as well as the estimation of minimum clock period and maximum clock frequency through simulation. The process includes specific steps for signal configuration, failure detection, and critical path analysis to ensure proper functionality of the circuit.

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ibadsalman86
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3 views6 pages

Work Plan

The document outlines the design and testing of a flip-flop circuit using a master-slave configuration, including schematic design, symbol creation, and testbench setup for validation. It details the measurement of setup and hold times, as well as the estimation of minimum clock period and maximum clock frequency through simulation. The process includes specific steps for signal configuration, failure detection, and critical path analysis to ensure proper functionality of the circuit.

Uploaded by

ibadsalman86
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Q.

Schematic and Symbol Design (Part 1)

Steps:

1. Master-Slave Configuration:
Master Latch:
 Use a transmission gate (NMOS: W/L = 90/50 nm, PMOS:
W/L = 180/50 nm) for input D.
 Add two cross-coupled inverters (sized as per specs) to
hold the state when CLK is high.

Slave Latch:
 Use identical transmission gates and inverters as the
master.
 Connect to the master’s output.
 Activate when CLK is low (inverted CLK signal).

2. CLK Inversion:
 Insert an inverter between the master and slave latches to
generate CLK' (inverted CLK).
 Ensure the inverter is sized correctly (NMOS: 90/50 nm, PMOS:
180/50 nm).

3. Symbol Creation:
Draw a rectangular symbol with:
 Inputs: D, CLK (with a falling-edge indicator ►▾).
 Outputs: Q, Q' (complementary).

Deliverable:

 Schematic diagram with labeled transistors and connections.


 Flip-flop symbol highlighting edge-triggering (falling edge).

2. Testbench Setup and Validation (Part 2)


1. Testbench Components:
CLK Source:
 Pulse generator with:
 Period = 5ns, rise/fall time = 1ps, duty cycle = 50%.

CLK' Generation:
Invert CLK using a sized inverter (same as latch inverters).

D Input:
 Set transitions:
 0 → 1 at 2ns (during CLK high phase).
 1 → 0 at 7ns (during CLK high phase).

2. Simulation Setup:
 Use a transient analysis with:
 Stop time = 10ns (to cover two D transitions).
 Step size = 1ps (as specified).

3. Expected Behavior:
Q updates on CLK falling edges (2.5ns, 7.5ns):
 At 2.5ns: Q should capture D=1 (set at 2ns).
 At 7.5ns: Q should capture D=0 (set at 7ns).

Stability Check: Q remains unchanged between clock edges.

Deliverable:

 Waveform plot showing:


o CLK and CLK' (5ns period, sharp edges).
o D transitions at 2ns and 7ns.
o Q updating after CLK falling edges (delayed by one cycle).

Verification Checklist

1. Transistor Sizing:
o Confirm NMOS/PMOS widths and lengths in inverters and
transmission gates.
2. Edge-Triggering:
 Ensure Q changes only on CLK falling edges.
3. Timing:
o D transitions occur during CLK high phases (setup time
compliance).

Q.2

Part 1-Measuring Setup Time

Objective: Determine the minimum time data (D) must stabilize before the
clock (CLK) rising edge.
Steps:

1. Simulation Setup:
o Implement the flip-flop circuit with two latches and three
inverters as described.
o Connect CLK and D as inputs; monitor outputs QM (master latch)
and Q (slave latch).
2. Signal Configuration:
o Set CLK to a periodic signal (e.g., 50% duty cycle).
o Set D to transition (0→1 or 1→0) at time t_x, and CLK to rise
at t_t.
o Define ΔT = t_t - t_x. Start with a large positive ΔT (e.g., D
transitions far before CLK edge).
3. Sweep ΔT:
o Decrease ΔT incrementally (move D transition closer to CLK
edge) while keeping CLK fixed.
o For each ΔT, simulate and check if Q captures the correct D
value after CLK edge.
4. Failure Detection:
o Identify the smallest ΔT where Q still functions correctly. This
ΔT is the setup time.

Part-2. Measuring Hold Time

Objective: Determine the minimum time data (D) must remain stable after
the CLK rising edge.
Steps:

1. Signal Configuration:
o Set ΔT to a large negative value (e.g., D transitions long after
CLK edge).
o Define ΔT = t_t - t_x (negative since t_x > t_t).
2. Sweep ΔT:
o Increase ΔT incrementally (move D transition closer to CLK edge
from the "after" side).
o For each ΔT, simulate and verify , Q maintains the correct value.
3. Failure Detection:
o Identify the smallest |ΔT| where Q starts to fail. This |ΔT| is
the hold time

Q.3

1. Estimate Minimum Clock Period (T)

Objective: Determine T>Tdk=0+TCLmax (ignoring skew).


Steps:

1. Circuit Setup:
 Implement the schematic with three flip-flops (FFs) and the
NAND gate.
 Connect FF1’s Q to NAND input A, FF2’s Q to NAND input B,
and NAND output to FF3’s D.
 Ensure all FFs share the same clock (CK).

2. Measure Tdk=0 (CLK-to-Q delay):


 Apply a clock pulse to FF1 and FF2.
 Measure time from CK rising edge to Q transitions (rising/falling)
using transient simulation.
 Record worst-case delay (max of rising/falling).

3. Measure TCLmax (NAND gate delay):


 Stimulate NAND inputs (A and B) with transitions.
 Measure delay from input change (A/B) to NAND output (O)
settling.
 Test all combinations (0→1, 1→0 for A/B) and record the
maximum delay.
4. Calculate Minimum T:
 Sum Tdk=0 and TCLmax.

2. Find Maximum Clock Frequency (Input B = 1, A Toggling)

Objective: Determine the highest frequency where the system operates


correctly.
Steps:

1. Signal Configuration:
 Fix B = 1 (FF2’s D = 1).
 Toggle A (FF1’s D) between 0→1→0 with a periodic signal.
 Set initial clock period large (e.g., 10 ns).

2. Sweep Clock Period:


 Gradually reduce clock period in simulations.
 Check if FF3’s Q captures the correct NAND output after CK edge.

3. Failure Detection:
 Identify the smallest period where output fails (setup/hold
violation).
 Max Frequency = 1 / Min Valid Period.

3. Repeat for Input A = 1, B Toggling

Objective: Identify the critical path (A vs. B).


Steps:

1. Signal Configuration:
 Fix A = 1 (FF1’s D = 1).
 Toggle B (FF2’s D) between 0→1→0.

2. Sweep Clock Period:


 Follow the same method as in Step 2.

3. Critical Path Analysis:


 Compare max frequencies from Step 2 and Step 3.
 The path with lower max frequency (longer delay) is critical.
 Explanation: Differences arise from NAND gate asymmetry
(e.g., PMOS/NMOS stacking, input capacitance).

4. Determine Overall Max Frequency

1. Compare Results:
o Take the lower max frequency from Steps 2 and 3 as the
system limit.
2. Validate Against Formula:
o Ensure the clock period T=1/fmax satisfies T>Tdk=0+TCLmax

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