ECE/CS 3724 - Microprocessors

Everything relating to the class is posted on: http://www.ece.msstate.edu/~reese/EE3724 Most of the course lecture notes are linked to WWW page -- print them out before class and bring them to lecture Be sure to read the class Policy/Syllabus, and follow the link to the EE 3724 LAB page Lots of material in this class - dont fall behind!

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Approaches to Digital System Design

In Digital Devices, you learned how to create a logic network (Flip-flops + combinational gates) to solve a problem
The logic network was SPECIFIC to the problem. To solve a different problem, needed a different logic network

Another approach is to design a logic network that can used to solve many different problems
This general purpose logic network might not be as efficient (speed, cost) as a special purpose logic network, but hopefully can be used to solve multiple problems!
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A Computer!!
A Computer is a digital system whose operation can be specified via a Program .
Changing the program changes the computer behavior! (solves a different problem!!!).

A Program is simply a sequence of binary codes that represent instructions for the computer. The Program is stored in a Memory . External inputs to the Computer can also alter the behavior the computer. The computer will have Outputs that can be set/reset via program instructions.
These external inputs/output are know as the I/O section of the computer. 6/00 BR
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Components of any Computer System

Control logic that controls fetching/execution of instructions Memory area where instructions/data are stored Input/Output external interaction with computer
C o n t r o l Address bus Databus bus Memory

Input/Output devices
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Problem Definition
Build a Digital System based upon your Social Security number (SSN). The Digital System will have one external input called ODD. If ODD is true, then the system will reset to display the LEFTMOST odd digit in your SSN, and then the output will sequence over the odd digits in your SSN, skipping over the even digits. If ODD is false, then the system will reset to display the LEFTMOST even digit in your SSN, and then the output will sequence over the even digits in your SSN, skipping over the odd digits.

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Two Approaches for Solving this Problem

Finite State Machine Will only work for one SSN sequence
Inputs n
Combinational Logic Circuit

Output s

k-bit Present State Value k

Memory Element

k-bit Next State Value k

Computer System Will only work for any SSN sequence, change program to change sequence

C o n t r o l

Address bus Memory Databus bus

Input/Output devices
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ASM chart for 458 70 2198

0 Dout = 4 Dout = 8 Dout = 0 Dout = 2 Dout = 8 S4 S5 S6 S7 odd? 1 Dout = 5

S0

Dout = 7 Dout = 1 Dout = 9

S1 S2 S3

Odd only affects sequence in State S0 (Reset state)

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FSM Implementation
Use 3 D-FFs for the 8 states. Use Binary State Encoding: S0=000, S1=001, S2=010, etc S7 = 111 Odd
Combinational Logic Circuit 3-bit Present State Value 3
Dffs

Ssn[3:0]

Outputs

3 Q R D

3-bit Next State Value Clk

Logic designed for a particular SSN sequence.

Alcr
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Computer System Implementation What do We Need? Input/Output First

ssn[3:0]

Odd

ssn[3:0] - 4 bit output bus that has the value of the ssn digit odd 1 bit input that controls whether or not even or odd sequence is displayed BR 6/00

Register for holding SSN output value

DIN 4 ld R E G

ssn[3:0]

Odd

aclr

Register loads DIN on rising clock edge when ld = 1. Aclr is an asynchronous clear.
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Memory for holding instructions

DIN 4 ld aclr R E G

ssn[3:0]

Odd
Address[?:0] M E M Data[?:0]

Memory is KxN (K locations, each location N bits wide). Dont know values of K, N yet.
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Register for specifying address Use counter

Din[3:0] 4

ssn[3:0]
R E G

Odd
Din[?:0] ? ld en aclr c n t r

ld aclr

Addr[?:0]

M E M

Data[?:0]

Counter increments on rising clock edge when en = 1. Loads on rising clock edge when ld = 1. Aclr is an asynchronous clear.
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What Instructions do we need?

Start: If (Odd = 1) goto Odd_start Even_start: output even digit #1 output even digit #2 output last even digit goto Start Odd_start: output odd digit #1 output odd digit #2 .. output last odd digit goto Start
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Psuedo Code for operations

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Needed Instructions
1. Jc location Jump conditionally If odd = 1, then jump to location (counter set equal to specified location). If odd = 0, then fetch next instruction (counter increments by 1). 2. Jmp location Jump unconditional Fetch next instruction from location (counter loaded with specified location). out data load output register with data. Used for setting the ssn[3:0] value.

3.

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Instruction Encoding
The binary encoding for instructions is usually divided into different fields; with each field representing part of the information needed by the instruction. Our instructions require two fields: Operation Code and Data Opcode | Data How many bits for the Opcode? Have 3 instructions, need at least 2 bits! (2 bits can encode 22 items) How many bits for Data? The data field must specify the 4 bits for the SSN number, and also specify a memory location. For now, lets use 4 bits for data. Instruction is 6 bits total. I5 I4 I3 I2 I1 I0 Opcode | Data
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Instruction Table
I5 I4 JMP location JC location OUT data 00 01 10 | | | I3 I2 I1 I0 4-bit location 4-bit location 4-bit data

Note that Opcode = 11 is unused. Also, the opcode assignments were arbitrary; we could have easily chosen some other assigment (such as OUT=00, JC=00, JMP=01)
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A Program for SID = 458 70 2198

JC odd_start OUT 4 OUT 8 OUT 0 OUT 2 OUT 8 JMP Start Odd_start: OUT 5 OUT 7 OUT 1 OUT 9 JMP Start
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Start:

; jmp only if odd input=1

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Convert Program to Binary, Put in Memory

Mem Location 00 01 02 03 04 05 06 07 08 09 0A 0B Mem Contents 01 0111 10 0100 10 1000 10 0000 10 0010 10 1000 00 0000 10 0101 10 0111 10 0001 10 1001 00 0000 Instruction Start: JC Odd_start (loc 7) OUT 4 OUT 8 OUT 0 OUT 2 OUT 8 JMP Start (loc 0) Odd_start: OUT 5 OUT 7 OUT 1 OUT 9 JMP Start (loc 0)

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Add Decode Logic to Execute Instructions

Data[3:0] odd r_ld D E C O D E c_ld c_en Op[1:0] Data[3:0] 4 ld aclr R E G

ssn[3:0] 4

4 ld en aclr

c n t r

Addr[3:0]

M E M

Data[5:0]

Data[5:4]

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What is Decode Logic?

Decode logic controls count register, out register based on Op code value (op[1:0] = Data[5:4]). When does out register get loaded? instruction): VHDL: When OP = 10!! (OUT

r_ld <= 1 when ( op = 10) else 0; When does Counter Load? When JMP instruction (OP=00) or when JC instruction and Odd = 1!!!! c_ld <= 1 when ( op=00 or (op = 01 and odd=1)) else 0; When does counter increment? When NOT Loading!! c_en <= not (c_ld);
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Decode Boolean Equations

r_ld <= op(1) -- dont really need op(0)

c_ld <= ( (not op(1)) and (not op(0)) or ( (not op(1)) and op(0) and odd)); c_en <= not (c_ld);

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Timing
CLK Aclr Abus Dbus r_ld c_ld odd SSN 0 4 8
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0
010111

1
100100

2
101000

3
100000

4
100010

5
101000

6
000000

0
010111

7
100101

8
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Timing (cont.)
CLK Aclr Abus Dbus r_ld c_ld odd SSN 2 8 5
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5
101000

6
000000

0
010111

7
100101

8
100111

9
100001

A
101001

B
000000

0
010111

9
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Comments
Notice that the aclr line forces the processor to fetch its first instruction from location 0.
All processors have a RESET line like this to force the first instruction fetch from a particular location.

Notice that execution never stops!!! Processor is always fetching, executing instructions! Called the Fetch,Execute loop. Must make sure that memory is loaded with valid instructions BEFORE execution starts!!!

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Instruction Pointer
The counter in this processor is a special purpose register that exists in one form or another in every processor Usually is called the Instruction Pointer (IP) register or Program Counter (PC) register. This register contains the address of the next instruction to be fetched.
Normal operation is to fetch very next instruction in memory Jump instructions change the IP value so that fetch occurs from some non-sequential memory location

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Implementation Comparisons
FSM Implementation
Only 3 D-FFs + combinational logic Will only do one SSN sequence Will operate a faster clock rate than Processor implementation because of simpler logic

Processor Implementation
Many more gates needed than FSM implementation Will execute at a slower clock rate than FSM General purpose: can implement any SSN sequence by simply changing program.

MANY applications are better suited for implementation by general purpose digital systems (Processors) than by dedicated logic
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Vocabulary
Address bus input bus to memory device specifying location of data to read/write Data bus input/output bus to memory device containing data value being read or written. Instruction Pointer special register in a processor specifying address of next instruction to be executed. Instruction Mnemonic the ascii representation of an instruction (I.e., OUT 4). Machine Code the binary representation of an instruction (I.e OUT 4 = 010100)
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Vocabulary (cont.)
Operation code (Op code) the part of the machine code for an instruction that tells what the instruction is ( JMP = 00). Assembly the process of converting instructions to their machine code representation OUT 4 10 0100 Disassembly the process of converting machine code to its instruction mnemoic 10 0100 OUT 4 Fetch/Execute - what processors do all day long (fetch instruction from memory, execute it).
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How are Commercial Processors different from SSN Processor?

SSN processor had 4-bit registers. Com. processors have registers with widths from 8 bits to 128 bits wide. SSN processor has 2 registers. Com. proc have many registers, some general purpose, some special purpose. SSN processor has 3 instructions. Com. Proc have 10s to a few hundred instructions (arithmetic, logical, control, Input/output, data movement,etc). SSN processor could address 16 memory locations. Com. Proc can address billions of memory locations. SSN processor can be implemented in a few 10s of gates. Com. Processors can take millions of gates to implement.

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What do you need to know?

Differences between specific logic networks and general purpose logic networks for digital systems. Basics of a computer system Logic Structure, timing of our SSN sequence processor Instruction assembly,disassembly, execution of SSN sequence processor Vocabulary

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