Range 40.

5-42 42/60

C
Mark
s

10/10.5

2 Which of the following is true of the supervisor mode (multiple may be correct):
☑ All instructions can be executed
☐ Only a subset of physical memory is accessible 1.5
☑ It is possible to switch out of the supervisor mode from within the mode
☑ Certain interrupts can turn on the supervisor mode
0.5 marks for each option if it is correctly checked or unchecked
1 Consider a 2-way set associative cache of size 128 bytes. Each block contains 4 bytes. Based on this:
Write down the TIO breakdown for the cache: _26 / 4 / 2_______ 1
1 Which of the following is empirically observed? Choose only 1:
☐ Miss rate decreases with block size
☐ Miss rate increases with block size 1
☐ Miss rate is low for very small or very large block size
☑ Miss rate is low for intermediate block size

2.5 Indicate whether the following signals given to a 32-bit register file with 64 registers, are input, output or
invalid signals (put an I or O or X in the space provided):
A. dataW (32 bit):_I__
B. regA (6 bit): _I__ 2.5
C. Clk (1 bit) _I__
D. regW (5 bit): _X_
E. dataA (32 bit): _O_
0.5 marks each

2 Which of the following issues are solved by segmentation?

☑ Protection - disallow access of memory belonging to a different process
☐ Fragmentation of RAM
☑ Multiprogramming 2
☐ Limited code space
0.5 marks for each option if it is correctly checked or unchecked

1
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8 2 marks for
each row if all
are correct. Cut
0.5 marks per
mistake in the
row.

6.5

2 Which of the following is true of a bootloader (multiple may be correct):

☐ It resides on the hard disk
☑ It copies programs from secondary memory to the RAM
☐ It copies programs from ROM to RAM 2
☑ It resides in the ROM
0.5 marks for each option if it is correctly checked or unchecked
3 Consider the order of instructions shown below. Indicate the instructions for which a data hazard exists in
absence of forwarding by circling the operand which is causing the hazard. If forwarding can solve the
hazard, indicate with an arrow where forwarding can work.

lw t1, 0 (t0)
lw t2, 4 (t0) 3
add t3, t1*, t2
lw t4, 8 (t0)
sw t3, 12 (t0)
add t5, t1, t4*
sw t5, 16 (t0)

1 Which of the following is empirically observed? Choose only 1:

☑ Miss rate decreases with associativity
☐ Miss rate increases with associativity
0
☐ Miss rate is low for very small or very large associativity
☐ Miss rate is low for intermediate associativity

2
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2 0.5 marks per
option

2 The minimum Hamming distance between valid code words for two bit EDCs is:
☐5 ☐4 ☑3 ☐2 Doubtful
The minimum Hamming distance between valid code words for two bit ECCs is: 0
☑5 ☐4 ☐3 ☐2
3 What is a better approach for reading mouse data: interrupt or polling? We will try to answer this based on
different considerations below:

Let us assume the following numbers: For smooth experience, let us assume that the mouse samples data
at 30 Hz, and the CPU should not miss too many samples.
Polling overhead: 400 cycles. Interrupt overhead: 500 cycles.

A. What is the minimum polling rate required to not miss any samples? Circle the correct answer.
☑ 60 Hz ☐ 100 Hz ☐ 30 Hz ☐ 20 Hz 0
B. Let us assume we poll at 50 Hz.How many cycles per second are used for reading mouse data with
(polling, interrupts)?
☐ (20k, 25k) ☑ (20k, 15k) ☐ (12k, 15k) ☐ (12k, 25k)

C. With polling, the overhead of 400 cycles comes due to context switching. The running program has to be
stopped and context saved, so that the polling routine can be run. However, the OS anyway does periodic
context switches when it is running multiple programs. If it performs the polling in that break, it saves on the
context-switch cycles. With this scheme, what should the polling overhead be so that polling becomes
preferable over interrupts for reading mouse data?
☐ 100 cycles ☐ 200 cycles ☑ 300 cycles ☐ 500 cycles

It turns out that without the context switch cost, polling is more efficient than interrupts. Therefore your mice
are always read via polling and not interrupts!

3
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4 1 mark for each
row if all are
Request for Mem to be 1/0 correct. Cut 0.5
marks per
mistake in bold
text.

8 Assume we have the following setup:

16 KiB pages, 64-bit virtual address space and 32-bit physical address space. A program uses 2 MiB of
memory. For simplicity, assume that our page tables only contain the VPN to PPN mapping, and no other
information such as permissions, dirty bit etc.
4
A. How many virtual and physical pages does a program have available?
__10^15 virtual and 4x10^9 physical__ (1 mark) Request for power of 2

B. How much space (number of pages) will a linear page table occupy in the physical memory?
__25x10^10__ (1 mark)

You will notice that the page table for a single process is bigger than the size of physical memory!

C. How many offset bits do we have? ___14______ (1 mark)

Let us assume we have a hierarchical page table now, with two levels. Each section of the L2 page table
should fit into a page.

D. How many bits of address do we use for finding the page within L2?
____12_________ (1 mark)

E. How many L2 sections do we have? ___2^38_____ (1 mark)

F. How many pages does the L1 table occupy? ___64x10^6__________ (1 mark)

G. In the best case, how many pages need to be loaded for the program to run? ___125____ (1 mark)

H. What is the total number of pages used for paging related data with a 2-level hierarchy?
__64x10^6+1_______ (1 mark)

As you can see, this is a much more reasonable, though still large chunk of the memory! A 3-level page
table would cut down the memory usage even further!

4
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5 A. Find the RISC-V single cycle datapath in the paper. On this datapath, trace out the entire flow of
information through the datapath for the load instruction. (2 marks)

B. Assume RAM access takes 100 ns, ALU and other computation 100 ps, reg file read / write 50 ps, all
multiplexers take 25 ps and imm generator takes 10 ps. What is the fastest processor frequency for your
datapath? You can make up to 5% approximations. Justify your answer in at most 5 words.
Max freq: _5 MHz_ Justification: _Load instruction is the critical path_____ (1+1 mark)

C. Now you use caches, and memory access takes 125 ps. What is the fastest frequency the CPU can run 4
at without errors?
_2 GHz________ (1 mark)

2.5 Name the 5 stages of a standard 5-stage pipeline.

Fetch . 2.5
Decode .
Execute .
Memory access.
Write back .
2 Consider a hard disk with the following specifications:
Rotation speed: 7200 revolutions / s Incorrect Given
1500 tracks with 6 ms to move across all tracks 1.5
1000 MB/s transfer rate
Controller overhead: 1 ms

What is the best case time taken by the disk to transfer 1 MB data? ___8 ms_____________

Give a one word answer: why can the time taken be larger than the minimum time? _fragmentation__

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2 For each cache attribute below, write whether it most likely belongs to an L1$ or L2$:

A. Low hit time ____L1________

B. Large cache size ____L2________ 1.5
C. Larger blocks ____L2________
D. Low associativity ____L1________

3 0.5 marks per

column

2 Give full marks

if 2 out of 3
rows are fully
correct.