Lpvlsi Unit I
Lpvlsi Unit I
1.1 Introduction
Design for low power has become nowadays one of the major concerns for
complex, very-large-scale-integration (VLSI) circuits. Deep submicron
technology, from 130 nm onwards, poses a new set of design problems
related to the power consumption of the chip. Tens of millions of gates are
nowadays being implemented on a relatively small die, leading to a power
density and total power dissipation that are at the limits of what packaging,
cooling, and other infrastructure can sup-port. As technology has shrunk to
90 nm and below, the leakage current has increased dramatically, and in
some 65-nm designs, leakage power is nearly as large as dynamic power.
So it is becoming impossible to increase the clock speed of high-
performance chips as technology shrinks and the chip density increases,
because the peak power consumption of these chips is already at the limit
and cannot be increased further. Also, the power density leads to reliability
problems because the mean time to failure decreases with temperature.
Besides, the timing degrades and the leakage currents increase with
temperature. For battery-powered devices also, this high on-chip power
density has become a significant problem, and techniques are being used in
these devices from software to architecture to implementation level to
alleviate this problem as much as possible like power gating and multi-
threshold libraries. Some other techniques being used nowadays are using
different supply voltages at different blocks of the design according to the
performance requirements, or voltage scaling techniques.
Later in the year 1975, Moore revisited that his 10-year-old forecast of
65,000 components was on the mark. However, he revised his prediction
rate from 1 year to 18 months, that is, the component density would double
every 18 months. This became known as Moore’s law.
Dynamic power is the power consumed when the device is active, that is,
when the signals of the design are changing values. It is generally
categorized into three types: switching power, short-circuit power, and
glitching power, each of which will be discussed in details below.
Energy/transition = 12 × C L ×Vdd 2
where CL is the load capacitance and Vdd is the supply voltage. Switching
power is therefore expressed as:
C
switch = Ptrans × CL ,
then, we can also describe the dynamic power with the more familiar
expression:
= C × V
P
switch eff dd 2 × fclock .
Switching power is not a function of transistor size, but it is dependent on
switching activity and load capacitance. Thus, it is data dependent.
Short-Circuit Power
In addition to the switching power, short-circuit power also contributes to
the dynamic power. Figure 1.10 illustrates short-circuit currents. Short-
circuit currents occur when both the negative metal–oxide–semiconductor
(NMOS) and positive metal–oxide–semiconductor (PMOS) transistors are
on. Let Vtn be the threshold voltage of the NMOS transistor and Vtp is the
threshold voltage of the PMOS transistor. Then, in the period when the
voltage value is between Vtn and Vdd–Vtp, while the input is switching either
from 1 to 0 or vice versa, both the PMOS and the NMOS transistors
remain ON, and the short-circuit current follows from Vdd to ground
(GND).
where tsc is the rise/fall time duration of the short-circuit current, Ipeak is the
total in-ternal switching current (short-circuit current plus the current to
charge the internal capacitance), μ is the mobility of the charge carrier,
εoxis the permittivity of the silicon dioxide, W is the width, L is the length,
and D is the thickness of the silicon dioxide.
The third type of dynamic power dissipation is the glitching power which
arises due to finite delay of the gates. Since the dynamic power is directly
proportional to the number of output transitions of a logic gate, glitching
can be a significant source of signal activity and deserves mention here.
Glitches often occur when paths with unequal propagation delays converge
at the same point in the circuit. Glitches oc-cur because the input signals to
a particular logic block arrive at different times, causing a number of
intermediate transitions to occur before the output of the logic block
stabilizes. These additional transitions result in power dissipation, which is
categorized as the glitching power.
Static power dissipation takes place as long as the device is powered on,
even when there are no signal changes. Normally in CMOS circuits, in the
steady state, there is no direct path from Vdd to GND and so there should be
no static power dissipation, but there are various leakage current
mechanisms which are responsible for static power dissipation. Since the
MOS transistors are not perfect switches, there will be leakage currents
and substrate injection currents, which will give rise to static pow-er
dissipation in CMOS. Since the substrate current reaches its maximum for
gate voltages near 0.4Vdd and gate voltages are only transiently in this
range when the devices switch, the actual power contribution of substrate
currents is negligible as compared to other sources of power dissipation.
Leakage currents are also normally negligible, in the order of nano-amps,
compared to dynamic power dissipation. But with deep submicron
technologies, the leakage currents are increasing drastically to the extent
that in 90-nm technology and thereby leakage power also has become
comparable to dynamic power dissipation.
Figure 1.11 shows several leakage mechanisms that are responsible for
static power dissipation. Here, I1 is the reverse-bias p–n junction diode
leakage current, I2 is the reverse-biased p–n junction current due to
tunneling of electrons from the valence band of the p region to the
conduction band of the n region, I3 is the subthreshold leakage current
between the source and the drain when the gate volt-age is less than the
threshold voltage ( Vth), I4 is the oxide tunneling current due to reduction in
the oxide thickness, I5 is the gate current due to hot carrier injection of
electrons (I4 and I5 are commonly known as IGATE leakage current), I6 is
the gate-induced drain leakage current due to high field effect in the drain
junction, and I7 is the channel punch through current due to close
proximity of the drain and the source in short-channel devices.
Apart from scaling the supply voltage to reduce dynamic power, another
alter-native approach is to minimize the switched capacitance comprising
the intrinsic capacitances and switching activity. Choosing which functions
to implement in hardware and which in software is a major engineering
challenge that involves is-sues such as cost complexity, performance, and
power consumption. From the be-havioral description, it is necessary to
perform hardware/software partitioning in a judicious manner such that the
area, cost, performance, and power requirements are satisfied. Transmeta’s
Crusoe processor is an interesting example that demonstrated that
processors of high performance with remarkably low power consumption
can be implemented as hardware–software hybrids. The approach is
fundamentally software based, which replaces complex hardware with
software, thereby achieving large power savings.
MOS Transistors
Introduction:-
The region between the two diffusion islands under the oxide layer is
called the channel region. The operation of an MOS transistor is based on
the controlled flow of current between the source and drain through the
channel region. Based on the channel current to flow and control it, There
are two possible ways to achieve this, which have resulted in
enhancement- and depletion-mode transistors. After fabrication, the
structure of an enhancement-mode nMOS transistor looks like Fig. 3.2a. In
this case, there is no conducting path in the channel region for the situation
Vgs = 0 V, that is when no voltage is applied to the gate with respect to the
source. If the gate is connected to a suitable positive voltage with respect
to the source, then the electric field established between the gate and the
substrate gives rise to a charge inversion region in the substrate under the
gate insulation, and a conducting path is formed be-tween the source and
drain. Current can flow between the source and drain through this
conducting path.
To start with, we may assume that the same voltage is applied to both
the source and drain terminals ( Vdb = Vsb) with respect to the substrate. This
defines the poten-tial of these two regions. In the potential plot, the
diffusion regions (where there is plentiful of charge carriers) can be
represented by very deep wells, which are filled with charge carriers up to
the levels of the potentials of the source and drain regions. The potential
underneath the MOS gate electrode determines whether the two wells are
connected or separated. The potential in the channel region can be
controlled with the help of the gate voltage. The potential at the channel
region is shown by the dotted lines of Fig. 3.5b. The dotted line 1
corresponding to Vgb = 0 is above the drain and source potentials. As the
gate voltage is gradually increased, more and more holes are repelled from
the channel region, and the potential at the channel region moves
downward as shown by the dotted lines 2, 3, etc. In this situation, the
source and drain wells are effectively isolated from each other, and no
charge can move from one well to the other. A point is reached when the
potential level at the gate region is the same as that of the source and
diffusion regions. At this point, the channel region is completely devoid of
holes. The gate voltage at which this happens is called the threshold
voltage ( Vt) of the MOS transistor. If the gate voltage is increased further,
there is an accumulation of electrons beneath the SiO2 layer in the channel
region, forming an inversion layer. As the gate voltage is increased further,
the potential at the gate region moves below the source and drain potentials
as shown by the dotted lines 3 and 4 in Fig. 3.5b. As a consequence, the
barrier between the two regions disappears and the charge from the source
and drain regions spills underneath the gate electrode leading to a uniform
surface potential in the entire region. By varying the gate voltage, the
thickness of the inversion layer can be controlled, which in turn will
control the conductivity of the channel as visualized in Fig. 3.5b. Under
the control of the gate voltage, the region under it acts as a movable barrier
that controls the flow of charge between the source and drain areas.
The fluid model, presented in the previous section, gives us some basic
understanding of the operation of an MOS transistor. We have seen that
the whole concept of the MOS transistor is based on the use of the gate
voltage to induce charge (inversion layer) in the channel region between
the source and the drain. Application of the source-to-drain voltage Vds
causes this charge to flow through the channel from the source to drain
resulting in source-to-drain current Ids. The Ids depends on two variable
parameters—the gate-to-source voltage Vgs and the drain-to-source voltage
Vds. The operation of an MOS transistor can be divided into the following
three regions:
(a) Cutoff region: This is essentially the accumulation mode, when there is
no effective flow of current between the source and drain.
Threshold Voltage
The expression holds good for both n-channel and p-channel devices.
•The substrate bias voltage Vsb is positive in nMOS and negative in pMOS.
where q is the charge of electron, εox is the dielectric constant of the silicon
sub-strate, NA is the doping concentration densities of the substrate (1016
cm−3), and Cox is the oxide capacitance, Ni is the carrier concentration of
the intrinsic silicon (1.45 ×1010 cm−3).
Transistor Trans-conductance gm
The figure of merit W0 gives us an idea about the frequency response of the
device
A fast circuit requires gm as high as possible and a small value of Cg. From
Eq. 3.23, it can be concluded that higher gate voltage and higher electron
mobility provide better frequency response.
Body Effect
Channel-Length Modulation
The transmission gate is one of the basic building blocks of MOS circuits.
It finds use in realizing multiplexors, logic circuits, latch elements, and
analog switches.
Case I: Large Capacitive Load First, consider the case when the input
has changed quickly to Vdd from 0 V and the output of the switch changes
slowly from 0 V ( Vss) to Vdd to charge a load capacitance CL. This can be
modeled by using Vdd as an input and a ramp voltage generated at the
output as the capacitor charges from Vss to Vdd. Based on the output
voltage, the operations of the two transistors can be divided into the
following three regions:
Region I: As the voltage difference between the input and output is large,
both nMOS and pMOS transistors are in saturation.
Region II: nMOS is in saturation and pMOS in linear for Vtp < Vout < Vdd
−Vtn .
Region III: nMOS is in cutoff and pMOS in linear for Vout > Vdd −Vtn .
Similarly, when the input voltage changes quickly from Vdd to 0 V and the
load capacitance discharges through the switch.
Region I: Both nMOS and pMOS are in saturation for Vout < Vtp .
Region II: nMOS is in the linear region, and pMOS is in saturation for
(Vdd − Vtp ) < Vout < Vtn .
Region III: nMOS is in the linear region, and pMOS is cutoff for Vout <
(Vdd − Vtn ).
Case II: Small Capacitive Load Another situation is the operation of the
trans-mission gate when the output is lightly loaded (smaller load
capacitance). In this case, the output closely follows the input. This is
represented in Fig. 3.18a.
In this case, the transistors operate in three regions depending on the input
voltage as follows:
Region I: nMOS is in the linear region, pMOS is cutoff for Vin < Vtp .
Region II: nMOS is in the linear region, pMOS linear for Vtp < Vin < (Vdd
− Vtn ).