Proceedings of the Fourth International Conference on Ubiquitous Computing and Intelligent Information Systems (ICUIS-2024)

IEEE Xplore Part Number: CFP24UG3-ART; ISBN: 979-8-3315-2963-5

Implementation of 8-bit SPI Protocol using

System Verilog and UVM
2024 4th International Conference on Ubiquitous Computing and Intelligent Information Systems (ICUIS) | 979-8-3315-2963-5/24/$31.00 ©2024 IEEE | DOI: 10.1109/ICUIS64676.2024.10867233

M. Saravanan1, R. Sandhiya2, S. Sivaranjani3,

Department of ECE, Department of ECE, Department of ECE,
Sri Eshwar College of Engineering, Sri Eshwar College of Engineering, Sri Eshwar College of Engineering,
Coimbatore, Tamilnadu, India Coimbatore, Tamilnadu, India Coimbatore, Tamilnadu, India
[email protected]. [email protected] [email protected].

K. Tamilarasi4, M.Tamilarasan5, G.M. Varshini6,

Department of ECE, Department of ECE, Department of ECE,
Sri Eshwar College of Engineering, Sri Eshwar College of Engineering, Sri Eshwar College of Engineering
Coimbatore, Tamilnadu, India Coimbatore, Tamilnadu, India Coimbatore, Tamilnadu, India
[email protected] [email protected] [email protected]

Abstract: Currently, the design and verification of peripheral devices [1 – 3]. Data exchange in SPI occurs
efficient communication protocols are essential in between a master device and one or more slave devices.
embedded systems. This paper focuses on the When data is transmitted by a device, incoming data must be
development and verification of an 8-bit Serial read before the next transmission can occur, ensuring that
Peripheral Interface (SPI) protocol using System Verilog data exchange is continuous and synchronized [4]. In SPI,
and Universal Verification Methodology (UVM). SPI, a each device must be capable of both transmitting and
popular protocol in embedded communication, enables receiving data. The master device governs the clock line
high-speed, synchronous, full-duplex data transfer (SCK), controlling data exchange between devices through
this clock line. Serial Peripheral Interface (SPI) is a
between a master and one or more slave devices. By
commonly used critical communication protocol in a variety
utilizing SystemVerilog for hardware modeling and
of embedded systems. It also enables high-speed
UVM for a modular, reusable testbench framework, this synchronous data transfer between devices. The main
approach enhances the verification process's efficiency objective is to enable efficient, dependable communication,
and accuracy. Various operational scenarios for the SPI especially in systems where pin count is critical. This study
protocol are tested, ensuring robust performance in focuses on developing an 8-bit SPI protocol with System
communication systems. Verilog, a strong hardware description and verification
language In scenarios such as processor-to-processor and
Keywords- SPI Protocol, SystemVerilog, Universal processor-to-peripheral communication, data integrity and
Verification Methodology (UVM), VLSI Design, speed are critical.
Embedded Systems, Communication Protocols, Modular
Testbench The methodology for
implementing and verifying the SPI protocol is based on
two key approaches: System Verilog for coding the protocol
I. INTRODUCTION and Universal Verification Methodology (UVM) for
System-on-chip designs typically include a wide verification. System Verilog allows for precise hardware
range of peripherals, such as analog-to-digital converters modeling of the SPI protocol, and UVM provides a
(ADCs), registers, memory units, and digital-to-analog standardized testbench framework for comprehensive and
converters (DACs). As a result, efficient data transmission systematic verification of the communication system. Using
and reception between these connected peripherals are these protocols guarantees that the design is robust and
essential for SoC functionality. The Serial Peripheral performs properly in a variety of scenarios. UVM also offers
Interface (SPI) is one of the most widely used serial a verification environment that is reusable and scalable
protocols for both inter-chip and intra-chip low-to-medium which results in improving verification efficiency and
speed data transfers. SPI facilitates communication between simplifies the testing procedure. Nonetheless, the SPI
processors and devices like external EEPROMs, DACs, protocol's lack of a flow control mechanism and addressing
ADCs, and similar components. In the landscape of scheme restricts its use in increasingly complex systems. In
communication protocols, SPI is often referred to as a addition, the slave devices have to obey the master's
"small" protocol. It's crucial to recognize the unique role of
commands to the letter, and in multi-slave deployments, it
each protocol; for instance, Ethernet, USB, and SATA are
designed for "outside-the-box communications," supporting can be challenging to manage several devices due to the
data exchange between entire systems. In contrast, SPI is absence of a formal addressing structure [5 – 7]. While
specifically designed for interconnecting integrated circuits System Verilog offers a versatile and powerful solution to
for low-to-medium speed data transfer on-board with implementing the 8-bit SPI protocol, UVM verification

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 Proceedings of the Fourth International Conference on Ubiquitous Computing and Intelligent Information Systems (ICUIS-2024)
IEEE Xplore Part Number: CFP24UG3-ART; ISBN: 979-8-3315-2963-5

allows for scalability and reuse. Method 1, which is direct slave is not selected, the MISO line is held in a high-
implementation with System Verilog, has the advantage of impedance state. Master Out Slave In (MOSI): Through the
having more control over hardware modeling, but it may MOSI line, the master transmits data to the slave in a serial,
lack systematic testing. Method 2, which uses UVM, one-way direction, also starting with the MSB. In SPI, the
addresses this issue by providing a reusable, modular rising or falling clock edges dictate when data is sent and
verification environment, which necessitates additional received by the master and slave, respectively. SPI
learning and setup time [8]. By comparing various methods, Communication setup where a single SPI Master device is
we hope to demonstrate how combining them can overcome connected to multiple SPI Slave devices (four in this case),
allowing the master to communicate with each slave
limits such as debugging complexity and increase overall
individually over a shared bus. The SPI protocol utilizes four
system verification efficiency [9 -11]. The novelty of the
main signal lines: SCLK (Serial Clock), MOSI (Master Out
project is unlike previous works that primarily focused on Slave In), MISO (Master In Slave Out), and SS (Slave
SystemVerilog and UVM, our paper uniquely integrates Select). The SCLK line, generated by the master, is a clock
both methodologies to deliver a comprehensive and robust signal that coordinates the timing of data transmission
verification framework. between the master and all slaves. This clock signal is shared
among all slave devices to ensure synchronized data transfer.
II. SPI PROTOCOL
The MOSI line is used by the master to send data to the
The Serial Peripheral Interface (SPI) is a widely used slaves, allowing it to transmit information in a serial format.
communication protocol, offering synchronous, full-duplex Each slave listens on this line, but only the selected slave
data transmission at high speeds over short distances— processes the data being sent. Conversely, the MISO line is
typically between devices on the same circuit board. As used by the active slave to send data back to the master,
shown in the figure 1, SPI is commonly employed to enable creating a two-way communication link. To avoid conflicts
communication between microcontrollers or when multiple slaves are connected to the same MISO line,
microprocessors and various peripherals [12]. To ensure only the select slave drives the line, while the others remain
synchronized data transmission and reception, SPI requires a in a high-impedance (tri-state) state, effectively
clock signal. Operating in a master-slave configuration, SPI disconnecting them from the line to prevent data overlap or
supports both single master-single slave and single master- interference. When the master pulls one of these SS lines
multiple slave architectures. Communication between low, it enables the corresponding slave to communicate,
while the other slaves remain inactive. For example, if the
master and slave devices occurs over a synchronous clock
master wants to communicate with the first slave, it pulls
signal generated by the master. Only four signal lines are SS1 low, activating only that slave and keeping others in
needed for communication between master and slave standby mode. This selective activation enables the master to
devices in SPI [14 -15]. communicate with multiple slaves over shared MOSI and
MISO lines without causing data conflicts. Once the slave is
selected, the master initiates data transfer over a series of
clock pulses.
In a typical 16-bit SPI setup, the master
and active slave exchange 16 bits of data in a full-duplex
manner, meaning data is sent on the MOSI line from the
master to the slave while, at the same time, data from the
slave is sent to the master over the MISO line. The SS
(Slave Select) lines play a crucial role in this configuration,
as they allow the master to select and activate a specific
slave for communication. Each slave has its dedicated SS
line, which is controlled directly by the master. When the
master pulls one of these SS lines low, it enables the
corresponding slave to communicate, while the other slaves
remain inactive. For example, if the master wants to
communicate with the first slave, it pulls SS1 low,
activating only that slave and keeping others in standby
mode. Each slave module would also have logic to drive the
Fig. 1. SPI Protocol MISO line with its data output when active. The use of shift
SPI consists of four primary signals: Serial Clock (SCK) registers in both the master and slave modules is a common
This clock signal synchronizes data transmission between the approach to handling serial data transfer, ensuring the
master and slave over the MOSI and MISO lines. An entire correct timing and format for 8-bit data frames.
byte of data is exchanged between master and slave within
eight clock cycles, with SCK generated by the master and III. PROPOSED ARCHITECTURE
serving as the input clock for the slave. Chip Select (CS) / (a) System Verilog Architecture
Slave Select (SS): This line selects the slave device for
communication. It remains active-low during data transfer The System Verilog testbench architecture provides a
[6-8]. Master In Slave Out (MISO): Through the MISO line, structured, modular approach to verifying a Design
the master receives data from the slave. Data is transmitted
Under Test (DUT), as shown in the figure 2. At the
serially, with the most significant bit (MSB) sent first. If the
highest level is the Top Module, which instantiates the

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 Proceedings of the Fourth International Conference on Ubiquitous Computing and Intelligent Information Systems (ICUIS-2024)
IEEE Xplore Part Number: CFP24UG3-ART; ISBN: 979-8-3315-2963-5

DUT and the Environment, setting up the necessary detailed insights into which parts of the DUT have been
connections for simulation. The Environment serves as tested. By setting specific coverage goals, the
a container for essential verification components, verification team can identify any untested scenarios
organizing and grouping them to ensure modularity and and adjust the stimulus to achieve comprehensive
reusability. Within the Environment, the Agent contains coverage, ensuring that every critical path in the DUT is
several critical sub-components, including the exercised. Another powerful aspect of this architecture
Generator, BFM (Bus Functional Model), Monitor, and is the use of Assertions, which are embedded within the
Coverage components. The Generator creates stimulus testbench to check for expected behavior in real time.
or test patterns, which are often randomized or Assertions act as checkpoints during simulation, quickly
constrained to simulate a wide range of operating identifying protocol violations or incorrect behavior by
scenarios and passes these patterns to the BFM. verifying that signals follow specified timing, order, or
Acting as an interface between the testbench state transitions. This immediate feedback accelerates
and the DUT, the BFM converts the high-level debugging and enhances the accuracy of test results.
transactions from the Generator into pin-level signals System Verilog also supports Randomization and
that drive the DUT inputs. Meanwhile, the Monitor Constraints in stimulus generation, enabling the creation
passively observes the communication between the of complex, varied test scenarios that help expose
BFM and the DUT, capturing output data without corner cases that may not be covered by manual test
interfering with the simulation. This data is then sent to patterns. Randomization introduces a degree of
the Scoreboard, which compares it with expected unpredictability in test patterns, while constraints guide
outputs to verify the DUT's functionality, checking for this randomness to ensure valid transactions within the
any mismatches and logging errors. DUT’s expected operating parameters. Additionally,
Virtual Interfaces are used in the testbench to simplify
connections between components and increase
modularity. Virtual interfaces allow different testbench
components to access shared signals dynamically,
making it easier to swap modules or reconfigure the
testbench for different DUT configurations.

(b) UVM Architecture

In IC design, the Universal Verification Methodology

(UVM) is pivotal for establishing a robust verification
framework that confirms a module meets its
specifications. Originating from the Open Verification
Methodology (OVM) and leveraging System Verilog,
UVM emphasizes key features like code reusability,
environment construction, random stimulus generation,
Fig. 2 System Verilog Architecture
and rigorous Design Under Test (DUT) verification to
meet project requirements. At its core, UVM organizes
Additionally, the Coverage component records its classes into three main categories: uvm_object, the
functional coverage data based on the monitored base class for data and operational methods, from which
transactions, tracking how much of the DUT’s essential classes like uvm_component and
functionality has been exercised, which ensures that all uvm_transaction inherit; uvm_transaction, which is
required scenarios have been tested. The architecture central to generating stimuli; and uvm_component, a
also includes Mailboxes (shown as "M" in the diagram) static class throughout simulation that encompasses
that serve as transaction queues, facilitating primary components such as the Top, Agent, Sequence
asynchronous communication between components like Item, Sequence, Test, Environment, Driver, Sequencer,
the Generator, BFM, and Monitor, allowing for efficient Monitor, and Scoreboard.
data transfer and coordination. This modular
architecture, with each component performing a specific
role, enhances testbench flexibility, reusability, and
scalability, making it well-suited for rigorous
verification of complex designs and adaptable for
different DUTs or testing scenarios.
The System Verilog testbench architecture
leverages several advanced features to enhance the
verification process and increase test coverage. One of
these features is Functional Coverage, which provides

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 Proceedings of the Fourth International Conference on Ubiquitous Computing and Intelligent Information Systems (ICUIS-2024)
IEEE Xplore Part Number: CFP24UG3-ART; ISBN: 979-8-3315-2963-5

Modeling (TLM) interfaces abstract data transactions,

decoupling components for modular design and scalability.
Sequences and Virtual Sequences allow for synchronized
stimulus generation across multiple agents, enabling
coordinated, complex scenarios. Phase Jumping provides
control over simulation flow by allowing transitions
between phases based on test requirements. Together, these
features make UVM an industry-standard approach for
creating scalable, reusable, and adaptable verification
environments.
IV. RESULTS AND DISCUSSION

Fig. 3 UVM Architecture

Each UVM component functions through defined
simulation phases that organize and control the verification
process. The Build Phase is responsible for creating and
configuring component hierarchies according to Fig.4. Simulated Waveform of SPI
configuration and factory settings, while the Connect Phase Figure 4 shows the simulated waveform of the serial
links ports among various UVM components. The Run peripheral interface data exchange between the master and
Phase handles runtime simulation tasks, and the Extract slave during the MISO and MOSI modes of operation. This
Phase gathers data from scoreboards and monitors for also shows data transfer and control signals over time,
functional coverage analysis. Following this, the Check where various signals are toggling in response to specific
Phase verifies DUT behavior, identifying errors in the clock cycles, indicating data flow and synchronization.
testbench execution, and the Report Phase displays
simulation results while saving them for analysis. The Final
Phase then signals the end of the simulation, ensuring all
components conclude safely.
As shown in the figure 3, the UVM testbench
architecture consists of several interconnected components:
the Testbench, which instantiates the DUT and test classes
and establishes their connections; the Test, which configures
the testbench and initiates stimulus sequences; and the
Environment, which groups reusable verification
components, such as the scoreboard and agent, into modular
units. Within the Environment, the Agent includes the
Monitor, Driver, and Sequencer, working as a signal entity
through the TLM interface. The Sequencer generates and
manages transactions, directing them to the Driver, while Fig. 5. SPI Master Slave Core
the Driver sends data to the DUT and reference model via
the interface. The Monitor samples data from the DUT, Figure 5 depicts the simulated waveform of the serial
peripheral interface data exchange between the master
recording and comparing transaction data, and the
and slave core. The timing diagram shows transitions and
Scoreboard verifies the DUT’s functionality through
data changes across different signals, illustrating the
embedded checkers.
behavior of the circuit over time.
Additional aspects further enhance UVM's
adaptability and effectiveness. For instance, UVM employs
a Factory Pattern for dynamic object creation and
substitution, allowing flexible testbench configurations
without code modifications. The Configuration Database
centralizes parameter passing across the testbench, ensuring
consistency and simplifying adjustments. Transaction-Level

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 Proceedings of the Fourth International Conference on Ubiquitous Computing and Intelligent Information Systems (ICUIS-2024)
IEEE Xplore Part Number: CFP24UG3-ART; ISBN: 979-8-3315-2963-5

Fig. 6. SPI Slave Waveform

Figure 6 illustrates the slave functioning waveform. The

figure shows the behavior of these slave signals over time
or control sequence.
Fig. 9 UVM Report of SPI’s Data Transaction Between
Master and Slave
Figure 10 gives the successful data transfer between master
and slave and vice-versa. Transaction details like RD_WR
Match, address Match, MISO data Match and MOSI data
Match are shown on successful data exchanged between the
master and slave

Fig. 7. Read Operation of the SPI Master

Figure 7 shows the read operation of the SPI master. The

delay signal demonstrates timing delays for
synchronization during the read process.

Fig. 10 Modes of Operation Simulation

Figure 10 shows the different modes of operation of the SPI
master and slave based on the clock polarity and clock
phase. The four SPI modes (0–3) define the clock polarity
and phase for data sampling and shifting. Modes 0 and 1
Fig. 8. Write Operation of SPI Master have a low idle clock, while modes 2 and 3 have a high idle
clock; modes 0 and 2 sample on the rising edge, and modes
Figure 8 demonstrates the write operation of the SPI
Master. The delay signal indicates the timing intervals 1 and 3 sample on the falling edge.
used for synchronization, ensuring data stability during Table 1 Modes of operation
each transfer.

Table 2 Code Coverage of Master Module

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 Proceedings of the Fourth International Conference on Ubiquitous Computing and Intelligent Information Systems (ICUIS-2024)
IEEE Xplore Part Number: CFP24UG3-ART; ISBN: 979-8-3315-2963-5

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This research study successfully demonstrates the

design and verification of an 8-bit SPI protocol using
SystemVerilog and UVM, providing a scalable and reusable
testbench architecture suitable for modern VLSI designs. By
achieving efficient data exchange between master and slave
devices, validated through comprehensive simulation, this
work highlights the importance of robust communication
protocols in VLSI circuits where high integration and
reliable interconnectivity are crucial. Future work could
explore implementing more complex SPI systems, such as
those supporting higher bit widths and multiple slaves in
larger VLSI systems, or integrating error detection and
correction mechanisms to enhance reliability. Additionally,
multi-master configurations and clock synchronization
across VLSI blocks could be addressed to broaden the
protocol's applications. Expanding the protocol’s usability
for IoT, automotive, and AI-driven applications can further
support the development of versatile VLSI solutions
adaptable to evolving industry demands.

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Peripheral Interface(SPI) Protocol for Low Power Applications”, Vol.
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