Prepared by:

Engr. Cindy D. Dullas

The analysis or design of a transistor amplifier requires a knowledge of both the
dc and the ac response of the system. Too often it is assumed that the transistor
is a magical device that can raise the level of the applied ac input without the
assistance of an external energy source. In actuality, any increase in ac voltage,
current, or power is the result of a transfer of energy from the applied dc
supplies.
The analysis or design of any electronic amplifier therefore has two
components: a dc and an ac portions. Fortunately, the superposition theorem is
applicable, and the investigation of the dc conditions can be totally separated
from the ac response. However, one must keep in mind that during the design or
synthesis stage the choice of parameters for the required dc levels will affect the
ac response, and vice versa.
The dc level of operation of a transistor is controlled by a number of factors,
including the range of possible operating points on the device characteristics.
We specify the range for the bipolar junction transistor (BJT) amplifier. Once the
desired dc current and voltage levels have been defined; a network must be
constructed that will establish the desired operating point. A number of these
networks are analyzed in this chapter. Each design will also determine the
stability of the system, that is, how sensitive the system is to temperature
variations.
 Be able to understand the operating point of
transistor during saturation region, linear
region and cut-off region
 Be able to determine the DC levels for the
variety of important BJT configuration such as
Fixed Bias Configuration, Emitter Bias
Configuration, Voltage Divider Bias
Configuration, Collector-feedback
Configuration, Emitter Follower Configuration
and Common Base Configuration
 Be able to perform a load line analysis of the
most common BJT configuration
 Recap on last Topic
𝑉𝐵𝐸 = 0.7𝑉

𝐼𝐶 = 𝛽𝐼𝐵

𝐼𝐸 = (𝛽 + 1)𝐼𝐵
 Alpha(α) of a transistor is the ratio of the collector
current to the emitter current.

αdc : Typically
extends from 0.90 to
0.998

αac : formally called the

IC common-base, short-circuit,
aac  VCB  constant
amplification factor
IE
 Beta(β) of a transistor is the gain or
amplification factor of a transistor

𝐼𝐶 βdc : Typically ranges from 50 to 400

𝛽𝑑𝑐 =
𝐼𝐵
βdc : h from AC hybrid equivalent and FE from
𝛽𝑑𝑐 = ℎ𝐹𝐸 βdc : h from
forward AC hybrid
current equivalent
amplification andand FE from
common
forward current amplification and common
emitter configuration.
emitter configuration.

𝛽𝑎𝑐 βac : formally called the

Δ𝐼𝐶 common-emitter, forward
= |𝑉𝐶𝐸 = constant current, amplification factor
Δ𝐼𝐵
𝛽𝑎𝑐 = ℎ𝑓𝑒
Using KCL: 𝐼𝐶 𝐼𝐶
𝑎= 𝛽=
𝐼𝐸 𝐼𝐵
𝐼𝐶 + 𝐼𝐵 − 𝐼𝐸 = 0
Using substitution method:
𝐼𝐸 = 𝐼𝐶 + 𝐼𝐵
𝐼𝑐 𝐼𝑐
= 𝐼𝐶 +
𝛼 𝛽
1 1
= 1 + |divideboth sides by IC
𝛼 𝛽
𝑜𝑟: 𝛽 = 𝛼𝛽 + 𝛼 = (𝛽 + 1)𝛼

So that:
𝛽 𝛼
𝑎= 𝛽=
𝛽+1 1−𝛼

For current levels:

𝐼𝐸 = 𝐼𝐶 + 𝐼𝐵 𝐼𝐶 = 𝛽𝐼𝐵
𝐼𝐸 = 𝛽𝐼𝐵 + 𝐼𝐵
𝐼𝐸 = (𝛽 + 1)𝐼𝐵
Various operating points within the limits of operation of a transistor

For the BJT to be biased in its linear or

active operating region the following must
be true:
1. The base–emitter junction must be
forward-biased (p-region voltage more
positive),
with a resulting forward-bias voltage of
about 0.6 V to 0.7 V.
2. The base–collector junction must be
reverse-biased (n-region more positive),
with
the reverse-bias voltage being any value
within the maximum limits of the device.
Various operating points within the limits of operation of a transistor

Operation in the cutoff, saturation,

and linear regions of the BJT
characteristic are provided as
follows:
1. Linear-region operation:
Base–emitter junction forward-biased
Base–collector junction reverse-
biased
2. Cutoff-region operation:
Base–emitter junction reverse-biased
Base–collector junction reverse-
biased
3. Saturation-region operation:
Base–emitter junction forward-biased
Base–collector junction forward-
biased
  The fixed bias is the simplest transistor dc
bias configuration.

DC Equivalent
Fixed Bias Circuit Circuit
Analyze the DC Equivalent Circuit
Forward Biased of Base-Emitter

𝐼𝐶 = 𝛽𝐼𝐵

DC Equivalent
Circuit

Using KVL: +𝑉𝐶𝐶 − 𝐼𝐵𝑅𝐵 − 𝑉𝐵𝐸 = 0

𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵
Analyze the DC Equivalent Circuit
Common-Emitter Loop

DC Equivalent
Circuit

Using KVL: +𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶 − 𝑉𝐶𝐸 = 0

𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶

Analyze the DC Equivalent Circuit
Common-Emitter Loop
Using KVL:
+𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶 − 𝑉𝐶𝐸 = 0
𝐼𝐶 = 𝛽𝐼𝐵
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶

VCE is the voltage from collector to emitter

𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸 VE=0
𝑉𝐶𝐸 = 𝑉𝐶

VBE is the voltage from base to emitter

𝑉𝐵𝐸 = 𝑉𝐵 − 𝑉𝐸
VE=0
𝑉𝐵𝐸 = 𝑉𝐵
 Saturation is any system where levels have
reached their maximum level
 Saturation conditions normally avoided because
the base-collector junction is no longer reverse-
bias and output amplified signal will be distorted
Actual Saturation Region Ideal Saturation Region
 Determining IC sat for the
Determining IC sat Fixed Bias Configuration

𝑉𝑐𝑐
𝐼𝐶𝑠𝑎𝑡 =
𝑅𝑐
 The device characteristics

Fixed bias load line

Fixed bias
+𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶 − 𝑉𝐶𝐸 = 0

𝑉𝐶𝐶 = 𝑉𝐶𝐸 |𝐼𝐶 = 0𝑚𝐴

𝑉𝐶𝐶
𝐼𝐶 = |𝑉𝐶𝐸 = 0𝑉
𝑅𝐶
Movement of Q-point with Effect of an increasing level of RC
increasing level of IB on the load line and the Q-point
Effect of lower values of VCC on the load
line and the Q-point
1. Determine the following for the fixed bias
configuration:
a. IBQ and ICQ a. IBQ and ICQ :
b. VCEQ
𝑉𝐶𝐶 − 𝑉𝐵𝐸 𝐼𝐵𝑄 = 𝐼𝐵
c. VB 𝐼𝐵𝑄 = 𝐼𝐵 =
𝑅𝐵 12𝑉 − 0.7𝑉
=
d. VC 240𝑘Ω
𝐼𝐵𝑄 = 47.083𝜇𝐴
e. VBC

𝐼𝐶𝑄 = 𝐼𝐶 = 𝛽𝐼𝐵 𝐼𝐶𝑄 = 𝐼𝐶 = (50)(47.083𝜇𝐴)

𝐼𝐶𝑄 = 2.354𝑚𝐴

b. VCEQ :
𝑉𝐶𝐸𝑄 = 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶

𝑉𝐶𝐸𝑄 = 12𝑉 − (2.354𝑚𝐴)(2.2𝑘Ω)

𝑉𝐶𝐸𝑄 = 6.821𝑉
1. Determine the following for the fixed bias
configuration:
a. IBQ and ICQ c. VB :
b. VCEQ
𝑉𝐵 = 𝑉𝐵𝐸 = 0.7𝑉
c. VB
d. VC d. VC :
e. VBC
𝑉𝐶 = 𝑉𝐶𝐸 = 6.821𝑉

e. VBC :

𝑉𝐵𝐶 = 𝑉𝐵 − 𝑉𝐶

𝑉𝐵𝐶 = 0.7𝑉 − 6.821𝑉

𝑉𝐵𝐶 = 6.121𝑉
2. Given the load line figure for a fixed bias configuration
below and the defined Q-point, determine the following
a. VCC
b. RC
c. RB
a. VCC :
𝑉𝐶𝐸 = 𝑉𝐶𝐶 = 20𝑉 at IC=0mA

𝑉𝐶𝐶
𝐼𝐶 = =10mA at VCE=0V
𝑅𝐶

b. RC :
𝑅𝐶
𝑉𝐶𝐶
= (Based on graph
𝐼𝐶
IC=10mA)
20𝑉
𝑅𝐶 = = 2𝑘Ω
10𝑚𝐴
2. Given the load line figure for a fixed bias configuration
below and the defined Q-point, determine the following
a. VCC
b. RC
c. RB
c. RC :
𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵

𝑉𝐶𝐶 − 𝑉𝐵𝐸 20𝑉 − 0.7𝑉

𝑅𝐵 = =
𝐼𝐵 25𝜇𝐴
𝑅𝐵 = 772𝑘Ω

IB based on graph
between 20μA and
30μA, hence IB = 25μA
 The emitter bias contains an emitter resistor
to improve the stability level compare to
fixed-bias.
Analyze the DC Equivalent Circuit
Base-Emitter Loop
Using KVL:
+𝑉𝐶𝐶 − 𝐼𝐵𝑅𝐵 − 𝑉𝐵𝐸 − 𝐼𝐸𝑅𝐸 = 0

Substitute IE=(β+1)IB to the equation

and simplify the equation

𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐸 = (𝛽 + 1)𝐼𝐵 𝐼𝐵 =
𝑅𝐵 + (𝛽 + 1)𝑅𝐸
Analyze the DC Equivalent Circuit
Base-Emitter Loop
Reflected impedance level of RE
𝑅𝑖 = (𝛽 + 1)𝑅𝐸
Analyze the DC Equivalent Circuit
Collector-Emitter Loop
Using KVL:
+𝐼𝐸𝑅𝐸 + 𝑉𝐶𝐸 + 𝐼𝐶𝑅𝐶 − 𝑉𝐶𝐶 = 0

IE ≈ IC:
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐵 + 𝑅𝐸)

VE voltage from emitter to ground:

𝑉𝐸 = 𝐼𝐸𝑅𝐸

VC voltage at collector:

𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸 𝑉𝐶 = 𝑉𝐶𝐸 + 𝑉𝐸
𝑜𝑟
𝑉𝐶 = 𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶
Analyze the DC Equivalent Circuit
Collector-Emitter Loop
VB voltage at base:

𝑉𝐵 = 𝑉𝐶𝐶 − 𝐼𝐵𝑅𝐵
𝑜𝑟
𝑉𝐵 = 𝑉𝐵𝐸 + 𝑉𝐸
Determining IC sat for the emitter-stabilized
bias circuit

𝑉𝐶𝐶
𝐼𝐶𝑠𝑎𝑡 =
𝑅𝐶 + 𝑅𝐸
Load line for the emitter-bias configuration

𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐶 + 𝑅𝐸)

𝑉𝐶𝐶 = 𝑉𝐶𝐸 |𝐼𝐶 = 0𝑚𝐴

𝑉𝐶𝐶
𝐼𝐶 = |𝑉𝐶𝐸 = 0𝑉
𝑅𝐶 + 𝑅𝐸
1. For the emitter-bias network below, determine
the following:
a. IB
b. IC
c. VCE
d. VC
e. VE
f. VB
g. VBC

a. IB :
𝑉𝐶𝐶 − 𝑉𝐵𝐸 b. IC :
𝐼𝐵 =
𝑅𝐵 + (𝛽 + 1)𝑅𝐸
𝐼𝐶 = 𝛽𝐼𝐵
20𝑉 − 0.7𝑉
𝐼𝐵 = 𝐼𝐶 = (50)(40.125𝜇𝐴)
430𝑘Ω + (50 + 1)(1𝑘Ω)
𝐼𝐵 = 40.125𝜇𝐴 𝐼𝐶 = 2.006𝑚𝐴
1. For the emitter-bias network below, determine
the following:
a. IB
b. IC
c. VCE
d. VC
e. VE
f. VB
g. VBC

c. VCE : d. VC :
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐶 + 𝑅𝐸) 𝑉𝐶 = 𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶

𝑉𝐶𝐸 = 20𝑉 − [2.006𝑚𝐴(2𝑘Ω + 1𝑘Ω)]

𝑉𝐶 = 20𝑉 − [2.006𝑚𝐴(2𝑘Ω)]
𝑉𝐶𝐸 = 13.982𝑉
𝑉𝐶 = 15.988𝑉
1. For the emitter-bias network below, determine
the following:
a. IB
b. IC
c. VCE
d. VC
e. VE
f. VB
g. VBC

e. VE :
𝑉𝐸 = 𝑉𝐶 − 𝑉𝐶𝐸 or 𝑉𝐸 = 𝐼𝐸𝑅𝐸 ≅ 𝐼𝐶𝑅𝐸

𝑉𝐸 = 15.988𝑉 − 13.982𝑉 𝑉𝐸 = (2.006𝑉)(1𝑘Ω)

𝑉𝐸 = 2.006𝑉 𝑉𝐸 = 2.006𝑉
1. For the emitter-bias network below, determine
the following:
a. IB
b. IC
c. VCE
d. VC
e. VE
f. VB
g. VBC

f. VB : g. VBC :
𝑉𝐵 = 𝑉𝐵𝐸 + 𝑉𝐸 𝑉𝐵𝐶 = 2.706𝑉 − 15.988𝑉

𝑉𝐵 = 0.7𝑉 + 2.006𝑉
𝑉𝐵 = 2.706𝑉 𝑉𝐵𝐶 = 2.706𝑉 − 15.988𝑉
𝑉𝐵𝐶 = −13.282𝑉
 2. Draw the load line for the characteristic of the transistor
below:

IC=5.455mA

VCC=18V

𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐶 + 𝑅𝐸)

𝑉𝐶𝐶 = 𝑉𝐶𝐸 |𝐼𝐶 = 0𝑚𝐴 𝑉𝐶𝐶 = 𝑉𝐶𝐸 = 18𝑉 |𝐼𝐶 = 0𝑚𝐴

𝑉𝐶𝐶 18𝑉
𝐼𝐶 = |𝑉𝐶𝐸 = 0𝑉 𝐼𝐶 = = 5.455𝑚𝐴|𝑉𝐶𝐸 = 0𝑉
𝑅𝐶 + 𝑅𝐶 2.2𝑘Ω + 1.1𝑘Ω
 2.b. Determine the values of ICQ and VCEQ for
the Q-point of the load line with a base
current of 15μA.

IC=5.455mA IC=5.455mA

Q-Point Q-Point
ICQ

VCC=18V
VCC=18V vCEQ VCC=18V
VCC=18V

Based on graph,
Q point approximation:
ICQ ≈ 3.3mA
VCEQ ≈ 7.5V
 The voltage divider comes from the voltage divider
formed by R1 and R2.The voltage drop across R2
forward biases the base-emitter junction.

Defining the Q-point of the voltage

Voltage-divide bias configuration divider bias configuration
Analyze the DC Equivalent Circuit
Exact Analysis

Using Thevenin Theorem

𝑅 = 𝑅 //𝑅
DC Component of
the voltage divider
Analyze the DC Equivalent Circuit
Exact Analysis

Redrawing
the input
side

Applying Voltage Divider rule:

𝑅2𝑉𝐶𝐶
DC Component of 𝐸𝑇𝐻 =
𝑅1 + 𝑅2
the voltage divider
Analyze the DC Equivalent Circuit
Exact Analysis

Redrawing
the input
side

Using KVL:
+𝐸𝑇𝐻 − 𝐼𝐵𝑅𝑇𝐻 − 𝑉𝐵𝐸 − 𝐼𝐸𝑅𝐸 = 0

𝐸𝑇𝐻 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝑇𝐻 + (𝛽 + 1)𝑅𝐸
DC Component of
the voltage divider
Analyze the DC Equivalent Circuit
Exact Analysis

Using KVL:
+𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶 − 𝑉𝐶𝐸 − 𝐼𝐸𝑅𝐸 = 0

I E ≈ I C: 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐶 + 𝑅𝐸)

VE voltage from emitter to ground:

𝑉𝐸 = 𝐼𝐸𝑅𝐸

VC voltage at collector:

𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸
DC Component of
the voltage divider
 The same saturation level same as emitter
bias configuration

𝑉𝐶𝐶
𝐼𝐶𝑠𝑎𝑡 = 𝐼𝐶 max =
𝑅𝐶 + 𝑅𝐸
 Thesame load line as emitter bias
configuration

𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐶 + 𝑅𝐸)

𝑉𝐶𝐶 = 𝑉𝐶𝐸 |𝐼𝐶 = 0𝑚𝐴

𝑉𝐶𝐶
𝐼𝐶 = |𝑉𝐶𝐸 = 0𝑉
𝑅𝐶 + 𝑅𝐶
1. For the voltage divider bias network below,
determine the following:
a. IC
b. VCE

Determine RTH and ETH:

𝑅 = 𝑅 //𝑅

(39𝑘Ω)(3.9𝑘Ω)
𝑅 =
39𝑘Ω + 3.9𝑘Ω
𝑅 = 3.55𝑘Ω
1. For the voltage divider bias network below,
determine the following:
a. IC
b. VCE

𝑅2𝑉𝐶𝐶 (3.9𝑘Ω)(22𝑉)
𝐸𝑇𝐻 = 𝐸𝑇𝐻 =
𝑅1 + 𝑅2 39𝑘Ω + 3.9𝑘Ω
𝐸𝑇𝐻 = 2𝑉
 1. For the voltage divider bias network below,
determine the following:
a. IC
b. VCE

a. IC =? :
𝐸𝑇𝐻 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝑇𝐻 + (𝛽 + 1)𝑅𝐸

𝐼𝐶 = 𝛽𝐼𝐵
2𝑉 − 0.7𝑉
𝐼𝐵 =
3.55𝑘Ω + (100 + 1)1.5𝑘Ω 𝐼𝐶 = (100)(8.38𝜇𝐴)
𝐼𝐵 = 8.38𝜇𝐴 𝐼𝐶 = 0.84𝑚𝐴
 1. For the voltage divider bias network below,
determine the following:
a. IC
b. VCE

b. VCE =? :
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐶 + 𝑅𝐸) 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐶 + 𝑅𝐸)
𝑉𝐶𝐸 = 22𝑉 − (0.84𝑚𝐴)(10𝑘Ω + 1.5𝑘Ω)
𝑉𝐶𝐸 = 12.34𝑉
1. Fixed Bias Configuration
2. Emitter Bias Configuration
3. Voltage Divider Bias Configuration
4. Collector-feedback Configuration
5. Emitter Follower Configuration
6. Common Base Configuration
 The collector feedback ensures that the transistor
is always biased in the active region regardless of
the value of Beta(β).It provides good stability

Collector Feedback bias DC bias circuit wit voltage

configuration feedback
DC Analysis
Base-Emitter Loop

Using KVL:
+𝑉𝐶𝐶 − 𝐼𝐶′𝑅𝐶 − 𝐼𝐵𝑅𝐹 − 𝑉𝐵𝐸 − 𝐼𝐸𝑅𝐸 = 0
+𝑉𝐶𝐶 − 𝛽𝐼𝐵𝑅𝐶 − 𝐼𝐵𝑅𝐹 − 𝑉𝐵𝐸 − 𝛽𝐼𝐵𝑅𝐸 = 0

+𝑉𝐶𝐶 − 𝛽𝐼𝐵(𝑅𝐶 + 𝑅𝐸) − 𝐼𝐵𝑅𝐹 − 𝑉𝐵𝐸 = 0

Using: 𝑰𝑪′ ≅ 𝑰𝑪 = 𝜷𝑰𝑩 𝒂𝒏𝒅 𝑰𝑪 ≅ 𝑰𝑬

𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐹 + 𝛽(𝑅𝐶 + 𝑅𝐸)
DC Analysis
Collector-Emitter Loop

Using KVL:
𝐼𝐸𝑅𝐸 + 𝑉𝐶𝐸 + 𝐼𝐶′𝑅𝐶 − 𝑉𝐶𝐶 = 0
𝐼𝐶(𝑅𝐶 + 𝑅𝐸) + 𝑉𝐶𝐸 − 𝑉𝐶𝐶 = 0

Using: 𝑰𝑪 ≅ 𝑰𝑪 𝒂𝒏𝒅 𝑰𝑪 ≅ 𝑰𝑬

𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐶 + 𝑅𝐸)

 The same saturation level same as emitter
bias configuration and voltage divider
𝐼𝐶′ = 𝐼𝐶

𝑉𝐶𝐶
𝐼𝐶𝑠𝑎𝑡 = 𝐼𝐶 max =
𝑅𝐶 + 𝑅𝐸
 Thesame load line same as emitter bias
configuration and voltage divider

𝐼𝐶′ = 𝐼𝐶
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐶 + 𝑅𝐸)

𝑉𝐶𝐶 = 𝑉𝐶𝐸 |𝐼𝐶 = 0𝑚𝐴

𝑉𝐶𝐶
𝐼𝐶 = |𝑉𝐶𝐸 = 0𝑉
𝑅𝐶 + 𝑅𝐶
1. For the collector feedback bias network
below, determine the following:
a. IC
b. VCE
 The collector follower also known as common
collector configuration. Collector terminal as
common to both input and output signals. The
emitter voltage follows the base voltage

Collector Follower DC equivalent

bias configuration
DC Analysis
Base-Emitter Loop

+𝐼𝐵𝑅𝐵 + 𝑉𝐵𝐸 + 𝐼𝐸𝑅𝐸 − 𝑉𝐸𝐸 = 0

𝑢𝑠𝑒: 𝐼𝐸 = (𝛽 + 1)𝐼𝐵
+𝐼𝐵𝑅𝐵 + [(𝛽 + 1)𝐼𝐵𝑅𝐸] = 𝑉𝐸𝐸 − 𝑉𝐵𝐸

𝑉𝐸𝐸 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵 + (𝛽 + 1)𝑅𝐸
DC Analysis
Collector-Emitter Loop

−𝑉𝐸𝐸 + 𝑉𝐶𝐸 + 𝐼𝐸𝑅𝐸 = 0

𝑉𝐶𝐸 = 𝑉𝐸𝐸 − 𝐼𝐸𝑅𝐸
2. For the emitter follower bias network
below, determine the following:
a. IC
b. VCE
 The base terminal as common to both input and
output signals. In the AC domain, it has a very low
input impedance, high output impedance and good
gain

Common Base configuration DC equivalent

DC Analysis
Base-Emitter Loop

−𝑉𝐸𝐸 + 𝐼𝐸𝑅𝐸 + 𝑉𝐵𝐸 = 0

𝑉𝐸𝐸 − 𝑉𝐵𝐸
𝐼𝐸 =
𝑅𝐸
DC Analysis
Base-Collector Loop
−𝑉𝐸𝐸 + 𝐼𝐸𝑅𝐸 + 𝑉𝐶𝐸 + 𝐼𝐶𝑅𝐶 − 𝑉𝐶𝐶 = 0
𝑉𝐶𝐸 = 𝑉𝐸𝐸 + 𝑉𝐶𝐶 − 𝐼𝐸𝑅𝐸 − 𝐼𝐶𝑅𝐶
Using:𝐼𝐸 ≅ 𝐼𝐶
𝑉𝐶𝐸 = 𝑉𝐸𝐸 + 𝑉𝐶𝐶 − 𝐼𝐸(𝑅𝐸 + 𝑅𝐶)

𝑉𝐶𝐵 + 𝐼𝐶𝑅𝐶 − 𝑉𝐶𝐶 = 0

𝑉𝐶𝐵 = 𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶
Using:𝐼𝐸 ≅ 𝐼𝐶
𝑉𝐶𝐵 = 𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶
3. For the common-base network below,
determine the following:
a. IE and IB
b. VCE and VCB