MEERUT INSTITUTE OF ENGINEERING & TECHNOLOGY

Microprocessor and Microcontroller (KEE 602)

UNIT 2

MAIN FEATURES OF 8085 MICROPROCESSOR

 It is an 8 bit microprocessor.
 It is manufactured with N-MOS technology.
 It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB)
memory locations through A0-A15
 The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7
 Data bus is a group of 8 lines D0 – D7
 It supports external interrupt request. .
 A 16 bit program counters (PC)
 A 16 bit stack pointer (SP)
 Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
 It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
 It is enclosed with 40 pins DIP (Dual in line package).

8085 Microprocessor Architecture

The 8085 microprocessor is an 8-bit processor available as a 40-pin IC package and uses +5 V for
power. It can run at a maximum frequency of 3 MHz. Its data bus width is 8-bit and address bus
width is 16-bit, thus it can address 216 = 64 KB of memory. The internal architecture of 8085 is
shown is Fig. 1.
 Fig 1.
1. Arithmetic and Logic Unit The ALU performs the actual numerical and logical operations such
as Addition (ADD), Subtraction (SUB), AND, OR etc. It uses data from memory and from
Accumulator to perform operations. The results of the arithmetic and logical operations are stored
in the accumulator.
2. Registers The 8085 includes six registers, one accumulator and one flag register, as shown in Fig.
2. In addition, it has two 16-bit registers: stack pointer and program counter. They are briefly
described as follows. The 8085 has six general-purpose registers to store 8-bit data; these are
identified as B, C, D, E, H and L. they can be combined as register pairs - BC, DE and HL to
perform some 16- bit operations. The programmer can use these registers to store or copy data
into the register by using data copy instructions.
 Fig 2.
2.1 Accumulator The accumulator is an 8-bit register that is a part of ALU. This register is used to
store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored
in the accumulator. The accumulator is also identified as register A.
2.2 Flag register The ALU includes five flip-flops, which are set or reset after an operation
according to data condition of the result in the accumulator and other registers. They are called Zero
(Z), Carry (CY), Sign (S), Parity (P) and Auxiliary Carry (AC) flags. Their bit positions in the flag
register are shown in Fig. 3. The microprocessor uses these flags to test data conditions.

Fig 3.
For example, after an addition of two numbers, if the result in the accumulator is larger than 8-bit, the
flip-flop uses to indicate a carry by setting CY flag to 1. When an arithmetic operation results in zero,
Z flag is set to 1. The S flag is just a copy of the bit D7 of the accumulator. A negative number has a
1 in bit D7 and a positive number has a 0 in 2’s complement representation. The AC flag is set to 1,
when a carry result from bit D3 and passes to bit D4. The P flag is set to 1, when the result in
accumulator contains even number of 1s.
2.3 Program Counter (PC) This 16-bit register deals with sequencing the execution of instructions.
This register is a memory pointer. The microprocessor uses this register to sequence the execution of
the instructions. The function of the program counter is to point to the memory address from which
the next byte is to be fetched. When a byte is being fetched, the program counter is automatically
incremented by one to point to the next memory location.
2.4 Stack Pointer (SP) The stack pointer is also a 16-bit register, used as a memory pointer. It points
to a memory location in R/W memory, called stack. The beginning of the stack is defined by loading
16-bit address in the stack pointer.
2.5 Instruction Register/Decoder It is an 8-bit register that temporarily stores the current
instruction of a program. Latest instruction sent here from memory prior to execution. Decoder then
takes instruction and decodes or interprets the instruction. Decoded instruction then passed to next
stage.
3. Control Unit
Generates signals on data bus, address bus and control bus within microprocessor to carry out the
instruction, which has been decoded. Typical buses and their timing are described as follows:
3.1 Data Bus: Data bus carries data in binary form between microprocessor and other external units
such as memory. It is used to transmit data i.e. information, results of arithmetic etc between memory
and the microprocessor. Data bus is bidirectional in nature. The data bus width of 8085
microprocessor is 8-bit i.e. 28 combination of binary digits and are typically identified as D0 – D7.
Thus size of the data bus determines what arithmetic can be done. If only 8-bit wide then largest
number is 11111111 (255 in decimal). Therefore, larger numbers have to be broken down into
chunks of 255. This slows microprocessor.
3.2 Address Bus: The address bus carries addresses and is one way bus from microprocessor to the
memory or other devices. 8085 microprocessor contain 16-bit address bus and are generally
identified as A0 - A15. The higher order address lines (A8 – A15) are unidirectional and the lower
order lines (A0 – A7) are multiplexed (timeshared) with the eight data bits (D0 – D7) and hence, they
are bidirectional.
3.3 Control Bus: Control bus are various lines which have specific functions for coordinating and
controlling microprocessor operations. The control bus carries control signals partly unidirectional
and partly bidirectional. The following control and status signals are used by 8085 processor:
 I. ALE (output): Address Latch Enable is a pulse that is provided when an address appears on the
AD0 – AD7 lines, after which it becomes 0.

MUX/DEMUX unit
 This unit is used to select a register out of all the available registers.
 This unit behaves as a MUX when data is going from the register to the internal data bus.
 It behaves as a DEMUX when data is coming to a register from the internal data bus of the
microprocessor.
 The register select will behave as the function selection lines of the MUX/DEMUX.

Address Buffer Register & Data/Address Buffer Register

 These registers hold the address/data, received from PC/internal data bus and then load the
external address and data buses.
 These registers actually behave as the buffer stage between the microprocessor and external
system buses.

Timing & Control unit

 The control unit generates signals within microprocessor to carry out the instruction, which has
been decoded.
 In reality, it causes certain connections between blocks of the microprocessor to be opened or
closed, so that the data goes where it is required and the ALU operations occur.

8085 PIN DESCRIPTION

3.1 Properties:
 It is a 8-bit microprocessor
 Manufactured with N-MOS technology
 40 pin IC package
 It has 16-bit address bus and thus has 216 = 64 KB addressing capability.
 Operate with 3 MHz single-phase clock
 +5 V single power supply
The logic pin layout and signal groups of the 8085 microprocessor are shown in Fig. 4. All the
signals are classified into six groups:
1. Address bus and Data bus
2. Control & status signals
3. Power supply and frequency signals
 4. Externally initiated signals
5. Serial I/O signals

Fig 4.
1. Address and Data Buses:
 A8 – A15 (output, 3-state): Most significant eight bits of memory addresses and the eight bits of
the I/O addresses. These lines enter into tri-state high impedance state during HOLD and HALT
modes.
 AD0 – AD7 (input/output, 3-state): Lower significant bits of memory addresses and the eight bits
of the I/O addresses during first clock cycle. Behaves as data bus during third and fourth clock
cycle. These lines enter into tri-state high impedance state during HOLD and HALT modes.
2. Control & Status Signals:
 ALE: Address latch enable
 RD : Read control signal.
 WR : Write control signal.
 IO/M, S1 and S0 : Status signals.

3. Power Supply & Clock Frequency:

  Vcc: +5 V power supply
 Vss: Ground reference
 X1, X2: A crystal having frequency of 6 MHz is connected at these two pins
 CLK: Clock output
4. Externally Initiated and Interrupt Signals:
 RESET IN: When the signal on this pin is low, the PC is set to 0, the buses are tri-stated and
the processor isreset.
 RESET OUT: This signal indicates that the processor is being reset. The signal can be used to
reset other devices.
 READY: When this signal is low, the processor waits for an integral number of clock cycles
until it goes high.
 HOLD: This signal indicates that a peripheral like DMA (direct memory access) controller is
requesting the use of address and data bus.
 HLDA: This signal acknowledges the HOLD request.
 INTR: Interrupt request is a general-purpose interrupt.
 INTA : This is used to acknowledge an interrupt.
 RST 7.5, RST 6.5, RST 5,5 – restart interrupt: These are vectored interrupts and have highest
priority than
 INTR- interrupt.
 TRAP: This is a non-maskable interrupt and has the highest priority.
5. Serial I/O Signals:
 SID: Serial input signal. Bit on this line is loaded to D7 bit of register A using RIM
instruction.
 SOD: Serial output signal. Output SOD is set or reset by using SIM instruction.

INSTRUCTION SET
Based on the design of the ALU provides instruction set for every machine code and mnemonics. and
decoding unit, the microprocessor manufacturer microprocessor. The instruction set consists of both
An instruction is a binary pattern designed inside a microprocessor to perform a specific function.
The entire group of instructions that a microprocessor supports is called instruction set.
Microprocessor instructions can be classified based on the parameters such functionality, length and
operand addressing.
Classification based on functionality:
1. Data transfer operations: This group of instructions copies data from source to destination. The
content of the source is not altered.

Opcod Operand Explanation of Description

e Instruction

MOV Rd, Rs Copy from This instruction copies the contents of the source
source(Rs) to register into the destination register; the contents
M, Rs destination(Rd) of the source register are not altered. If one of the
operands is a memory location, its location is
Rd, M specified by the contents of the HL registers.

Example: MOV B, C or MOV B, M

MVI Rd, data Move immediate 8- The 8-bit data is stored in the destination register
bit or memory. If the operand is a memory location, its
M, data location is specified by the contents of the HL
registers.

Example: MVI B, 57H or MVI M, 57H

LDA 16-bit Load accumulator The contents of a memory location, specified by a

address 16-bit address in the operand, are copied to the
accumulator. The contents of the source are not
altered.

Example: LDA 2034H

LDAX B/D Reg. Load accumulator The contents of the designated register pair point to
pair indirect a memory location. This instruction copies the
contents of that memory location into the
accumulator. The contents of either the register
pair or the memory location are not altered.

Example: LDAX B

LXI Reg. Load register pair The instruction loads 16-bit data in the register pair
pair, 16- immediate designated in the operand.
bit data
Example: LXI H, 2034H or LXI H, XYZ

LHLD 16-bit Load H and L The instruction copies the contents of the memory
address registers direct location pointed out by the 16-bit address into
register L and copies the contents of the next
memory location into register H. The contents of
 source memory locations are not altered.

Example: LHLD 2040H

STA 16-bit 16-bit address The contents of the accumulator are copied into the
address memory location specified by the operand. This is a
3-byte instruction, the second byte specifies the
low-order address and the third byte specifies the
high-order address.

Example: STA 4350H

STAX Reg. Store accumulator The contents of the accumulator are copied into the
pair indirect memory location specified by the contents of the
operand (register pair). The contents of the
accumulator are not altered.

Example: STAX B

SHLD 16-bit Store H and L The contents of register L are stored into the
address registers direct memory location specified by the 16-bit address in
the operand and the contents of H register are
stored into the next memory location by
incrementing the operand. The contents of registers
HL are not altered. This is a 3-byte instruction, the
second byte specifies the low-order address and the
third byte specifies the high-order address.

Example: SHLD 2470H

XCHG none Exchange H and L The contents of register H are exchanged with the
with D and E contents of register D, and the contents of register
L are exchanged with the contents of register E.

Example: XCHG

SPHL none Copy H and L The instruction loads the contents of the H and L
registers to the registers into
stack pointer the stack pointer register, the contents of the H
register provide the high-order address and the
contents of the L register provide the low-order
address. The contents of the H
and L registers are not altered.

Example: SPHL

XTHL none Exchange H and L The contents of the L register are exchanged with
with top of stack the stack location pointed out by the contents of
the stack pointer register. The contents of the H
register are exchanged with the next stack location
(SP+1); however, the contents of the stack pointer
 register are not altered.

Example: XTHL

PUSH Reg. Push register pair The contents of the register pair designated in the
pair onto stack operand are copied onto the stack in the following
sequence. The stack pointer register is
decremented and the contents of the highorder
register (B, D, H, A) are copied into that location.
The stack pointer register is decremented again
and the contents of the low-order register (C, E, L,
flags) are copied to that location.

Example: PUSH B or PUSH A

POP Reg. Pop off stack to The contents of the memory location pointed out by
pair register pair the stack pointer register are copied to the low-
order register (C, E, L, status flags) of the operand.
The stack pointer is incremented by 1 and the
contents of that memory location are copied to the
high-order register (B, D, H, A) of the operand. The
stack pointer register is again incremented by 1.

Example: POP H or POP A

OUT 8-bit Output data from The contents of the accumulator are copied into
port accumulator to a the I/O port specified by the operand.
address port with 8-bit
address Example: OUT F8H

IN 8-bit Input data to The contents of the input port designated in the
port accumulator from a operand are read and loaded into the accumulator.
address port with 8-bit
address Example: IN 8CH

2.Arithmetic Instructions

Opcod Operan Explanation Description

e d of
Instruction

ADD R Add The contents of the operand (register or memory)

register or are added to the contents of the accumulator and
M memory, the result is stored in the accumulator. If the
to operand is a memory location, its location is
accumulat specified by the contents of the HL registers. All
 or flags are modified to reflect the result of the
addition.

Example: ADD B or ADD M

ADC R Add The contents of the operand (register or memory)

register to and M the Carry flag are added to the contents of
M accumulat the accumulator and the result is stored in the
or with accumulator. If the operand is a memory location,
carry its location is specified by the contents of the HL
registers. All flags are modified to reflect the result
of the addition.

Example: ADC B or ADC M

ADI 8-bit Add The 8-bit data (operand) is added to the contents of
data immediate the accumulator and the result is stored in the
to accumulator. All flags are modified to reflect the
accumulat result of the addition.
or
Example: ADI 45H

ACI 8-bit Add The 8-bit data (operand) and the Carry flag are
data immediate added to the contents of the accumulator and the
to result is stored in the accumulator. All flags are
accumulat modified to reflect the result of the addition.
or with
carry Example: ACI 45H

LXI Reg. Load The instruction loads 16-bit data in the register pair
pair, register designated in the operand.
16-bit pair
data immediate Example: LXI H, 2034H or LXI H, XYZ

DAD Reg. Add The 16-bit contents of the specified register pair are
pair register added to the contents of the HL register and the
pair to H sum is stored in the HL register. The contents of the
and L source register pair are not altered. If the result is
registers larger than 16 bits, the CY flag is set. No other flags
are affected.

Example: DAD H

SUB R Subtract The contents of the operand (register or memory )

register or are subtracted from the contents of the
M memory accumulator, and the result is stored in the
from accumulator. If the operand is a memory location,
accumulat its location is specified by the contents of the HL
or registers. All flags are modified to reflect the result
of the subtraction.
 Example: SUB B or SUB M

SBB R Subtract The contents of the operand (register or memory )

source and M the Borrow flag are subtracted from the
M and contents of the accumulator and the result is placed
borrow in the accumulator. If the operand is a memory
from location, its location is specified by the contents of
accumulat the HL registers. All flags are modified to reflect the
or result of the subtraction.

Example: SBB B or SBB M

SUI 8-bit Subtract The 8-bit data (operand) is subtracted from the
data immediate contents of the accumulator and the result is stored
from in the accumulator. All flags are modified to reflect
accumulat the result of the subtraction.
or
Example: SUI 45H

SBI 8-bit Subtract The contents of register H are exchanged with the
data immediate contents of register D, and the contents of register
from L are exchanged with the contents of register E.
accumulat
or with Example: XCHG
borrow

INR R Increment The contents of the designated register or memory)

register or are incremented by 1 and the result is stored in the
M memory same place. If the operand is a memory location, its
by 1 location is specified by the contents of the HL
registers.

Example: INR B or INR M

INX R Increment The contents of the designated register pair are

register incremented by 1 and the result is stored in the
pair by 1 same place.

Example: INX H

DCR R Decremen The contents of the designated register or memory

t register are M decremented by 1 and the result is stored in
M or the same place. If the operand is a memory
memory location, its location is specified by the contents of
by 1 the HL registers.

Example: DCR B or DCR M

DCX R Decremen The contents of the designated register pair are

t register decremented by 1 and the result is stored in the
 pair by 1 same place.

Example: DCX H

DAA none Decimal The contents of the accumulator are changed from
adjust a binary value to two 4-bit binary coded decimal
accumulat (BCD) digits. This is the only instruction that uses
or the auxiliary flag to perform the binary to BCD
conversion, and the conversion procedure is
described below. S, Z, AC, P, CY flags are altered to
reflect the results of the operation.

If the value of the low-order 4-bits in the

accumulator is greater than 9 or if AC flag is set,
the instruction adds 6 to the low-order four bits.

If the value of the high-order 4-bits in the

accumulator is greater than 9 or if the Carry flag is
set, the instruction adds 6 to the high-order four
bits.

Example: DAA

3.LOGICAL INSTRUCTIONS

Opcode Operan Explanation of Description

Instruction

CMP Compare register or The contents of the operand (register or

memory with memory) are M compared with the contents
accumulator of the accumulator. Both contents are
preserved . The result of the comparison is
shown by setting the flags of the PSW as
follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are
reset
Example: CMP B or CMP M

CPI 8-bit Compare immediate The second byte (8-bit data) is compared
with accumulator with the contents of the accumulator. The
values being compared remain unchanged.
The result of the comparison is shown by
setting the flags of the PSW as follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H
ANA Logical AND register The contents of the accumulator are
or memory with logically ANDed with M the contents of the
accumulator operand (register or memory), and the
result is placed in the accumulator. If the
operand is a memory location, its address is
specified by the contents of HL registers. S,
Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.

Example: ANA B or ANA M

ANI 8-bit Logical AND The contents of the accumulator are

immediate with logically ANDed with the
accumulator 8-bit data (operand) and the result is placed
in the
accumulator. S, Z, P are modified to reflect
the result of the
operation. CY is reset. AC is set.

Example: ANI 86H

XRA Exclusive OR The contents of the accumulator are

register or Exclusive ORed with M the contents of the
memory with operand (register or memory), and the
accumulator result is placed in the accumulator. If the
operand is a memory location, its address is
specified by the contents of HL registers. S,
Z, P are modified to reflect the result of the
operation. CY and AC are reset.

Example: XRA B or XRA M

XRI 8-bit Exclusive OR The contents of the accumulator are

immediate with Exclusive ORed with the 8-bit data
accumulator (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect
the result of the operation. CY and AC are
reset.

Example: XRI 86H

ORA Logical OR register The contents of the accumulator are

or memory with logically ORed with M the contents of the
accumulator operand (register or memory), and the
result is placed in the accumulator. If the
operand is a memory location, its address is
specified by the contents of HL registers. S,
Z, P are modified to reflect the result of the
operation. CY and AC are reset.

Example: ORA B or ORA M

ORI 8-bit Logical ORThe contents of the accumulator are logically ORed
immediate with with the 8-bit data (operand) and the result
accumulator is placed in the accumulator. S, Z, P are
modified to reflect the result of the
operation. CY and AC are reset.

Example: ORI 86H

RLC none Rotate Each binary bit of the accumulator is

accumulator left rotated left by one position. Bit D7 is placed
in the position of D0 as well as in the Carry
flag. CY is modified according to bit D7. S,
Z, P, AC are not affected.

Example: RLC

RRC none Rotate Each binary bit of the accumulator is

accumulator right rotated right by one position. Bit D0 is
placed in the position of D7 as well as in the
Carry flag. CY is modified according to bit
D0. S, Z, P, AC are not affected.

Example: RRC

RAL none Rotate Each binary bit of the accumulator is

accumulator left rotated left by one position through the
through carry Carry flag. Bit D7 is placed in the Carry flag,
and the Carry flag is placed in the least
significant position D0. CY is modified
according to bit D7. S, Z, P, AC are not
affected.

Example: RAL

RAR none Rotate Each binary bit of the accumulator is

accumulator right rotated right by one position through the
through carry Carry flag. Bit D0 is placed in the Carry flag,
and the Carry flag is placed in the most
significant position D7. CY is modified
according to bit D0. S, Z, P, AC are not
affected.

Example: RAR

CMA none Complement The contents of the accumulator are

accumulator complemented. No flags are affected.

Example: CMA

CMC none Complement carry The Carry flag is complemented. No other

 flags are affected.

Example: CMC

STC none Set Carry Set Carry

Example: STC

4.BRANCHING INSTRUCTIONS

Opcode Operan Explanatio Description

d n of
Instruction

JMP 16-bit Jump The program sequence is

transferred to the memory
address unconditionall
location specified by the 16-bit
y address given in the operand.

Example: JMP 2034H or JMP

XYZ

Flag 16-bit Jump The program sequence is

Opcode Description address transferred to the memory
conditionally
Status location specified by the 16-bit
address given in the operand
JC Jump on Carry CY = 1 based on the specified flag of
the PSW as described below.
Jump on no
JNC CY = 0 Example: JZ 2034H or JZ XYZ
Carry

JP Jump on positive S=0

JM Jump on minus S=1

JZ Jump on zero Z=1

JNZ Jump on no zero Z=0

Jump on parity
JPE P=1
even

Jump on parity
JPO P=0
odd
Opcode Description Flag Status 16-bit Uncondition The program sequence is
transferred to the memory
address al
CC Call on Carry CY = 1 location specified by the 16-bit
subroutine address given in the operand.
CNC Call on no Carry CY = 0 Before the transfer, the address
call
of the next instruction after CALL
CP Call on positive S=0 (the contents of the program
counter) is pushed onto the
CM Call on minus S=1 stack.
Example: CALL 2034H or CALL
XYZ
CZ Call on zero Z=1

CNZ Call on no zero Z = 0

Call on parity
CPE P=1

Call on parity
CPO P=0

PCHL none Load The contents of registers H and

L are copied into the program
program
counter. The contents of H are
counter with placed as the high-order byte
and the contents of L as the low-
HL contents
order byte.

Example: PCHL

5.Control Instructions

Opcod Operan Explanation of Description

e d Instruction

NOP none No operation No operation is performed. The instruction is

fetched and decoded. However no operation is
executed.

Example: NOP

HLT none Halt and enter wait The CPU finishes executing the current
instruction and halts any further execution. An
state
interrupt or reset is necessary to exit from the
halt state.

Example: HLT
 DI none Disable interrupts The interrupt enable flip-flop is reset and all the
interrupts except the TRAP are disabled. No
flags are affected.
Example: DI

EI none Enable interrupts The interrupt enable flip-flop is set and all
interrupts are enabled. No flags are affected.
After a system reset or the acknowledgement of
an interrupt, the interrupt enable flipflop is
reset, thus disabling the interrupts. This
instruction is
necessary to reenable the interrupts (except
TRAP).
Example: EI

RIM none Read interrupt mas This is a multipurpose instruction used to read
the status of interrupts 7.5, 6.5, 5.5 and read
serial data input bit. The instruction loads eight
bits in the accumulator with the following
interpretations.

Example: RIM

SIM none Set interrupt mask This is a multipurpose instruction and used to
implement the 8085 interrupts 7.5, 6.5, 5.5, and
serial data output. The instruction interprets the
accumulator contents as follows.
Example: SIM

Classification based on length:

I. One-byte instructions: Instruction having one byte in machine code. Examples are
depicted in Table 2.
II. Two-byte instructions: Instruction having two byte in machine code. Examples are
depicted in Table3
III. Three-byte instructions: Instruction having three byte in machine code. Examples are
depicted in Table 4.
INTERRUPTS IN 8085
Interrupts are the signals generated by the external devices to request the microprocessor
to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5,
and INTR.
Interrupt are classified into following groups based on their parameter −
 Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt − In this type of interrupt, the interrupt address is not known
to the processor so, the interrupt address needs to be sent externally by the device
to perform interrupts. For example: INTR.
 Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing
some instructions into the program. For example: RST7.5, RST6.5, RST5.5,INTR.
 Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt
by writing some instructions into the program. For example: TRAP.
 Software interrupt − In this type of interrupt, the programmer has to add the
instructions into the program to execute the interrupt. There are 8 software
interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware
interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTR.
[Note − INTA is not an interrupt, it is used by the microprocessor for sending
acknowledgement. TRAP has the highest priority, then RST7.5 and so on.]
Interrupt Service Routine (ISR)

A small program or a routine that when executed, services the corresponding interrupting
source is called an ISR.
TRAP

It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault, it
is enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the
data to backup memory. This interrupt transfers the control to the location 0024H.
RST7.5

It is a maskable interrupt, having the second highest priority among all interrupts. When
this interrupt is executed, the processor saves the content of the PC register into the stack
and branches to 003CH address.
RST 6.5

It is a maskable interrupt, having the third highest priority among all interrupts. When this
interrupt is executed, the processor saves the content of the PC register into the stack and
branches to 0034H address.
RST 5.5

It is a maskable interrupt. When this interrupt is executed, the processor saves the content
of the PC register into the stack and branches to 002CH address.
INTR

It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled
by resetting the microprocessor.
When INTR signal goes high, the following events can occur −
 The microprocessor checks the status of INTR signal during the execution of each
instruction.
 When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.
 When instructions are received, then the microprocessor saves the address of the
next instruction on stack and executes the received instruction.
TIMING DIAGRAM
Each instruction in 8085 microprocessor consists of two part- operation code (opcode) and
operand. The opcode is a command such as ADD and the operand is an object to be operated on,
such as a byte or the content of a register.
Instruction Cycle: The time taken by the processor to complete the execution of an instruction. An
instruction cycle consists of one to six machine cycles.
Machine Cycle: The time required to complete one operation; accessing either the memory or I/O
device. A machine cycle consists of three to six T-states.
T-State: Time corresponding to one clock period. It is the basic unit to calculate execution of
instructions or programs in a processor.
To execute a program, 8085 performs various operations as:
 Opcode fetch
 Operand fetch
 Memory read/write
 I/O read/write
External communication functions are:
 Memory read/write
 I/O read/write
 Interrupt request acknowledge

1. Opcode Fetch Machine Cycle: It is the first step in the execution of any instruction. The timing
diagram of this cycle is given in Fig. 5. The following points explain the various operations that
take place and the signals that are changed during the execution of opcode fetch machine cycle:
T1 clock cycle
i. The content of PC is placed in the address bus; AD0 - AD7 lines contains lower bit address and
A8 – A15 contains higher bit address.
ii. IO/M signal is low indicating that a memory location is being accessed. S1 and S0 also
changed to the levels as indicated in Table 1.
iii.ALE is high, indicates that multiplexed AD0 – AD7 act as lower order bus.
T2 clock cycle
i. Multiplexed address bus is now changed to data bus.
ii. The RD signal is made low by the processor. This signal makes the memory device load the
data bus with the contents of the location addressed by the processor.
T3 clock cycle
i. The opcode available on the data bus is read by the processor and moved to the instruction
register.
ii. The RD signal is deactivated by making it logic 1.
T4 clock cycle
i. The processor decode the instruction in the instruction register and generate the necessary
control signals to execute the instruction. Based on the instruction further operations such as
fetching, writing into memory etc takes place.

Fig. Timing diagram for opcode fetch cycle

2. Memory Read Machine Cycle: The memory read cycle is executed by the processor to read
a data byte from memory. The machine cycle is exactly same to opcode fetch except: a) It has
three T-states b) The S0 signal is set to 0. The timing diagram of this cycle is given in Fig. 6.

Fig. Timing diagram for memory read machine cycle

3. Memory Write Machine Cycle: The memory write cycle is executed by the processor to
write a data byte in a memory location. The processor takes three T-states and WR signal is
made low. The timing diagram of this cycle is given in Fig. 7.

Fig. Timing diagram for memory write machine cycle

4. I/O Read Cycle: The I/O read cycle is executed by the processor to read a data byte from I/O
port or from peripheral, which is I/O mapped in the system. The 8-bit port address is placed
 both in the lower and higher order address bus. The processor takes three Tstates to execute
this machine cycle. The timing diagram of this cycle is given in Fig. 8.

Fig. Timing diagram I/O read machine cycle

5. I/O Write Cycle: The I/O write cycle is executed by the processor to write a data byte to I/O
port or to a peripheral, which is I/O mapped in the system. The processor takes three T-states
to execute this machine cycle. The timing diagram of this cycle is given in Fig. 9.

Fig. Timing diagram I/O write machine cycle