A B C D E

1 1

LCFC Confidential
2 2

EG521 EG522 EZ511 EG721 MB Schematics Document

Kabylake-U42 with DDR4
2017-04-25
3
REV:0.2 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 1 o f 60

A B C D E
 A B C D E

LCFC confidential

DDR4 SO-DIMM x1
Page 18

Memory Bus (Dual Channel)

1
1.2V DDR4 2133MT/s DDR4 Memory Down 1

4pcs x16 Page 17

USB3.0 x1 USB3.0 Left Conn

USB2.0 x1 USB3.0 Port1
USB2.0 Port1 Page 41
HDMI Conn. HDMI (DDI 1)
Page 34

USB3.0 x1 USB3.0 Left Conn

USB2.0 x1 USB3.0 Port3
eDP x2 Lane USB2.0 Port3 Page 41
eDP Conn
USB2.0 x1
Intel MCP
Int. Camera Conn. USB3.0 x1 Type-C IC
USB2.0 Port4 USB2.0 x1 Realtek RTS5449 Type-C Conn
Page 43 Page43
Int. MIC Conn. KBL-U22/U23E 15W
Page 33
USB2.0 x1 Touch Screen (Optional)
2 2
USB2.0 Port6 Page 33

SATA HDD SATA Gen3 x1

USB2.0 x1
Page 42 Finger Print (Optional)
SATA Port0
BGA-1356
USB2.0 Port7 Page45
42mm*24mm
SATA ODD SATA Gen1 x1 PCIe Gen1 x1 NGFF WLAN&BT
Page 42 SATA Port1A USB2.0 x1 PCIe Port6
USB2.0 Port7 Page 40

SSD/Optane memory LAN Chip

(Optional) PCIe Gen1 x1 RJ45 Conn.
Realtek_RTL8111GUL Page 38
Page 40 PCIe Port 9~12
PCIe Port5 Page 37

SD/MMC Conn.
Page 31
SPI SPI ROM (8MB)
Codec & C/R W25Q64FVSSIQ
3 USB2.0 x1 Page07
3

SPK Conn.
Page 30
HD Audio I2C
Realtek RTS5119
Page 3~16
Touch Pad
HP&Mic Combo Conn.
Page 30 LPC Page 45
Page 30 USB2.0 Port5

EC TPM (Reserved)
ITE IT8586E-LQFP
Page 44
Z32H320TC Page 32

Sub-board( for 15" 17")

Int.KBD Thermal Sensor (Reserved) ODD BOARD

Page 45
NCT7718W Page 39

4 4

Securitii y Clasll sificii ationii LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciiiphered Date 2016/08/20 Block Diagram

THISI SHEET OF ENGINI EERINI G DRAWINII G ISITHE PROPRIETARII Y PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIALII
AND TRADE SECRET IN I FORMATION I . THIS
I SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION I OF R&D Siiize Documenttt Number Re v
DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITI HER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISCI LOSED TO ANY THIRI D PARTY WITI HOUT PRIORII WRITI TEN CONSENT OF LC FUTURE CENTER...
Custttom
EG521 0..2

Dattte::: Tuesday,,, Apriiilll 25,,,2017 Sheettt 2 o ff60

A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3 +3V_PCH
PU301 PU904

V
B+
BATT BATT V +3VALW
1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4
PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN

Vb (DIS)
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU801

V
PU501
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)

V
PU901 VR_ON Q31 +1.5VS_VGA

V
V

+CPU_CORE PU601

V
+5VS
B B

V
Q32 +1.05VSP_VGA

V
SUSP#,SUSP 9 +3VS PU702
VGA

V
PU602

V
+1.5VS +3VS_VGA

V
Q27

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Power sequence block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 47 o f 60

5 4 3 2 1
 5 4 3 2 1

Silergy
PMIC-LV5075AGQV
+1.0VALW/6A
Converter
D D

SUSP# EN FOR PCH PGOOD

+5VLP/ 100mA
B+ Silergy
SY8288CRAC +5VALW/6A
Adaptor Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
PAGE 39

ANPEC
+3VLP/ 100mA
Silergy PMIC-LV5075AGQV +1.8VALW/1A
SY8286BRAC
QFN20_3X3 +3VALW/ 5A EN PGOOD
Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
C PAGE 39 C

Richtek +1.2V/7A

PMIC-LV5075AGQV
SYSON S5
TI SUSP# S3 Switch Mode +0.6VS/2A

BQ24780SRUYR FOR DDR PGOOD

Battery Charger
Switch Mode
PAGE 46 ANPEC
Richtek +1.35V/8A PMIC-LV5075AGQV +2.5V/1A

NB685GQ-Z
EN PGOOD
SYSON S5 QFN16_3X3
SMBus
SUSP# S3
Switch Mode
FOR DDR
B B

PGOOD

Battery Onsemi CPU Core/23A

polymer NCP81206MNR2G VCCGT/25A

2S1P QFN60_7X7
VR_ON
Switch Mode VCCSA/7A
FOR CPU Core
EN PGOOD VGATE
PGOOD_NB

RichTek

A NB681GD-Z VCC_OPC/4.5A A

VIDs
Switch Mode
EC_VR_ON EN FOR GPU VDDC PGOOD

Securityii Clasll sifi ici ationii LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciiiphered Date 2016/08/20 PWR-Power Diagram
THISII SHEET OF ENGINEII ERINGII DRAWINGII ISITHE PROPRIEII TARY PROPERTY OF L C F UTURE CENTER... AND CONTAINSII CONFIDEII NTIALI
AND TRADE SECRET INFIIORMATIOII N... THISII SHEET MAY NOT BE TRANSF ERED F ROM THE CUSTODY OF THE COMPETENT DIVISIOIIIIIIN OF R&D Siiize Documenttt Number R ev
DEPARTMENT EXCEPT AS AUTHORIZII ED BY L C F UTURE CENTER NEITHEII R THISII SHEET NOR THE INFIIORMATIOII N ITICONTAINSII
MAY BE USED BY OR DISI CL OSED TO ANY THIRDII PARTY WITHOII UT PRIOII R WRITTEII N CONSENT OF L C F UTURE CENTER...
Cus t om
CG411 0.. 1

D att e : Tuesday,,, Apriiilll 25,,, 2 0 1 7 Sheettt 50 o ff60

5 4 3 2 1
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON

Power Plane
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+3VALW +5VS

+5VALW +1.2V +3VS S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
1 +VCCIO 1
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
V20B+ +3VALW_PCH +2.5V_DDR +VCCSTG
+VCCSA
+1.8VALW +VCCST +VCC_GT
+1.0VALW +CPU_CORE
State +0.6VS
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 Conn Left @ Not stuff
2 USB Type-C 14@ For 14" part
3 USB3.0 Conn Left 15@ For 15" part
USB3.0
4 NC 14or15@ For 14" or 15" part
S0 O O O O 5 NC 14or17@ For 14" or 17" part
6 NC
1 USB3.0 Conn Left
S3 O O O X 2 USB Type-C Cannonlake@ For Cannonlake part
3 USB3.0 Conn Left CD@ For C cost down
S3 4 Finger Print DUALMIC@ For Dual MIC part
2
Battery only O O O X USB2.0 5 Cardreader EMC@ For EMC part 2

6 Touch Panel EMC_15@ For EMC 15" part

S5 S4 7 Bluetooth EMC_NS@ For EMC nu-stuff part

AC Only O O X X 8 Camera EMC_PX@ For EMC PX part

9 NC EMC_PXNS@ For EMC PX nu-stuff part
S5 S4 10 NC ES@ For ES CPU

Battery only O X X X EXO@ For EXO GPU

1~4 DGPU
S5 S4 X4 PCIE
ME@ For ME part

AC & Battery X X X X 5 LAN

NTS@ For nu-touch part

don't exist
PCIE 6 WLAN DIS@ For GPU part
7 SATA HDD OPT@ For NV GPU part
SMBUS Control Table 8 SATA ODD PX@ For AMD GPU part
RANKA@ For VRAM rank A part
SOURCE BATT Charger DGPU IT8586E Memory PCH PMIC SODIMM Thermal WLAN RANKB@ For VRAM rank B part
Down Sensor WiMAX 9~12 Optane Memory
Realtek_SD@ For Realtek SD part
X4 PCIE
SINGLEMIC@ For single MIC part
3 3
EC_SMB_CK1 IT8586E V V X V X X X X X X 0 HDD SINGLERANK@ For single VRAN rank part
EC_SMB_DA1 +3VL_EC +3VL_EC 1A ODD DUALRANK@ For dual VRAN rank part
SATA
1B used as PCIE TS@ For touch screen part
EC_SMB_CK2 IT8586E X X V V X V X X V X 2 used as PCIE TPM@ For TPM part
EC_SMB_DA2 +3VS +3VG_AON +3VS +3VALW_PCH UMA@ For UMA part

EC_SMB_CK3 IT8586E X X X V X X V X X X
EC_SMB_DA3 +3VL_EC +3VL_EC

PCH_SMB_CLK PCH X X X X X V X V X V
PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS +3VS

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address

Device Address Device Address Device Address Device Address
Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
4 4
Charger 0001 0010 b PCH need to update W lan Reserved
DGPU need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Notes List

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF LC FUTURE CENTER... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: Tu e s d a y, Apriiilll 2 5 , 2 0 1 7 Sheet 3 o f 60

A B C D E
 5 4 3 2 1

SKL_ULT ?
UC1A

HDMI_TX2- E55 C47 CPU_EDP_TX0-

34 HDMI_TX2- HDMI_TX2+ DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0+ CPU_EDP_TX0- 33
HDMI D2 34 HDMI_TX2+ HDMI_TX1-
F55
DDI1_TXP[0] EDP_TXP[0]
C46
CPU_EDP_TX1- CPU_EDP_TX0+ 33
E58 D46
34 HDMI_TX1- HDMI_TX1+ DDI1_TXN[1] EDP_TXN[1] CPU_EDP_TX1+ CPU_EDP_TX1- 33
HDMI D1 34 HDMI_TX1+ HDMI_TX0-
F58
DDI1_TXP[1] EDP_TXP[1]
C45
CPU_EDP_TX1+ 33
34 HDMI_TX0- F53 A45
HDMI_TX0+ DDI1_TXN[2] EDP_TXN[2]
D HDMI D0 34 HDMI_TX0+ HDMI_CLK-
G53
DDI1_TXP[2] EDP_TXP[2]
B45 D

34 HDMI_CLK- F56 A47

HDMI_CLK+ DDI1_TXN[3] EDP_TXN[3]
HDMI CLK 34 HDMI_CLK+ G56
DDI1_TXP[3] EDP_TXP[3]
B47

C50 E45 CPU_EDP_AUX#

D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 CPU_EDP_AUX CPU_EDP_AUX# 33
C52 DDI2_TXP[0] EDP_AUXP CPU_EDP_AUX 33 +3VS
D52 DDI2_TXN[1] B52
A50 DDI2_TXP[1] EDP_DISP_UTIL
B50 DDI2_TXN[2] G50
D51 DDI2_TXP[2] DDI1_AUXN F50 GPP_E15 RC1601 1 @ 2 10K_0402_5%
C51 DDI2_TXN[3] DDI1_AUXP E48
DDI2_TXP[3] DDI2_AUXN F48
DDI2_AUXP G46
DISPLAY SIDEBANDS DDI3_AUXN F46
DDPB_CLK L13 DDI3_AUXP
34 DDPB_CLK DDPB_DATA L12 GPP_E18/DDPB_CTRLCLK L9 HDMI_HPD
34 DDPB_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 HDMI_HPD 34
L7
DDPC_CLK N7 GPP_E14/DDPC_HPD1 L6 GPP_E15 RC181 1 2 0_0402_5%
DDPC_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 EC_SCI# 44
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD
GPP_E17/EDP_HPD CPU_EDP_HPD 33
N11
N12 GPP_E22/DDPD_CTRLCLK

1
+VCCIO R12 PCH_ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R11 PCH_EDP_PWM PCH_ENBKL 33
RC13
EDP_COMP EDP_BKLTCTL U13 PCH_ENVDD PCH_EDP_PWM 33
RC4 2 1 24.9_0402_1% E52 100K_0402_5%
EDP_RCOMP EDP_VDDEN PCH_ENVDD 33
+VCCIO&EDP_COMP : 1 OF20
Trace Width: 20mil SKYLAKE-U_BGA1356

2
Isolation Spacing: 25mil REV = 1 ?
M ax length: 100mil @

C C

+VCCST_CPU

1
+VCCSTG
RC1625
@ 49.9_0402_1%
1

RC19 UC1D SKL_ULT ?

2
1K_0402_5%
check PROCHOT# circuit with PWR CATERR# D63
H_PECI CATERR#
44 H_PECI A54
2

RC20 1 2 499 +-1%0402 H_PROCHOT#_R PECI XDP_TCK RC1546 1 2 0_0402_5% JTAGX RC1551 1 2 51_0402_5%
C65 JTAG
44,55 H_PROCHOT# H_THRMTRIP# PROCHOT#
C63
A65 THERMTRIP# B61 XDP_TCK 1 XDP_TDO RC1547 1 PCH_JTAG_TDO
SKTOCC# PROC_TCK XDP_TDI TC15 PAD @ 2 0_0402_5% RC1543 1 2 51_0402_5% +VCCSTG
D60 1
CPU MISC PROC_TDI TC16 PAD @
1

1 XDP_BPM0# C55 A61 XDP_TDO 1

PAD @ TC11 TC17 PAD @
RC143 1 XDP_BPM1# D55 BPM#[0] PROC_TDO C60 XDP_TMS 1 XDP_TDI PCH_JTAG_TDI
PAD @ TC12 TC18 PAD @ RC1548 1 2 0_0402_5%
1 XDP_BPM2# B54 BPM#[1] PROC_TMS B59 XDP_TRST# 1
1K_0402_5% PAD @ TC13 TC27 PAD @
PAD @ TC14 1 XDP_BPM3# C56 BPM#[2] PROC_TRST# XDP_TMS RC1549 1 2 0_0402_5% PCH_JTAG_TMS
BPM#[3] B56 PCH_JTAG_TCK 1 TC29 PAD @
2

1 GPP_E3 A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI 1 XDP_TRST# PCH_JTAG_TRST#

PAD @ TC162 TC31 PAD @ RC1550 1 2 0_0402_5%
+VCCST_CPU A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO 1
TC35 PAD @
BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS 1 TC36 PAD @
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 PCH_JTAG_TRST# 1
check H_THRMTRIP# if need to connector to EC GPP_B4/CPU_GP3 PCH_TRST# A59 TC42 PAD @ check JTAG circuit?
JTAGX 1 TC43 PAD @
RC155 1 2 49.9_0402_1% PROC_OPI_RCOMP AT16 JTAGX
RC156 1 2 49.9_0402_1% PCH_OPI_RCOMP AU16 PROC_POPIRCOMP
U23E@ RC157 1 2 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
U23E@ RC170 1 2 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
B OPC_RCOMP B

1 OF20
SKYLAKE-U_BGA1356
REV = 1 ?
@

+3VS check DDPC_CLK pull high or not?

DDP*_CTRLDATA strapping sampled on the rising edge of PWROK
RPC26
DDPC_CLK
Port Strap Enable Disable
1
2
4 @
3 DDPC_DATA Disable DDI2 G320 SDV wei
Pull up to 3.3 V 2.2K_0404_4P2R_5%
Port 1 DDPB_CTRLDATA with 2.2Kohm NC
RPC27
Pull up to 3.3 V 1 4 DDPB_CLK
Port 2 DDPC_CTRLDATA with 2.2Kohm NC 2 3 DDPB_DATA

2.2K_0404_4P2R_5%

A A

Securiiity Clllassiiifiiicatiiion LC Future Center Secret Data Title

Issued Date 2015/08/20 Decipii hered Date 2016/08/20 MCP (DDI,EDP)
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF LC FUTURE CENTER... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CENTER...
Custttom
EG521 0..2

Dat e: Tuesday,,, Apriiilll 25,,,2017 Sheet 4 o f 60

5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1B

AU53
17 DDRA_DQ[0..63] DDRA_DQ0 AL71 DDR0_CKN[0] DDRA_CLK0# 17
AT53
DDRA_DQ1 AL68 DDR0_DQ[0] DDR0_CKP[0] DDRA_CLK0 17
AU55
DDRA_DQ2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55
DDRA_DQ3 AN69 DDR0_DQ[2] DDR0_CKP[1]
DDRA_DQ4 AL70 DDR0_DQ[3] BA56
DDRA_DQ5 AL69 DDR0_DQ[4] DDR0_CKE[0] DDRA_CKE0 17
BB56
D DDRA_DQ6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW 56 D
DDRA_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDRA_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3]
DDRA_DQ9 AR68 DDR0_DQ[8] AU45
DDRA_DQ10 AU71 DDR0_DQ[9] DDR0_CS#[0] DDRA_CS0# 17
AU43
DDRA_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45
DDRA_DQ12 AR71 DDR0_DQ[11] DDR0_ODT[0] DDRA_ODT0 17
AT43
DDRA_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1]
DDRA_DQ14 AU70 DDR0_DQ[13] BA51
DDRA_DQ15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDRA_MA5 17
BB54
DDRA_DQ16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDRA_MA9 17
BA52
DDRA_DQ17 AW 65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDRA_MA6 17
AY52
DDRA_DQ18 AW 63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDRA_MA8 17
AW 52
DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDRA_MA7 17
DDRA_DQ19 AY63 AY55
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDRA_BG0 17
DDRA_DQ20 BA65 AW 54
DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDRA_MA12 17
DDRA_DQ21 AY65 BA54
DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDRA_MA11 17
DDRA_DQ22 BA63 BA55
DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDRA_ACT# 17
DDRA_DQ23 BB63 AY54
DDRA_DQ24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDRA_DQ25 AW 61 DDR0_DQ[24]/DDR0_DQ[40]
AU46 DDRA_MA13 17
DDRA_DQ26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48
DDRA_DQ27 AW 59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDRA_MA15_CAS# 17
AT46
DDRA_DQ28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_W E#/DDR0_CAB[2]/DDR0_MA[14] DDRA_MA14_WE# 17
AU50
DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDRA_MA16_RAS# 17
DDRA_DQ29 AY61 AU52
DDRA_DQ30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDRA_BS0# 17
AY51
DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDRA_MA2 17
DDRA_DQ31 AY59 AT48
DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDRA_BS1# 17
DDRA_DQ32 AY39 AT50
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDRA_MA10 17
DDRA_DQ33 AW 39 BB50
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDRA_MA1 17
DDRA_DQ34 AY37 AY50
DDR0_DQ[34]/DDR1_DQ[2] DDRA_MA0 17
DDRA_DQ35 AW 37 DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50
DDR0_DQ[35]/DDR1_DQ[3] DDRA_MA3 17
DDRA_DQ36 BB39 DDR0_MA[3] BB52
DDR0_DQ[36]/DDR1_DQ[4] DDRA_MA4 17
DDRA_DQ37 BA39 DDR0_MA[4]
C DDRA_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDRA_DQS#0 C
DDRA_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDRA_DQS0
DDRA_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDRA_DQS#1
DDRA_DQ41 AW 35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDRA_DQS1
DDRA_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDRA_DQS#2
DDRA_DQ43 AW 33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDRA_DQS2 DDRA_DQS#[0..7]
DDRA_DQ44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDRA_DQS#3 DDRA_DQS#[0..7] 17
DDRA_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDRA_DQS3 DDRA_DQS[0..7]
DDRA_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDRA_DQS#4 DDRA_DQS[0..7] 17
DDRA_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDRA_DQS4
DDRA_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDRA_DQS#5
DDRA_DQ49 AW 31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] DDRA_DQS5
BA34
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1]
DDRA_DQ50 AY29 BA30 DDRA_DQS#6
DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4]
DDRA_DQ51 AW 29 AY30 DDRA_DQS6
DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4]
DDRA_DQ52 BB31 AY26 DDRA_DQS#7
DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5]
DDRA_DQ53 BA31 BA26 DDRA_DQS7
DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDRA_DQ54 BA29
DDRA_DQ55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW 50
DDRA_DQ56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDRA_ALERT# 17
AT52
DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDRA_PAR 17
DDRA_DQ57 AW 27 SMVREF
DDR0_DQ[57]/DDR1_DQ[41]
DDRA_DQ58 AY25
DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA
AY67
DDR_SA_VREFCA 17 WIDTH:20MIL
DDRA_DQ59 AW 25 AY68 SPACING: 20MIL
DDRA_DQ60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ BA67
DDR CH - A
DDRA_DQ61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ DDR_SB_VREFCA 18
DDRA_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW 67 DDR_VTT_CNTL
DDRA_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR0_DQ[63]/DDR1_DQ[47]
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
B B

+3VALW

RC30
100K_0402_5%
2

CPU_DRAMPG_CNTL 55
+1.2V
1

C
RC3 1 2 2 QC18
1K_0402_5% B
E
3

MMBT3904WH_SOT323-3

DDR_VTT_CNTL
2

RC29 @
10K_0402_5%
1

A A

Securiiity Clllassiiifiiicatiiion LC Future Center Secret Data Title

Issued Date 2015/08/20 Decipii hered Date 2016/08/20 MCP (DDR4)
THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIETARII Y PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIALII
AND TRADE SECRET INI FORMATIONII .. THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONIIIII OF Siiize Document Number R ev
R&D DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITI HER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISCI LOSED TO ANY THIRI D PARTY WITI HOUT PRIORII WRITI TEN CONSENT OF LC FUTURE CENTER...
Custtom
EG521 0..2

Date: Tuesday,,, Apriiilll 25,,,2017 Sheet 5 o f 60

5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1C
18 DDRB_DQ[0..63]

DDRB_DQ0 AF65 AN45

DDRB_DQ1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDRB_CLK0# 18
DDRB_DQ2 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDRB_CLK1# 18
DDRB_DQ3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDRB_CLK0 18
DDRB_DQ4 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDRB_CLK1 18
D DDRB_DQ5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 D
DDRB_DQ6 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDRB_CKE0 18
DDRB_DQ7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDRB_CKE1 18
DDRB_DQ8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDRB_DQ9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDRB_DQ10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDRB_DQ11 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDRB_CS0# 18
DDRB_DQ12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDRB_CS1# 18
DDRB_DQ13 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW 42 DDRB_ODT0 18
DDRB_DQ14 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDRB_ODT1 18
DDRB_DQ15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
DDRB_DQ16 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDRB_MA5 18
DDRB_DQ17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDRB_MA9 18
DDRB_DQ18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDRB_MA6 18
DDRB_DQ19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDRB_MA8 18
DDRB_DQ20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDRB_MA7 18
DDRB_DQ21 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDRB_BG0 18
DDRB_DQ22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48
DDRB_MA12 18
DDRB_DQ23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53
DDRB_MA11 18
DDRB_DQ24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52
DDRB_DQ25 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDRB_ACT# 18
DDRB_DQ26 AP60 DDR1_DQ[25]/DDR0_DQ[57] DDRB_BG1 18
BA43
DDRB_DQ27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDRB_MA13 18
DDRB_DQ28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDRB_MA15_CAS# 18
DDRB_DQ29 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_W E#/DDR1_CAB[2]/DDR1_MA[14] AW 44 DDRB_MA14_WE# 18
DDRB_DQ30 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDRB_MA16_RAS# 18
DDRB_DQ31 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDRB_BS0# 18
DDRB_DQ32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDRB_MA2 18
DDRB_DQ33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW 46 DDRB_BS1# 18
DDRB_DQ34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDRB_MA10 18
DDRB_DQ35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46
DDRB_DQ36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDRB_MA1 18
BB46
C DDRB_DQ37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] DDRB_MA0 18 C
BA47
DDRB_DQ38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDRB_MA3 18
DDRB_DQ39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDRB_DQS#0 DDRB_MA4 18
DDRB_DQ40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDRB_DQS0
DDRB_DQ41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDRB_DQS#1
DDRB_DQ42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDRB_DQS1
DDRB_DQ43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDRB_DQS#2
DDRB_DQ44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDRB_DQS2
DDRB_DQ45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDRB_DQS#3 DDRB_DQS#[0..7]
DDRB_DQ46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDRB_DQS3 DDRB_DQS#[0..7] 18
DDRB_DQ47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDRB_DQS#4 DDRB_DQS[0..7]
DDRB_DQ48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDRB_DQS4 DDRB_DQS[0..7] 18
DDRB_DQ49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDRB_DQS#5
DDRB_DQ50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDRB_DQS5
DDRB_DQ51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDRB_DQS#6
DDRB_DQ52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDRB_DQS6
DDRB_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDRB_DQS#7
DDRB_DQ54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDRB_DQS7
DDRB_DQ55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDRB_DQ56 AT22 DDR1_DQ[55] AN43
DDRB_DQ57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 DDRB_ALERT# 18
DDRB_DQ58 AU21 DDR1_DQ[57] DDR1_PAR AT13 CPU_DRAMRST#_R DDRB_PAR 18
DDRB_DQ59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP_0 RC24 1 2 121_0402_1%
DDRB_DQ60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1 RC25 1 2 80.6_0402_1%
DDRB_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 RC26 1 2 100_0402_1%
DDRB_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDRB_DQ63 AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
B @ B

+1.2V
1

RC22
470_0402_5%
2

RC23 1 2 0_0402_5% CPU_DRAMRST#_R

17,18 CPU_DRAMRST#

1
CC1
0.01U_0201_25V6-K
EMC_NS@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 6 o f 60

5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH +3VS +3VS

?
SKL_ULT
UC1E

3
4

4
3
SPI - FLASH
SMBUS, SMLINK
SPI_CLK_R AV2 R7 PCH_SMB_CLK RPC20 RPC24
SPI0_CLK GPP_C0/SMBCLK R8

2
D SPI_CLK SPI_CLK_R PCH_SMB_DATA D
RC1539 1 2 15_0402_5% SPI_SO_R AW 3 DIMM, NGFF 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
44 SPI_CLK SPI_SI_R SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT#
AV3
SPI_WP#_R AW 2 SPI0_MOSI GPP_C2/SMBALERT #

2
1

1
2
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R SPI_HOLD#_R AU4 SPI0_IO2 R9 SML0_CLK
44 SPI_SO SPI_CS0#_R SPI0_IO3 GPP_C3/SML0CLK W 2 SML0_DATA PCH_SMB_CLK
AU3 QC2A 6 1
SMB_CLK_S3 18,40

S
AU2 SPI0_CS0# GPP_C4/SML0DATA W 1 SML0_ALERT#

D
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R SPI0_CS1# GPP_C5/SML0ALERT # 2N7002KDWH_SOT363-6
44 SPI_SI AU1
SPI0_CS2#

5
W3 PCH_SML1_CLK

G
GPP_C6/SML1CLK V3 PCH_SML1_DAT
SPI_CS0# SPI_CS0#_R SPI - TOUCH GPP_C7/SML1DATA AM7 SML1_ALERT#
GPU, EC, Thermal Sensor
RC51 1 2 0_0402_5%
44 SPI_CS0# GPP_B23/SML1ALERT#/PCHHOT #
M2
M3 GPP_D1/SPI1_CLK PCH_SMB_DATA QC2B 3 4
SMB_DATA_S3 18,40

S
J4 GPP_D2/SPI1_MISO

D
V1 GPP_D3/SPI1_MOSI 2N7002KDWH_SOT363-6
V2 GPP_D21/SPI1_IO2
BOARD_ID4 M1 GPP_D22/SPI1_IO3 LPC AY13
8 BOARD_ID4 GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_AD0 32,44
BA13
GPP_A2/LAD1/ESPI_IO1 BB13 LPC_AD1 32,44
C LINK GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD2 32,44
GPP_A4/LAD3/ESPI_IO3 BA12 LPC_AD3 32,44
G3
CL_CLK GPP_A5/LFRAME#/ESPI_CS# BA11 SUS_STAT# LPC_FRAME# 32,44 1
G2
CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# TC81@
G1
CL_RST#
AW9 CLK_PCI_EC_R
GPP_A9/CLKOUT_LPC0/ESPI_CLK RC173 2 1 22_0402_5% CLK_PCI_EC 44
KBRST# AW13 AY9 CLK_PCI_TPM_R
44 KBRST# RC1541 2 TPM@ 1 22_0402_5% CLK_PCI_TPM 32
GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN#
GPP_A8/CLKRUN# PM_CLKRUN# 32
SERIRQ AY11
32,44 SERIRQ GPP_A6/SERIRQ

1 OF 20
SKYLAKE-U_BGA1356
REV = 1
?
@

+3V_SPI
C C
+3VS +3VALW_PCH
check CLKRUN# / SUS_STAT# signal if need to connect +3VS
RC171 1 2 0_0402_5% +3VALW_PCH

RC172 1 @ 2 0_0402_5%
PM_CLKRUN# RC11 1 2 8.2K_0402_5% SMB_ALERT# 2 1 RC1562
+3V_SPI 2.2K_0402_5%

1. If support DS3, connect to +3VS and don't support EC mirror code; SERIRQ RC12 1 2 10K_0402_5%
* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
KBRST# RC10 1 2 10K_0402_5%
+3VALW_PCH

RPC23
SML0_CLK 4 1
KBRST# CC1255 1 2 1000P_0201_50V7-K SML0_DATA 3 2

EMC_N S@ 2.2K_0404_4P2R_5%
+3V_SPI

+3VALW_PCH
1

RC60 RC61
1K_0402_5% 1K_0402_5% SML0_ALERT# RC1564 2 @ 1 2.2K_0402_5%
Check with BIOS, SPI is Dual mode or quad mode
2

This signal has a weak internal pull-down. 0

SPI_WP#_R RC54 1 @ 2 15_0402_5% SPI_WP# +3VALW_PCH +3VS = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.
SPI_HOLD#_R RC55 1 @ SPI_HOLD#
Notes:
2 15_0402_5% 1.The internal pull-down is disabled after RSMRST#
de-asserts.
4
3

2.This signal is in the primary wel

RPC25 Rising edge of RSMRST#

2
B B
2.2K_0404_4P2R_5% +3VALW_PCH

G
1
2

PCH_SML1_CLK QC10A 6 1 @ SML1_ALERT# RC1569 1 @ 2 150K_0402_5% +3VS

EC_SMB_CK2 39,44
S
D

2N7002KDWH_SOT363-6 RC1655 1 2 150K_0402_5%

5
+3V_SPI

G
UC3
SPI_CS0# 1 8
/CS VCC
To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be added
PCH_SML1_DAT QC10B 3 4 @ EC_SMB_DA2 39,44 to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#. (Refer to
S
SPI_SO 2 7 SPI_HOLD#
WW52_MOW)
D

DO (IO1) IO3 1
CC8 2N7002KDWH_SOT363-6
SPI_WP# 3 6 SPI_CLK 0.1u_0201_10V6K
IO2 CLK
4 5 SPI_SI 2
GND DI (IO0)

W25Q64JVSSIQ_SO8

A A

Securiiity Clllassiiifiiicatiiion LC Future Center Secret Data Title

Issued Date 2015/08/20 Decipherii ed Date 2016/08/20 MCP (MISC,JTAG,SPI,LPC,SMB)

PC,SMB)
THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIAI L
AND TRADE SECRET INIFORMATIONII .. THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R &
DDEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIZEII D BY LC FUTURE CENTER NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORII WRITTEII N CONSENT OF LC FUTURE CENTER...
C
EG521 0..2

Dattte::: Tuesday,,, Apriiilll 25,,, 2017 Sheettt 7 o ff60

5 4 3 2 1
 5 4 3 2 1

+3VS

@UMA SKU
RC1558 1 UMA@ 2 10K_0402_5% DGPU_PWROK

1 RC1613 2

2
@ 15@ @ DIS@ PX@ @

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
1 RC1615 2

1 RC1611 2

1 RC1609 2

1 RC1606 2
RC1608
1
BOARD_ID0
BOARD_ID1
BOARD_ID2
D +3VS 9 BOARD_ID2 BOARD_ID3 D
BOARD_ID4
7 BOARD_ID4 BOARD_ID5
RPC28
1 4 PCH_I2C_SDA0
2 3 PCH_I2C_SCL0

10K_0402_5%
1 RC1614 2

1 RC123 2
2.2K_0404_4P2R_5% 14@ @ UMA@ OPT@ @

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
1 RC1616 2

1 RC1612 2

1 RC1610 2

1 RC1607 2
RC1658 2 1 10K_0402_5% PCH_TP_INT# UC1F SKL_ULT ?

LPS S ISH
10/25 SIT For I2C T/P Function wei
AN8 P2 BOARD_ID0
AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 BOARD_ID1
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
+3VS RC1561 1 @ 2 2.2K_0402_5%
GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 BOARD_ID3
GPP_B18/GSPI0_MOSI GPP_D12
AM5 M4 BOARD_ID6
PCH_CMOS_ON# AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3 BOARD_ID5
33 PCH_CMOS_ON# AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
RC1563 1 @ 2 2.2K_0402_5% GPP_B22 AN5 GPP_B21/GSPI1_MISO N1 BOARD_ID7 Board ID Description Stuff R
+3VS GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2 BOARD_ID8
AB1 GPP_D8/ISH_I2C1_SCL 00 14" RC1616 RC1614
40 UART_RX_DEBUG AB2 GPP_C8/UART0_RXD AD11
40 UART_TX_DEBUG W 4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 Board_ID[0:1] 01 15" RC1616 RC1613
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS# 10 17" RC1615 RC1614
RC1595 2 @ 1 10K_0402_5% PCH_CMOS_ON# AD1 U1
RC1596 2 1 10K_0402_5% PCH_WLAN_OFF# AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
11 Reserved RC1615 RC1613
RC1597 2 1 10K_0402_5% PCH_BT_OFF# DGPU_PWROK AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 0 Reserved RC1612
Board_ID2
double check if need the pull up resisor GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
1 Reserved RC1611
AC1
RC1656 1 2 0_0402_5% PCH_I2C_SDA0 U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
45 TP_I2C_SDA0 PCH_I2C_SCL0 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD 0 UMA RC1610
45 TP_I2C_SCL0
RC1657 1 2 0_0402_5% U6 AC3 Board_ID3
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
PCH_WLAN_OFF# U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS# PCH_TP_INT# 45 1 DIS RC1609
40 PCH_WLAN_OFF# PCH_BT_OFF# U9 GPP_C18/I2C1_SDA AY8 0 RC1607
C
40 PCH_BT_OFF# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 Board_ID4 NV GPU C

AH9 GPP_A19/ISH_GP1 BB7

AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7 1 AMD GPU RC1608
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7
AH11 GPP_A22/ISH_GP4 AW7 Board_ID5 0 Reserved RC123
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6 1 Reserved RC1606
AF11
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL +3VS

+3VALW_PCH +3VS SKYLAKE-U_BGA1356 1 OF 20

REV = 1 ?
RC1600 1 @ 2 1K_0402_5% @ DIMM_ONLY@ DIMM_ONLY@ 520Z@ @ @

RC47 1 @ 2 1K_0402_5% HDA_SDOUT

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2 RC1631 1

2 RC1632 1

2 RC1633 1

2 RC1639 1

2 RC1651 1
*
HDA_SDO This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap BOARD_ID6
should only be asserted high during external pull-up in BOARD_ID7
manufacturing/debug environments ONLY. BOARD_ID8
BOARD_ID9
BOARD_ID10
UC1G SKL_ULT ?
HDA_SDIN0 @ @ 320G@ @ @
For EMI
1 AUDIO
CC7

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2 RC1634 1

2 RC1635 1

2 RC1636 1

2 RC1640 1

2 RC1652 1
10P_0201_50V8F RC43 1 2 33_0402_5% HDA_SYNC BA22
30 HDA_SYNC_AUDIO HDA_SYNC/I2S0_SFRM
EMC_NS@ RC42 1 2 33_0402_5% HDA_BCLK AY22
30 HDA_BITCLK_AUDIO
2 HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK SDIO/SDXC
HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
30 HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
RC44 1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
30 HDA_RST_AUDIO# J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
B
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12 B

AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11

I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W 8
RC45 1 2 33_0402_5% HDA_SDOUT AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W 7
30 HDA_SDOUT_AUDIO
RC46 1 2 0_0402_5% AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
44 ME_FLASH AK10 GPP_F2/I2S2_TXD Board ID Description Stuff R
BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL Samsung 8Gb
BOARD_ID10 H5 AB7 SD_RCOMP 00 2400 MT/s RC1634 RC1635
BOARD_ID9 D7 GPP_D19/DMIC_CLK0 SD_RCOMP
+3VS GPP_D20/DMIC_DATA0 Hynix 8Gb
01 RC1634 RC1632

1
D8 AF13 2400 MT/s
C8 GPP_D17/DMIC_CLK1 GPP_F23
RC49 Board_ID
RC14 1 @ 2 2.2K_0402_5% PCH_BEEP GPP_D18/DMIC_DATA1
200_0402_1% [6,7] Micron 8Gb
30 PCH_BEEP
PCH_BEEP AW 5 10 2400 MT/s RC1631 RC1635
GPP_B14/SPKR

2
11 SO-DIMM Only RC1631 RC1632
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@ 0 320G RC1636
Board_ID8
Default When 1 520Z RC1633
Pin Name Strap Description Configuration Value Sampled
Internal PD 0 Reserved RC1640
0 = Disable “ Top Swap” Board_ID9
SPKR / Top Swap 0 Rising edge
GPP_B14 Override
mode. (Default)
1 = Enable “ Top S wap” * of PCH_PWROK 1 Reserved RC1639
mode.
Internal PD 0 Reserved RC1652
GSPI0_MOSI 0 = Disable “ No Reboot ” Rising edge Board_ID1
/GPP_B18 No Reboot 0 of PCH_PWROK
mode. (Default)
1 = Enable “ No Reboot”* 0 1 Reserved RC1651
A mode A

GSPI1_MOSI Boot BIOS Internal PD Rising edge

/GPP_B22 Strap Bit
BBS
0 = SPI (Default)
1 = LPC
* 0 of PCH_PWROK

Securiiity Clllassiiifiiicatiiion LC Future Center Secret Data Title

Issued Date 2015/08/20 Decipherii ed Date 2016/08/20 MCP (LPSS,ISH,AUDIO,SDIO)

SDIO)
THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIAI L
AND TRADE SECRET INIFORMATIONII .. THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R &
DDEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIZEII D BY LC FUTURE CENTER NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORII WRITTEII N CONSENT OF LC FUTURE CENTER...
C
EG521 0..2

Dattte::: Tuesday,,, Apriiilll 25,,, 2017 Sheettt 8 off 60

5 4 3 2 1
 5 4 3 2 1

D D

SKL_ULT ?
UC1H

SSIC / USB3
PCIE/USB3/SATA
H8 USB30_RX_N1
USB3_1_RXN G8 USB30_RX_P1 USB30_RX_N1 41
H13 USB3_1_RXP C13 USB30_TX_N1 USB30_RX_P1 41 LEFT USB3.0
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB30_TX_P1 USB30_TX_N1 41
B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX_P1 41
A17 PCIE1_TXN/USB3_5_TXN J6 USB30_RX_N2
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6 USB30_RX_P2 USB30_RX_N2 43
G11 USB3_2_RXP/SSIC_1_RXP B13 USB30_TX_N2 USB30_RX_P2 43
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB30_TX_P2 USB30_TX_N2 43 Type-C
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB30_TX_P2 43
C16 PCIE2_TXN/USB3_6_TXN J10 USB30_RX_N3
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10 USB30_RX_P3
USB3_3_RXP/SSIC_2_RXP B15 USB30_RX_N3 41
H16 USB30_TX_N3
G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15 USB30_TX_P3 USB30_RX_P3
USB30_TX_N3
41
41
LEFT USB3.0
D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
USB30_TX_P3 41
C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
F15 PCIE4_RXN USB3_4_TXN D15
B19 PCIE4_RXP USB3_4_TXP
A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 AB10 USB20_P1 USB20_N1 41
37 PCIE_PRX_DTX_N5
PCIE_PRX_DTX_N5 F16 USB2P_1 USB20_P1 41 LEFT USB3.0
PCIE_PRX_DTX_P5 E16 PCIE5_RXN AD6 USB20_N2
37 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 C19 PCIE5_RXP USB2N_2 AD7 USB20_P2 USB20_N2 43
CC1262 1 2 0.1u_0201_10V6K
LAN 37 PCIE_PTX_C_DRX_N5
CC1261 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P5 D19 PCIE5_TXN USB2P_2 USB20_P2 43 Type-C
C 37 PCIE_PTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3 C
PCIE_PRX_DTX_N6 G18 USB2N_3 AJ3 USB20_P3 USB20_N3 41
40 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 F18 PCIE6_RXN USB2P_3 USB20_P3 41 LEFT USB3.0
40 PCIE_PRX_DTX_P6 CC1264 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N6 D20 PCIE6_RXP AD9 USB20_N4
WLAN 40 PCIE_PTX_C_DRX_N6 CC1263 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P6 C20 PCIE6_TXN USB2N_4 AD10 USB20_P4 USB20_N4 45
40 PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 45 Finger Print
SATA_PRX_DTX_N0 F20 AJ1 USB20_N5
42 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 30
E20 AJ2
42 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 B21 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 30 Card reader
SATA HDD 42 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN
USB2
AF6 USB20_N6
PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USB20_P6 USB20_N6 33
42 SATA_PTX_DRX_P0
SATA_PRX_DTX_N1 G21 USB2P_6 USB20_P6 33 Touchpanel
42 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
42 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_P7 USB20_N7 40
SATA ODD 42 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 40 BT
PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
42 SATA_PTX_DRX_P1 USB20_N8 33
PCIE_PRX_DTX_N9 E22 USB2N_8 AF9 USB20_P8
40 PCIE_PRX_DTX_N9 OPTANE@ PCIE_PRX_DTX_P9 E23 PCIE9_RXN USB2P_8 USB20_P8 33 Camera
40 PCIE_PRX_DTX_P9 CC22 1 2 0.22U_0201_6.3V6-KPCIE_PTX_DRX_N9 B23 PCIE9_RXP AG1
40 PCIE_PTX_C_DRX_N9 CC23 1 2 0.22U_0201_6.3V6-KPCIE_PTX_DRX_P9 A23 PCIE9_TXN USB2N_9 AG2
40 PCIE_PTX_C_DRX_P9 PCIE9_TXP USB2P_9
PCIE_PRX_DTX_N10 F25
OPTANE@ PCIE10_RXN AH7
40 PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 E25 USB2N_10
OPTANE@ PCIE10_RXP AH8
40 PCIE_PRX_DTX_P10 CC1266 1 2 0.22U_0201_6.3V6-KPCIE_PTX_DRX_N10 D23 USB2P_10
40 PCIE_PTX_C_DRX_N10 CC1265 1 2 0.22U_0201_6.3V6-KPCIE_PTX_DRX_P10 C23 PCIE10_TXN AB6 USB2_COMP RC118 2 1 113_0402_1% USBRBIAS
OPTANE@ PCIE10_TXP USB2_COMP USB2_ID RC1626 1 2 0_0402_5% Width 20Mil
40 PCIE_PTX_C_DRX_P10 AG3
PCIE_RCOMPN USB2_ID USB2_VBUSSENSE RC1627 1
RC119 1 2 100_0402_1% F5
USB2_VBUSSENSE
AG4 2 1K_0402_5% Space 15Mil
PCIE_RCOMPP PCIE_RCOMPN
E5
PCIE_RCOMPP USB_OC0#
Length 500Mil
A9
Optane Memory PCIE_RCOMPN and PCIE_RCOMPP PAD @ TC20 1 XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1#
USB_OC1# 41
Trace Width: 12-15mil PAD @ TC19 1 XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2#
Differential between RCOMPP/RCOMPN BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
PIRQA#
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# B
PCIE_PRX_DTX_N11 E28 GPP_E4
40 PCIE_PRX_DTX_N11 PCIE11_RXN/SATA1B_RXN J1 RC1628 1 2 0_0402_5%
PCIE_PRX_DTX_P11 E27 GPP_E4/DEVSLP0 J2 GPP_E5 1 EC_SMI# 44
OPTANE@ PCIE11_RXP/SATA1B_RXP
40 PCIE_PRX_DTX_P11 CC1267 1 2 0.22U_0201_6.3V6-KPCIE_PTX_DRX_N11 D24 GPP_E5/DEVSLP1
J3 @ PAD TC202
40 PCIE_PTX_C_DRX_N11 1 2 0.22U_0201_6.3V6-KPCIE_PTX_DRX_P11 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
40 PCIE_PTX_C_DRX_P11
CC1268
PCIE_PRX_DTX_N12 E30 PCIE11_TXP/SATA1B_TXP H2 SATA0GP
2016/05/03: Implement as Power Button
OPTANE@
40 PCIE_PRX_DTX_N12
OPTANE@ PCIE_PRX_DTX_P12 F30
PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0
H3 ODD_DETECT# function for Windows RedStone support
40 PCIE_PRX_DTX_P12 CC1269 1 2 0.22U_0201_6.3V6-KPCIE_PTX_DRX_N12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 SATA2GP
40 PCIE_PTX_C_DRX_N12 CC1270 1 2 0.22U_0201_6.3V6-KPCIE_PTX_DRX_P12 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
40 PCIE_PTX_C_DRX_P12 PCIE12_TXP/SATA2_TXP H1 BOARD_ID2
GPP_E8/SATALED# BOARD_ID2 8
OPTANE@

SKYLAKE-U_BGA1356 1 OF 20
REV = 1
?
@

+3VS

+3VALW_PCH

+3VS GPP_E4 RC1617 2 @ 1 10K_0402_5%

RPC2 RPC17
1 8 ODD_DETECT# USB_OC0# 8 1
2 7 SATA0GP USB_OC1# 7 2
3 6 SATA2GP USB_OC3# 6 3
4 USB_OC2# 5 4 USB_OC2# RC1654 1 20_0402_5%
5 PIRQA# TYPE_C_OCP# 43
10K_0804_8P4R_5% 10K_0804_8P4R_5%
8/24 Reserve TYPE_C_OCP# to CPU USB_OC2# wei
A A

SATA2GP RC189 1 2 0_0402_5%

SSD_DET# 40
OPTANE@
Add SSD_DET# for Optane memory wei
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 3,USB2)

MCP (PCIE,SATA,USB3,USB2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 9 o f 60

5 4 3 2 1
 5 4 3 2 1

UC1I
SKL_ULT ?

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
CSI2_DP0 CSI2_CLKP0
C38 C32
CSI2_DN1 CSI2_CLKN1
D38 D32
CSI2_DP1 CSI2_CLKP1
C36 C29
D CSI2_DN2 CSI2_CLKN2 D
D36 D29
CSI2_DP2 CSI2_CLKP2
check the Pull up resistor A38
CSI2_DN3 CSI2_CLKN3
B26
B38 A26
CSI2_DP3 CSI2_CLKP3
+3VS C31 E13 CSI2_COMP RC73 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
RPC4 D33 CSI2_DN5
1 8 LAN_CLKREQ# A31 CSI2_DP5 EMMC

2 7 W LAN_CLKREQ# B31 CSI2_DN6 AP2

3 6 SSD_PCIE_CLKREQ# A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
4 5 B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
10K_0804_8P4R_5% A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP RC50 1 2 200_0402_1%
EMMC_RCOMP
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@

UC1J SKL_ULT ?
SUSCLK RC95 1 @ 2 1K_0402_5%
C C
CLOCK SIGNALS

D42 DIFFCLK_BIASREF RC1555 1 2 60.4_0402_1%

C42 CLKOUT_PCIE_N0 Cannonlake@
AR10 CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#
CLK_PCIE_SSD# B42
40 CLK_PCIE_SSD# CLK_PCIE_SSD CLKOUT_PCIE_N1 CLK_PCIE_XDP# 1
Optane memory 40 CLK_PCIE_SSD
A42
SSD_PCIE_CLKREQ# AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N
F43
CLK_PCIE_XDP
TC85 @
E43 1 TC87 @
40 SSD_PCIE_CLKREQ# GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
CLK_PCIE_WLAN# D41 BA17 SUSCLK
40 CLK_PCIE_WLAN# SUSCLK 40
PCIE CLK5 WLAN CLK_PCIE_WLAN C41 CLKOUT_PCIE_N2 GPD8/SUSCLK
40 CLK_PCIE_WLAN WLAN_CLKREQ# CLKOUT_PCIE_P2
AT8 E37
40 WLAN_CLKREQ# GPP_B7/SRCCLKREQ2# XTAL24_IN +VCCCLK5
E35
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 DIFFCLK_BIASREF RC72 1 2 2.7K_0402_1%
AT10 CLKOUT_PCIE_P3 XCLK_BIASREF
GPP_B8/SRCCLKREQ3# AM18 RTC_X1
CLK_PCIE_LAN# B40 RTCX1 AM20 RTC_X2
37 CLK_PCIE_LAN# CLK_PCIE_LAN A40 CLKOUT_PCIE_N4 RTCX2
PCIE CLK4 LAN 37 CLK_PCIE_LAN LAN_CLKREQ# AU8 CLKOUT_PCIE_P4 AN18 SRTC_RST#
37 LAN_CLKREQ# GPP_B9/SRCCLKREQ4# SRTCRST# AM16 RTC_RST#
E40 RTCRST#
E38 CLKOUT_PCIE_N5
AU7 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

1
SKYLAKE-U_BGA1356 1 OF 20 CC3
REV = 1 ? VCCRTC 1U_0402_6.3V6K
@
B 2 B
RC33 1 2 20K_0402_1% SRTC_RST#
RTC_RST#
RC34 1 2 20K_0402_1% RC1624 1 @ 2 0_0402_5%
EC_RTC_RST# 44

1
CC6 JCMOS1
1U_0402_6.3V6K SHORT PADS
@

2
2

RTC_X1

RC32 2 1 10M_0402_5% RTC_X2

YC1
1 2

2 32.768KHZ_9PF_X1A0001410002 2

CC4 CC5
7P_0402_50V8J 7P_0402_50V8J
1 1
when single end external clock generator used,
this pin should be grounded

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 CK)

MCP (CSI2,EMMC,CLOCK)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 10 o f 60

5 4 3 2 1
 5 4 3 2 1

SKL_ULT ?
UC1K
SYSTEM POWER MANAGEMENT

AT11
GPP_B12/SLP_S0#
AP15 PM_SLP_S3#_R RC96 1 @ 2 0_0402_5%
2 0_0402_5% PLT_RST#_R GPD4/SLP_S3# PM_SLP_S4#_R PM_SLP_S3# 13,44
RC84 1 AN10 BA16 RC97 1 @ 2 0_0402_5%
32,37,40,44 PLT_RST# SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S4# 44
AY16
PCH_RSMRST#_R SYS_RESET# GPD10/SLP_S5#
D RC85 1 2 0_0402_5% AY17 D
44 EC_RSMRST# RSMRST# AN15 PM_SLP_SUS#_R 1 2 0_0402_5%
PAD @ TC21 RC89 @
1 CPU_PROCPWRGD A68 SLP_SUS# AW 15 PM_SLP_SUS# 44
VCCST_PWRGD_R RC93 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17 Reserve for DS3
VCCST_PWRGD GPD9/SLP_WLAN# AN16
RC139 1 2 0_0402_5% SYS_PWROK_R B6 GPD6/SLP_A#
44 SYS_PWROK 2 0_0402_5% PCH_PWROK_R BA20 SYS_PWROK BA15 PBTN_OUT#_R
RC126 1 RC87 1 @ 2 0_0402_5%
44 PCH_PWROK PCH_DPWROK_R BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT_R PBTN_OUT# 44
DSW _PW ROK GPD1/ACPRESENT AU13 BATLOW#
RC86 1 @ 2 0_0402_5% SUSWARN#_R AR13 GPD0/BATLOW #
44 SUSWARN# AP11 GPP_A13/SUSWARN#/SUSPWRDNACK
RC79 1 @ 2 0_0402_5% SUSACK#_R VCCRTC
44 SUSACK# Reserve for DS3 GPP_A15/SUSACK# AU11 PME# @1 TC89
RC91 1 @ 2 0_0402_5% W AKE# BB15 GPP_A11/PME# AP16 INTVRMEN RC41 2 1 330K_0402_5%
37,40,44 PCIE_WAKE# PCH_LAN_WAKE# AM15 W AKE# INTRUDER#
AW 17 GPD2/LAN_WAKE# AM10
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11
GPD7/RSVD GPP_B2/VRALERT#

1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@

RC88 1 @ 2 0_0402_5% AC_PRESENT_R

44 AC_PRESENT
+3VALW

1
RC74 1 2 10K_0402_5% AC_PRESENT_R D
2 QC8
44 ACIN# G
RC75 1 2 8.2K_0402_5% BATLOW# 2N7002KW _SOT323-3
C C
@
RC76 2 1 1K_0402_5% W AKE# Follow CRB change to 1kohm S

3
RC90 1 2 10K_0402_5% PCH_LAN_WAKE#

+3VALW_PCH +3VALW +VCCST_CPU +VCCSTG

2
RC78 1 @ 2 10K_0402_5% SUSWARN#_R

2
RC137 RC1554
RC136 1K_0402_5% 1K_0402_5%
10K_0402_5% @
+3VS @

1
1
VCCST_PWRGD_R
RC80 1 2 10K_0402_5% SYS_RESET#

3
D

6
D 5 QC6B 2
RC138 1 @ 2 0_0402_5% 2 QC6A G CC140
44 EC_VCCST_PWRGD 2N7002KDW H_SOT363-6
G 2N7002KDWH_SOT363-6 @ 1000P_0201_50V7-K
1 @ S EMC_NS@

4
1000P_0201_50V7-K 1 2 CC1254 PCH_RSMRST#_R CC46 S 1

1
EMC_NS@ 0.01U_0201_25V6-K
Stuff to fix Reset&PWRGD test fail issue EMC_NS@
0.01U_0201_10V6K 1 2 CC104 PCH_PWROK 2

1000P_0201_50V7-K 1 2 CC103 PCH_DPWROK_R

EMC_NS@
B B
47P_0201_25V8-J 1 2 CC101 SYS_PW ROK

0.01U_0201_10V6K 1 2 CC1260 EC_RSMRST#

RC1599 1 2 0_0402_5%

Add to fix Reset&PWRGD test fail issue

PM_SLP_S3# DC4 1 2 @

RPC21 RB751V-40_SOD323-2
1 8 PCH_RSMRST#_R
2 PCH_PWROK
7
3 6 SYS_PW ROK
4 5

10K_0804_8P4R_5%
RC182 1 2 0_0402_5% EC_RSMRST#

PCH_DPWROK_R RC81 1 @ 2 0_0402_5% DPWROK_EC 44

100K_0402_5% 2 1 RC92 PLT_RST#_R Reserve for DS3

100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R

A A
100P_0201_25V8J 1 2 CC1294 PLT_RST#

10/25 SIT Add to fix PLT_RST# glitch issue wei Title

Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2016/08/20 ANAGEMENT)
MCP (SYSTEM PWR MANAGEMENT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 11 o f 60

5 4 3 2 1
 5 4 3 2 1

+VCC_GT
+CPU_CO RE +CPU_CO RE +CPU_CO RE +VCC_GT +VCC_GT
SKL_ULT ? UC1M SKL_ULT
?
UC1L

31000mA
CPU POW ER 1 OF 4 VCORE_VCC_SEN VCCGT_VCC_SEN
RC77 1 2 100_0402_1% RC83 1 2 100_0402_1% +CPU_CO RE CPU POW ER 2 OF 4
32000mA A30 G32 N70
A34 VCC_A30 VCC_G32 G33 A48 VCCGT_N70 N71
A39 VCC_A34 VCC_G33 G35 VCO RE_VSS_SEN RC82 1 2 100_0402_1% VCCGT_VSS_SEN RC98 1 2 100_0402_1% A53 VCCGT_A48 VCCGT_N71 R63
A44 VCC_A39 VCC_G35 G37 A58 VCCGT_A53 VCCGT_R63 R64
AK33 VCC_A44 VCC_G37 G38 A62 VCCGT_A58 VCCGT_R64 R65
AK35 VCC_AK33 VCC_G38 G40 A66 VCCGT_A62 VCCGT_R65 R66
AK37 VCC_AK35 VCC_G40 G42 AA63 VCCGT_A66 VCCGT_R66 R67
AK38 VCC_AK37 VCC_G42 J30 AA64 VCCGT_AA63 VCCGT_R67 R68
AK40 VCC_AK38 VCC_J30 J33 AA66 VCCGT_AA64 VCCGT_R68 R69
AL33 VCC_AK40 VCC_J33 J37 AA67 VCCGT_AA66 VCCGT_R69 R70
AL37 VCC_AL33 VCC_J37 J40 AA69 VCCGT_AA67 VCCGT_R70 R71
D
AL40 VCC_AL37 VCC_J40 K33 AA70 VCCGT_AA69 VCCGT_R71 T62 D
AM32 VCC_AL40 VCC_K33 K35 SVID +VCCST_CPU AA71 VCCGT_AA70 VCCGT_T62 U65
AM33 VCC_AM32 VCC_K35 K37 AC64 VCCGT_AA71 VCCGT_U65 U68
AM35 VCC_AM33 VCC_K37 K38 AC65 VCCGT_AC64 VCCGT_U68 U71
AM37 VCC_AM35 VCC_K38 K40 AC66 VCCGT_AC65 VCCGT_U71 W63
AM38 VCC_AM37 VCC_K40 K42 AC67 VCCGT_AC66 VCCGT_W 63 W64
G30 VCC_AM38 VCC_K42 K43 AC68 VCCGT_AC67 VCCGT_W 64 W65
VCC_G30 VCC_K43 AC69 VCCGT_AC68 VCCGT_W 65 W66
VCORE_VCC_SEN 1 VCCGT_AC69 VCCGT_W 66
@ TC90 1 K32 E32 CC42 AC70 W67
RSVD_K32 VCC_SENSE VCO RE_VSS_SEN VCORE_VCC_SEN 59 VCCGT_AC70 VCCGT_W 67
E33 0.1u_0201_10V6K AC71 W68
VCORE_VSS_SEN 59 VCCGT_AC71 VCCGT_W 68

1
AK32 VSS_SENSE @ J43 W69
RSVD_AK32 VCCGT_J43 VCCGT_W 69

56_0402_5%
CPU_SV ID_ALERT#_R

100_0402_1%

100_0402_1%
B63 2 J45 W70

RC131

RC132
RC1544
AB62 VIDALERT# A63 CPU_SVID_CLK_R J46 VCCGT_J45 VCCGT_W 70 W71
P62 VCCOPC_AB62 VIDSCK D64 CPU_SVID_DAT_R J48 VCCGT_J46 VCCGT_W 71 Y62
V62 VCCOPC_P62 VIDSOUT J50 VCCGT_J48 VCCGT_Y62 +CPU_CO RE

2
VCCOPC_V62 G20 J52 VCCGT_J50
VCCSTG_G20 +VCCSTG VCCGT_J52
H63 @ J53 AK42
VCC_OPC_1P8_H63 J55 VCCGT_J53 VCCGTX_AK42 AK43
G61 J56 VCCGT_J55 VCCGTX_AK43 AK45
VCC_OPC_1P8_G61 RC133 1 2 220_0402_1% CPU_SVID_ALERT#_R J58 VCCGT_J56 VCCGTX_AK45 AK46
59 VR_SVID_ALRT# VCCGT_J58 VCCGTX_AK46 AK48
AC63 J60
AE63 VCCOPC_SENSE K48 VCCGT_J60 VCCGTX_AK48 AK50
VSSOPC_SENSE RC134 1 2 0_0402_5% CPU_SVID_CLK_R K50 VCCGT_K48 VCCGTX_AK50 AK52
59 VR_SVID_CLK VCCGT_K50 VCCGTX_AK52 AK53
AE62 K52
AG62 VCCEOPIO_AE62 K53
VCCGT_K52 VCCGTX_AK53 AK55
VCCEOPIO_AG62 RC1545 1 2 0_0402_5% CPU_SVID_DAT_R K55 VCCGT_K53 VCCGTX_AK55 AK56
59 VR_SVID_DAT VCCGT_K55 VCCGTX_AK56 AK58
AL63 K56
AJ62 VCCEOPIO_SENSE 1, Alert# Route Between CLK and Data K58 VCCGT_K56 VCCGTX_AK58 AK60
VSSEOPIO_SENSE K60 VCCGT_K58 VCCGTX_AK60 AK70
L62 VCCGT_K60 VCCGTX_AK70 AL43
SKYLAKE-U_BGA1356 1 OF 20 L63 VCCGT_L62 VCCGTX_AL43 AL46
REV = 1 ? L64 VCCGT_L63 VCCGTX_AL46 AL50
@ L65 VCCGT_L64 VCCGTX_AL50 AL53
L66 VCCGT_L65 VCCGTX_AL53 AL56
L67 VCCGT_L66 VCCGTX_AL56 AL60
L68 VCCGT_L67 VCCGTX_AL60 AM48
L69 VCCGT_L68 VCCGTX_AM48 AM50
+CPU_CO RE L70 VCCGT_L69 VCCGTX_AM50 AM52
C C
+VCC_GT Backside Cap 8x10uF 0402, SIT update L71 VCCGT_L70 VCCGTX_AM52 AM53
12x10uF 0402, SIT update to 0603 package M62 VCCGT_L71 VCCGTX_AM53 AM56
N63 VCCGT_M62 VCCGTX_AM56 AM58
N64 VCCGT_N63 VCCGTX_AM58 AU58
N66 VCCGT_N64 VCCGTX_AU58 AU63
N67 VCCGT_N66 VCCGTX_AU63 BB57
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCGT_N67 VCCGTX_BB57 BB66
N69
CC1086

CC1085

CC1295

CC1296

CC1080

CC1236

CC1237

CC1093

CC1092

CC1091

CC1089

CC1238

CC1305

CC1097

CC1104

CC1299

CC1119

CC1240

CC1124

CC1125

CC1126

CC1127

CC1128

CC1129

CC1311

CC1312

CC1313
VCCGT_N69 VCCGTX_BB66
VCCGT_VCC_SEN J70 AK62 VCCGTX_SENSE 1 TC133 @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 59 VCCGT_VCC_SEN VCCGT_VSS_SEN J69 VCCGT_SENSE VCCGTX_SENSE VSSGTX_SENSE 1 TC134 @
59 VCCGT_VSS_SEN AL61
VSSGT_SENSE VSSGTX_SENSE

@ @ @ SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

+CPU_CO RE
15x1uF 0201, SIT update to 0402 package +VCC_GT
Backside Cap 12x1uF 0201, SIT update
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1 1 1 1 1 1 1 1 1 1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CC1095

CC1096

CC1098

CC1099

CC1100

CC1101

CC1102

CC1105

CC1108

CC1109

1 1 1 1 1 1 1 1 1

CC1111

CC1114

CC1115

CC1116

CC1118

CC1122

CC1123

CC1241

CC1314
2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2
@ @ @ @ @ @
@ @ @

B B

+CPU_CO RE
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1 1 1 1 1 1 1 1 1 1 1 1
CC1308

CC1298

CC1301

CC1302

CC1303

CC1304

CC1306

CC1307

CC1309

CC1310

CC1297

CC1300

2 2 2 2 2 2 2 2 2 2 2 2

@ @ @ @ @ @ @

SDV Add for U42 wei 02/21

A A

Securiiity Clllassiiifiiicatiiion LC Future Center SecretData Title

Issued Date 2016/12/14 Deciphii ered Date 2017/12/13 MCP (CPU PWR1)
THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIAI L
AND TRADE SECRET INIFORMATIONII ..THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R &
D Siiize Documenttt Number Rev
DEPARTMENT EXCEPT AS AUTHORIZEII D BY LC FUTURE CENTER NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORII WRITTEII N CONSENT OF LC FUTURE CENTER...
Cus t om
EG521 0.. 2

Dattte::: Tuesday,,, Apriiilll 25,,, 2017 Sh eett 12 o ff 60

5 4 3 2 1
 5 4 3 2 1

+VCCIO
3.1A 2x10uF, 4x1uF

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1
+VCCIO

CC1218

CC1230

CC1231

CC1232
CC1152

CC1153

CC1158

CC1159

CC1160

CC1161
?
+1.2V UC1N SKL_ULT
CPU POW ER 3 OF 4 2 2 2 2 2 2 2 2 2 2
2800mA AU23 AK28 3100mA
AU28 VDDQ_AU23 VCCIO_AK28 AK30
AU35 VDDQ_AU28 VCCIO_AK30 AL30 @ @ @ @ @
AU42 VDDQ_AU35 VCCIO_AL30 AL42
+1.2V 2A , 3x22uF, 6x10uF, 4x1uF, SIT update BB23 VDDQ_AU42 VCCIO_AL42 AM28
BB32 VDDQ_BB23 VCCIO_AM28 AM30 +VCCSA
BB41 VDDQ_BB32 VCCIO_AM30 AM42
BB47 VDDQ_BB41 VCCIO_AM42
D VDDQ_BB47 D
BB51 AK23 5100mA +VCCSA
VDDQ_BB51 VCCSA_AK23

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
AK25
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCSA_AK25 G23 4.5A 10x10uF, 7x1uF, SIT update

CC1168

CC1169

CC1171

CC1222

CC1223

CC1243

CC1244
CC1256

CC1257

CC1258

CC1224

CC1225

CC1226

CC1227
AM40 VCCSA_G23 G25
+VDDQ_CPU_CLK VDDQC VCCSA_G25 G27
2 2 2 2 2 2 2 2 2 2 2 2 2 2 A18 VCCSA_G27 G28
+VCCST_CPU VCCST VCCSA_G28

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
J22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD@ CD@ @ @ CD@ @ CD@ @ A22 VCCSA_J22 J23

CC1133

CC1134

CC1135

CC1136

CC1137

CC1251

CC1252

CC1253

CC1139

CC1140

CC1142

CC1145

CC1141

CC1143

CC1144
+VCCSTG VCCSTG_A22 VCCSA_J23 J27

CC1132
AL23 VCCSA_J27 K23
+VCCSFR_OC VCCPLL_OC VCCSA_K23 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
K25
K20 VCCSA_K25 K27
130mA K21 VCCPLL_K20 VCCSA_K27 K28
+VCCPLL_CPU VCCPLL_K21 VCCSA_K28 @
K30 @ @ @ @ CD@ CD@ CD@
VCCSA_K30
AM23 VCCIO_SE NSE 1 TC136 @
VCCIO_SENSE AM22 VSSIO_SE NSE 1 TC137 @
VSSIO_SENSE
H21 VCCSA_V SS_SEN
VSSSA_SENSE H20 VCCSA_V CC_SEN VCCSA_VSS_SEN 59
VCCSA_SENSE VCCSA_VCC_SEN 59

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

+VCCSTG +VCCST_CPU
+VDDQ_CPU_CLK
120mA
RC1497 1 2 0_0402_5% +VCCIO RC103 1 2 0_0402_5%
+1.2V

1U_0402_6.3V6K
1
RC1604 1 @ 2 0_0402_5%
1U_0201_6.3V6-M

10U_0402_6.3V6M

CC86
1 1 +VCCST_CPU

1U_0402_6.3V6K
+VCCSA
CC1228
CC1229

1
+1.0VALW +VCCST_CPU

CC87
C C
2
2 2 Reserved for VCCST/VCCSTG/VCCPLL
@ power optimized 2
RC1605 1 @ 2 0_0402_5%
VCCSA_VCC_SEN RC101 1 2 100_0402_1%
Reserved for VCCST/VCCSTG/VCCPLL power
+VCCSFR_OC VCCSA_VSS_SEN RC102 1 2 100_0402_1%
optimized

+VCCPLL_CPU
RC104 1 2 0_0402_5%

120mA
1U_0201_6.3V6-M

1
RC105 1 2 0_0402_5%
CC85

+VCCST_CPU

1U_0402_6.3V6K
0.1u_0201_10V6K
2 1 1

CC84
CC1249
2 2

+VCCIO
+1.0VALW

10U_0603_6.3V6M
1 2 0_0402_5% VCCIO_EN

10U_0603_6.3V6M
RC128

22U_0603_6.3V6-M

22U_0603_6.3V6-M
44 EC_VCCIO_EN 1 1 1 1

C1102
CC1250
CC72
CC71
B B
DC1 1 2 @
11,44 PM_SLP_S3#
1 0.01U_0201_6.3V7-K 2 2 2 2
RB751V-40_SOD323-2
CC77 UC4 @
@ 1 14
2 2 IN1_1 OUT1_2 13
@ IN1_2 OUT1_1
VCCIO_EN 3 12 CC1293 1 2 1000P_0201_50V7-K
EN1 CT1
+5VALW 4 11
VBIAS GND
VCCST_EN 5 10 CC1292 1 2 1000P_0201_50V7-K
+1.0VALW EN2 CT2 +VCCST_CPU
6 9
7 IN2_1 OUT2_2 8
IN2_2 OUT2_1

10U_0603_6.3V6M
VCCST_EN 1
1 2 0_0402_5% 15
10U_0603_6.3V6M

RC142

CC80
44 EC_VCCST_EN GPAD
1
G5016KD1U_TDFN14_2X3
CC79

1 0.01U_0201_6.3V7-K 2
CC81 @
2
2
@
Follow DG470 change to Dual Switch 8/24 wei

A A

Securiiity Clllassiiifiiicatiiion LC Future Center SecretData Title

Issued Date 2015/08/20 Deciphii ered Date 2016/08/20 MCP (CPU PWR2)
THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIAI L
AND TRADE SECRET INIFORMATIONII ..THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R &
D Siiize Documenttt Number Rev
DEPARTMENT EXCEPT AS AUTHORIZEII D BY LC FUTURE CENTER NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORII WRITTEII N CONSENT OF LC FUTURE CENTER...
Cus t om
EG521 0.. 2

Dattte::: Tuesday,,, Apriiilll 25,,, 2017 Sh eett 13 o ff60

5 4 3 2 1
 5 4 3 2 1

+1.0VALW RC1503 1 2 0_0603_5% +VCCAMPHY

+1.0VALW RC1504 1 2 0_0402_5%

+VCCAPLL_1P0 +3VALW_PCH +VCCPGPPG

+VCCHDA

RC1622 1 2 0_0402_5%
D D

+3VALW_PCH RC1586 1 2 0_0402_5%

+1.0VALW RC1620 1 @ 2 0_0402_5% VCCMPHYON_1P0_L1

1U_0402_6.3V6K
1

CC144
2

+3VALW_PCH

0.696A
+1.0VALW
Near AB19

1U_0402_6.3V6K
1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CC141
1 1 1 1 1
22mA 2.574A +VCCPGPPG

CC156

CC164

CC172

CC173

CC174
+1.0VALW +1.0VALW ?

22U_0603_6.3V6-M
1 1 SKL_ULT

1U_0402_6.3V6K
2 UC1O

CC158
1.5A @ 2 2 2 2 2

CC153
+1.0VALW CPU POWER 4 OF 4
@ @ @ @
+VCCDSW _1P0

1U_0402_6.3V6K
2 2 AB19 1
AB20 VCCPRIM_1P0_AB19

1U_0402_6.3V6K
@ AK15 20mA Near Y15

CC175
1 VCCPGPPA +3VALW_PCH
P18 VCCPRIM_1P0_AB20 AG15 4mA
1U_0201_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

CC145
1 1 1 VCCPRIM_1P0_P18 VCCPGPPB

1U_0402_6.3V6K
Near AF18 Y16 6mA
C2084

CC148

CC147

VCCPGPPC 1
AF18 Y15 8mA 2

CC176
2 AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16 6mA @
VCCPGPPE +1.8VALW
C 2 2 2 V20 VCCPRIM_CORE_AF19 AF16 161mA C
VCCPGPPF +1.8VALW
V21 VCCPRIM_CORE_V20 AD15 61mA

1U_0402_6.3V6K
PCH Internal VRM 2
1
VCCPRIM_CORE_V21 VCCPGPPG @

CC142
@ @ +3VALW_PCH
AL1 V19
DCPDSW _1P0 VCCPRIM_3P3_V19

1U_0402_6.3V6K
Near N15

0.1u_0201_10V6K
1 1
K17 T1 2

CC143
CC149
+1.0VALW
88mA VCCMPHYON_1P0_L1 L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1
+VCCAMPHY VCCMPHYAON_1P0_L1 AA1 6mA
VCCATS_1P8
1U_0402_6.3V6K

2 2
22U_0603_6.3V6-M

1 1 N15
VCCMPHYGT_1P0_N15 AK17 1mA
C1096

N16
CC151

VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
N17
VCCMPHYGT_1P0_N17 1mA
P15 AK19 VCCRTC
2 2 VCCMPHYGT_1P0_P15 VCCRTC_AK19
Near K15 P16 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14

1U_0402_6.3V6K
0.1u_0201_10V6K
@ 1 1
K15 BB10 VCCRTCEXT

CC1242
CC146
VCCAMPHYPLL_1P0_K15 DCPRTC
L15
VCCAMPHYPLL_1P0_L15 35mA
A14 +1.0VALW
VCCCLK1 2 2

0.1u_0201_10V6K
22mA V15
+VCCAPLL_1P0 VCCAPLL_1P0 1
29mA 0_0603_5%1 2RC1587 +1.0VALW

CC55
K19
VCCCLK2
1U_0402_6.3V6K
0.1u_0201_10V6K

1 1 AB17
+1.0VALW
Y18 VCCPRIM_1P0_AB17

1U_0402_6.3V6K
L21 24mA
C1097

CC154

VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW 1 1 2

22U_0603_6.3V6-M
C1098
CC56
+VCCHDA
0.118A AD17 N20 33mA
+3VALW VCCCLK4 +VCCCLK4
2 2 AD18 VCCDSW _3P3_AD17
0.1u_0201_10V6K

1
AJ17 VCCDSW _3P3_AD18 L19 4mA 2 2
CC165

VCCDSW_3P3_AJ17 VCCCLK5 +VCCCLK5

@
68mA AJ19 A10 10mA
2 VCCHDA VCCCLK6 +1.0VALW

1U_0402_6.3V6K
11mA AJ16 AN11
+3VALW_PCH VCCSPI GPP_B0/CORE_VID0 1

CC57
AN13
0.642A GPP_B1/CORE_VID1
+1.0VALW AF20
VCCSRAM_1P0_AF20
AF21
VCCSRAM_1P0_AF21
1U_0402_6.3V6K

Near AF20 T19 2

1 VCCSRAM_1P0_T19
CC159

T20
VCCSRAM_1P0_T20
75mA AJ21
2 +3VALW_PCH VCCPRIM_3P3_AJ21
1U_0402_6.3V6K

CD@ 1 AK20
+1.0VALW VCCPRIM_1P0_AK20
CC171

33mA N18 0_0603_5%1 2RC1588

B +1.0VALW VCCAPLLEBB +VCCCLK4 +1.0VALW B

22U_0603_6.3V6-M
2
1
1U_0402_6.3V6K

SKYLAKE-U_BGA1356 1 OF 20

C1099
1
CD@ REV = 1
CC169

?
@
2
2 @

0_0603_5%1 2RC1589 +1.0VALW

+VCCCLK5
Near A18

22U_0603_6.3V6-M
1

C1100
2
@

A A

Securityii Clasll sifi ici ationii LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciiiphered Date 2016/08/20 MCP (PCH PWR)
THISII SHEET OF ENGINEEII RINGII DRAWINGII ISITHE PROPRIEII TARY PROPERTY OF L C F UTURE CENTER... AND CONTAINSII CONFIDEII NTIALI
AND TRADE SECRET INFIIORMATIOII N... THISII SHEET MAY NOT BE TRANSF ERED F ROM THE CUSTODY OF THE COMPETENT DIVISIOIIIIIIN OF R&D Siiize Documenttt Number Rev
DEPARTMENT EXCEPT AS AUTHORIZII ED BY L C F UTURE CENTER NEITHEII R THISII SHEET NOR THE INFIIORMATIOII N ITICONTAINSII
MAY BE USED BY OR DISCLOII SED TO ANY THIRDII PARTY WITHOII UT PRIOII R WRITTEII N CONSENT OF L C F UTURE CENTER...
Custttom
EG521 0.. 2

Dattte::: Tuesday,,, Apriiilll 25,,, 2 0 1 7 Sheettt 14 o ff 60

5 4 3 2 1
 5 4 3 2 1

UCSK1LQ_ULT?
USCK1LP_ULT?
D GND 2 OF 3 D
GND 1 OF 3
AT63 BA49
VSS_AT63 VSS_BA49
A5 AL65 AT68 BA53
VSS_A5 VSS_AL65 VSS_AT68 VSS_BA53
A67 AL66 AT71 BA57
VSS_A67 VSS_AL66 VSS_AT71 VSS_BA57
A70 AM13 AU10 BA6
AA2 VSS_A70 VSS_AM13 AM21 AU15 VSS_AU10 VSS_BA6 BA62
VSS_AA2 VSS_AM21 VSS_AU15 VSS_BA62
AA4 AM25 AU20 BA66
VSS_AA4 VSS_AM25 VSS_AU20 VSS_BA66
AA65 AM27 AU32 BA71
VSS_AA65 VSS_AM27 VSS_AU32 VSS_BA71
AA68 AM43 AU38 BB18
VSS_AA68 VSS_AM43 VSS_AU38 VSS_BB18
AB15 AM45 AV1 BB26
AB16 VSS_AB15 VSS_AM45 AM46 AV68 VSS_AV1 VSS_BB26 BB30
VSS_AB16 VSS_AM46 VSS_AV68 VSS_BB30
AB18 AM55 AV69 BB34
VSS_AB18 VSS_AM55 VSS_AV69 VSS_BB34
AB21 AM60 AV70 BB38 ?
VSS_AB21 VSS_AM60 VSS_AV70 VSS_BB38 SKL_ULT
UC1R
AB8 AM61 AV71 BB43
VSS_AB8 VSS_AM61 VSS_AV71 VSS_BB43
AD13 AM68 AW 10 BB55
AD16 VSS_AD13 VSS_AM68 AM71 AW 12 VSS_AW10 VSS_BB55 BB6 GND 3 OF 3
VSS_AD16 VSS_AM71 VSS_AW12 VSS_BB6
AD19 AM8 AW 14 BB60 F8 L18
VSS_AD19 VSS_AM8 VSS_AW14 VSS_BB60 VSS_F8 VSS_L18
AD20 AN20 AW 16 BB64 G10 L2
VSS_AD20 VSS_AN20 VSS_AW16 VSS_BB64 VSS_G10 VSS_L2
AD21 AN23 AW 18 BB67 G22 L20
VSS_AD21 VSS_AN23 VSS_AW18 VSS_BB67 VSS_G22 VSS_L20
AD62 AN28 AW 21 BB70 G43 L4
AD8 VSS_AD62 VSS_AN28 AN30 AW 23 VSS_AW21 VSS_BB70 C1 G45 VSS_G43 VSS_L4 L8
VSS_AD8 VSS_AN30 VSS_AW23 VSS_C1 VSS_G45 VSS_L8
AE64 AN32 AW 26 C25 G48 N10
VSS_AE64 VSS_AN32 VSS_AW26 VSS_C25 VSS_G48 VSS_N10
AE65 AN33 AW 28 C5 G5 N13
VSS_AE65 VSS_AN33 VSS_AW28 VSS_C5 VSS_G5 VSS_N13
AE66 AN35 AW 30 D10 G52 N19
VSS_AE66 VSS_AN35 VSS_AW30 VSS_D10 VSS_G52 VSS_N19
AE67 AN37 AW 32 D11 G55 N21
AE68 VSS_AE67 VSS_AN37 AN38 AW 34 VSS_AW32 VSS_D11 D14 G58 VSS_G55 VSS_N21 N6
VSS_AE68 VSS_AN38 VSS_AW34 VSS_D14 VSS_G58 VSS_N6
AE69 AN40 AW 36 D18 G6 N65
VSS_AE69 VSS_AN40 VSS_AW36 VSS_D18 VSS_G6 VSS_N65
AF1 AN42 AW 38 D22 G60 N68
VSS_AF1 VSS_AN42 VSS_AW38 VSS_D22 VSS_G60 VSS_N68
AF10 AN58 AW 41 D25 G63 P17
VSS_AF10 VSS_AN58 VSS_AW41 VSS_D25 VSS_G63 VSS_P17
AF15 AN63 AW 43 D26 G66 P19
AF17 VSS_AF15 VSS_AN63 AP10 AW 45 VSS_AW43 VSS_D26 D30 H15 VSS_G66 VSS_P19 P20
C VSS_AF17 VSS_AP10 VSS_AW45 VSS_D30 VSS_H15 VSS_P20 C
AF2 AP18 AW 47 D34 H18 P21
VSS_AF2 VSS_AP18 VSS_AW47 VSS_D34 VSS_H18 VSS_P21
AF4 AP20 AW 49 D39 H71 R13
VSS_AF4 VSS_AP20 VSS_AW49 VSS_D39 VSS_H71 VSS_R13
AF63 AP23 AW 51 D44 J11 R6
VSS_AF63 VSS_AP23 VSS_AW51 VSS_D44 VSS_J11 VSS_R6
AG16 AP28 AW 53 D45 J13 T15
AG17 VSS_AG16 VSS_AP28 AP32 AW 55 VSS_AW53 VSS_D45 D47 J25 VSS_J13 VSS_T15 T17
VSS_AG17 VSS_AP32 VSS_AW55 VSS_D47 VSS_J25 VSS_T17
AG18 AP35 AW 57 D48 J28 T18
VSS_AG18 VSS_AP35 VSS_AW57 VSS_D48 VSS_J28 VSS_T18
AG19 AP38 AW 6 D53 J32 T2
VSS_AG19 VSS_AP38 VSS_AW 6 VSS_D53 VSS_J32 VSS_T2
AG20 AP42 AW 60 D58 J35 T21
VSS_AG20 VSS_AP42 VSS_AW60 VSS_D58 VSS_J35 VSS_T21
AG21 AP58 AW 62 D6 J38 T4
AG71 VSS_AG21 VSS_AP58 AP63 AW 64 VSS_AW62 VSS_D6 D62 J42 VSS_J38 VSS_T4 U10
VSS_AG71 VSS_AP63 VSS_AW64 VSS_D62 VSS_J42 VSS_U10
AH13 AP68 AW 66 D66 J8 U63
VSS_AH13 VSS_AP68 VSS_AW66 VSS_D66 VSS_J8 VSS_U63
AH6 AP70 AW 8 D69 K16 U64
VSS_AH6 VSS_AP70 VSS_AW 8 VSS_D69 VSS_K16 VSS_U64
AH63 AR11 AY66 E11 K18 U66
VSS_AH63 VSS_AR11 VSS_AY66 VSS_E11 VSS_K18 VSS_U66
AH64 AR15 B10 E15 K22 U67
AH67 VSS_AH64 VSS_AR15 AR16 B14 VSS_B10 VSS_E15 E18 K61 VSS_K22 VSS_U67 U69
VSS_AH67 VSS_AR16 VSS_B14 VSS_E18 VSS_K61 VSS_U69
AJ15 AR20 B18 E21 K63 U70
VSS_AJ15 VSS_AR20 VSS_B18 VSS_E21 VSS_K63 VSS_U70
AJ18 AR23 B22 E46 K64 V16
VSS_AJ18 VSS_AR23 VSS_B22 VSS_E46 VSS_K64 VSS_V16
AJ20 AR28 B30 E50 K65 V17
VSS_AJ20 VSS_AR28 VSS_B30 VSS_E50 VSS_K65 VSS_V17
AJ4 AR35 B34 E53 K66 V18
AK11 VSS_AJ4 VSS_AR35 AR42 B39 VSS_B34 VSS_E53 E56 K67 VSS_K66 VSS_V18 W 13
VSS_AK11 VSS_AR42 VSS_B39 VSS_E56 VSS_K67 VSS_W13
AK16 AR43 B44 E6 K68 W6
VSS_AK16 VSS_AR43 VSS_B44 VSS_E6 VSS_K68 VSS_W 6
AK18 AR45 B48 E65 K70 W9
VSS_AK18 VSS_AR45 VSS_B48 VSS_E65 VSS_K70 VSS_W 9
AK21 AR46 B53 E71 K71 Y17
VSS_AK21 VSS_AR46 VSS_B53 VSS_E71 VSS_K71 VSS_Y17
AK22 AR48 B58 F1 L11 Y19
AK27 VSS_AK22 VSS_AR48 AR5 B62 VSS_B58 VSS_F1 F13 L16 VSS_L11 VSS_Y19 Y20
VSS_AK27 VSS_AR5 VSS_B62 VSS_F13 VSS_L16 VSS_Y20
AK63 AR50 B66 F2 L17 Y21
VSS_AK63 VSS_AR50 VSS_B66 VSS_F2 VSS_L17 VSS_Y21
AK68 AR52 B71 F22
VSS_AK68 VSS_AR52 VSS_B71 VSS_F22
AK69 AR53 BA1 F23
VSS_AK69 VSS_AR53 VSS_BA1 VSS_F23
AK8 AR55 BA10 F27
AL2 VSS_AK8 VSS_AR55 AR58 BA14 VSS_BA10 VSS_F27 F28
VSS_AL2 VSS_AR58 VSS_BA14 VSS_F28 1 OF 20
AL28 AR63 BA18 F32 SKYLAKE-U_BGA1356
VSS_AL28 VSS_AR63 VSS_BA18 VSS_F32
AL32 AR8 BA2 F33 REV = 1 ?
B VSS_AL32 VSS_AR8 VSS_BA2 VSS_F33 B
AL35 AT2 BA23 F35 @
VSS_AL35 VSS_AT2 VSS_BA23 VSS_F35
AL38 AT20 BA28 F37
AL4 VSS_AL38 VSS_AT20 AT23 BA32 VSS_BA28 VSS_F37 F38
VSS_AL4 VSS_AT23 VSS_BA32 VSS_F38
AL45 AT28 BA36 F4
VSS_AL45 VSS_AT28 VSS_BA36 VSS_F4
AL48 AT35 F68 F40
VSS_AL48 VSS_AT35 VSS_F68 VSS_F40
AL52 AT4 BA45 F42
VSS_AL52 VSS_AT4 VSS_BA45 VSS_F42
AL55 AT42 BA41
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA41
VSS_AL58 VSS_AT56
AL64 AT58
VSS_AL64 VSS_AT58
1 OF 20
SKYLAKE-U_BGA1356
1 OF 20
SKYLAKE-U_BGA1356 REV = 1 ?
REV = 1 ? @
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (VSS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 15 o f 60

5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1S
+VCCST_CPU
UC1T SKL_ULT ?
RESERVED SIGNALS-1

CPU_CFG0 E68 BB68 S PA R E

D 1 CPU_CFG1 CFG[0] RSVD_TP_BB68 +1.8VALW D
PAD @ TC142 B67 BB69
CFG[1]

1
PAD @ TC143 1 CPU_CFG2 D65 RSVD_TP_BB69 AW 69 F6
PAD @ TC144 1 XDP_CPU_CFG3 D67 CFG[2] AK13 AW 68 RSVD_AW 69 RSVD_F6 E3 XTAL24_IN RC1619
RSVD_AW 68 RSVD_E3
2

CPU_CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 AU56 C11 150_0402_5%

PAD @ TC146 1 CPU_CFG5 CFG[4] RSVD_TP_AK12 AW 48 RSVD_AU56 RSVD_C11 B11
RC1618 C68 @
PAD @ TC147 1 CPU_CFG6 D68 CFG[5] BB2 Cannonlake@ XTAL24_OUT C7 RSVD_AW 48 RSVD_B11 A11
1K_0402_5%

2
1 CPU_CFG7 1 0_0402_5% RSVD_U12 U12 RSVD_C7 RSVD_A11
@ PAD @ TC148 C67 CFG[6] RSVD_BB2 BA3 RC1582 2 D12
RSVD_U12 RSVD_D12
2

PAD @ TC153 1 CPU_CFG8 F71 RC1583 2 1 0_0402_5% RSVD_U11 U11 C12

CFG[7] RSVD_BA3
1

PAD @ TC150 1 CPU_CFG9 H11 RSVD_U11 RSVD_C12 F52 RSVD_F52

RC106 G69 CFG[8] Cannonlake@
PAD @ TC151 1 CPU_CFG10 F70 AU5 RSVD_H11 RSVD_F52
1K_0402_5% CFG[9]
PAD @ TC152 1 CPU_CFG11 G68 AT5
CFG[10] TP5
PAD @ TC157 1 CPU_CFG12 H70 CFG[11] TP6 1 OF 20
1

PAD @ TC154 1 CPU_CFG13 G71 SKYLAKE-U_BGA1356

CPU_CFG14 CFG[12]
PAD @ TC155 1 H69 CFG[13] D5 REV = 1 ?
PAD @ TC156 1 CPU_CFG15 G70 D4 @
CFG[14] RSVD_D5
CFG[15] RSVD_D4 B2
PAD @ TC159 1 CPU_CFG16 E63 C2
RSVD_B2
PAD @ TC158 1 CPU_CFG17 F63 CFG[16] RSVD_C2
B3
CPU_CFG18 CFG[17]
PAD @ TC161 1 E66 A3 RC71 2 1 1M_0402_5%
CPU_CFG19 RSVD_B3
PAD @ TC160 1 F66 CFG[18] RSVD_A3
AW 1 YC2
C CFG_RCOMP E60 CFG[19] C
CFG_RCOMP RSVD_AW 1 2 0_0201_5% XTAL24_OUT
E1 2 3 RC240 1
PAD @ TC166 1 XDP_ITP_PMODE E8 RSVD_E1 E2 GND1 OSC2
2

ITP_PMODE RSVD_E2 XTAL24_IN RC241 1 2 0_0201_5% 1 4

RC162 AY2 OSC1 GND2
BA4
49.9_0402_1% AY1 RSVD_AY2 RSVD_BA4
BB4
RSVD_AY1 RSVD_BB4 1 24MHZ_6PF_7V24000032 1
D1 A4 CC12 CC11
1

D3 RSVD_D1 RSVD_A4 3.3P_0402_50V8-C 2.7P_0402_50V9-B

C4
RSVD_D3 RSVD_C4
K46 BB5 2 2
RSVD_K46 TP4
K45
RSVD_K45 A69
AL25 RSVD_A69 B69 need to use 38.4MHz (30ohm) for Cannonlake-u
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RSVD_AY3 need to check with Intel
C71 RSVD_AY3

2
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70 RC107
F60 RSVD_C70 0_0402_5%
RSVD_F60 C54
A52 RSVD_C54 D54

1
B RSVD_A52 RSVD_D54 B
BA70 AY4
RSVD_TP_BA70 TP1
BA68 BB3
RSVD_TP_BA68 TP2
J71 AY71 VSS_AY71 need to check with Intel
RSVD_J71 VSS_AY71 1 TC167 @ PAD
J68 AR56
RSVD_J68 ZVM#

2
PAD @ TC169 1 F65 AW 71 1 TC177 @PAD
1 VSS_F65 RSVD_TP_AW 71 1 RC108
PAD @ TC170 G65 AW 70 TC178 @PAD
VSS_G65 RSVD_TP_AW 70 0_0402_5%
F61 AP56 1 TC168 @PAD
E61 RSVD_F61 MSM# C64 PROC_SELECT# 1 2 +VCCST_CPU

1
RSVD_E61 PROC_SELECT# 100K_0402_5% Cannonlake@ R22

1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
Default
Pin Name Strap Description Configuration Value

A A
CFG[4] Display Port — 1 = eDP Disabled 1
Presence strap — 0 = eDP Enabled * Security Classification LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CFG,RESERVED)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 16 o f 60

5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[0..63]
DDRA_DQ[0..63] 5
DDRA_DQS#[0..7]
UD1 @ UD2 @
DDRA_DQS#[0..7] 5
DDRA_MA0 DDRA_DQ2 DDRA_MA0 DDRA_DQ18 +1.2V DDRA_DQS[0..7]
P3 G2 P3 G2
DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ3 DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ19 DDRA_DQS[0..7] 5
DDRA_MA2 A1 DQ1 DDRA_DQ6 DDRA_MA2 A1 DQ1 DDRA_DQ22 DDRA_MA[0..13]
R3 H3 R3 H3
DDRA_MA3 N7 A2 DQ2 DDRA_DQ1 DDRA_MA3 N7 A2 DQ2 DDRA_DQ21 DDRA_MA[0..13] 5
H7 H7
DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ7 DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ23
DDRA_MA5 DQ4 DDRA_DQ0 DDRA_MA5 DQ4 DDRA_DQ17 1

1
P8 A4 H8 P8 A4 H8 MD@ MD@ +0.6VS
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ4 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ16
DDRA_MA7 A6 DDRA_MA7 A6 CD119 RD45
R8 DQ6 J7 DDRA_DQ5 R8 DQ6 J7 DDRA_DQ20
DDRA_MA8 A7 DDRA_MA8 A7 0.1u_0201_10V6K 2 1.8K_0402_1% DDRA_CLK0# RD49 1 MD@ 2 36_0402_1%
R2 DQ7 A3 DDRA_DQ11 R2 DQ7 A3 DDRA_DQ30
DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ8 DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ28 DDRA_CLK0 2 36_0402_1%
RD50 1 MD@
DDRA_MA10 DDRA_DQ14 DDRA_MA10 DDRA_DQ26

2
M3 A9 DQ9 C3 M3 A9 DQ9 C3
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ13 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ25 DDRA_CS0# 2 34.8_0402_1%
RD51 1 MD@
DDRA_MA12 M7 A11 DQ11 DDRA_DQ15 DDRA_MA12 M7 A11 DQ11 DDRA_DQ31 +VREF_CA_MD DDRA_ODT0 RD52 1 MD@ 2 34.8_0402_1%
C2 C2 RD46 1 2 MD@
DDRA_MA13 T8 A12/BC_N DQ12 DDRA_DQ12 DDRA_MA13 T8 A12/BC_N DQ12 DDRA_DQ24 5 DDR_SA_VREFCA
C8 C8 2.7_0402_1%
A13 DQ13 D3 DDRA_DQ10 A13 DQ13 D3 DDRA_DQ27 DDRA_CKE0 2 34.8_0402_1%
1 RD53 1 MD@
DDRA_MA14_WE# DQ14 DDRA_DQ9 DDRA_MA14_WE# L2 DQ14 DDRA_DQ29

1
D L2 D7 D7 MD@ D
5 DDRA_MA14_WE# DDRA_MA15_CAS# M8 WE_N/A14 DQ15 DDRA_MA15_CAS# M8 WE_N/A14 DQ15 1 DDRA_MA0 2
RD47 MD@ RD54 1 MD@ 34.8_0402_1%
5 DDRA_MA15_CAS# DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V CD111 DDRA_MA1
MD@ 1.8K_0402_1% CD112 RD55 1 MD@ 2 34.8_0402_1%
5 DDRA_MA16_RAS# RAS_N/A16 RAS_N/A16 0.022U_0201_6.3V6-K 2 DDRA_MA2 2
D1 D1 RD56 1 MD@ 34.8_0402_1%
DDRA_CLK0# K8 VDD1 J1 DDRA_CLK0# K8 VDD1 J1 2 0.1u_0201_10V6K DDRA_MA3
RD57 1 MD@
2 34.8_0402_1%
5 DDRA_CLK0#

2
1
DDRA_CLK0 K7 CK_C VDD2 L1 DDRA_CLK0 K7 CK_C VDD2 L1
5 DDRA_CLK0 CK_T VDD3 R1 CK_T VDD3 R1 DDRA_MA4
RD48 RD58 1 MD@ 2 34.8_0402_1%
DDRA_CKE0 K2 VDD4 B3 DDRA_CKE0 K2 VDD4 B3 DDRA_MA5 34.8_0402_1%
5 DDRA_CKE0 24.9_0402_1% MD@ RD59 1 MD@ 2
CKE VDD5 G7 CKE VDD5 G7 DDRA_MA6 2
RD60 1 MD@ 34.8_0402_1%
DDRA_DQS#0 F3 VDD6 B9 DDRA_DQS#2 F3 VDD6 B9 DDRA_MA7 2 34.8_0402_1%
RD61 1 MD@

2
DDRA_DQS0 G3 LDQS_C VDD7 J9
DDRA_DQS2 G3 LDQS_C VDD7 J9
DDRA_DQS#1 A7 LDQS_T DDRA_DQS#3 A7 LDQS_T DDRA_MA8 2 34.8_0402_1%
VDD8 VDD8 RD62 1 MD@
+1.2V DDRA_DQS1 B7 UDQS_C VDD9 T9L9 +1.2V DDRA_DQS3 B7 UDQS_C VDD9 T9L9 DDRA_MA9 RD63 1 MD@ 2 34.8_0402_1%
UDQS_T VDD10 UDQS_T VDD10 DDRA_MA10 2
RD64 1 MD@ 34.8_0402_1%
DDRA_MA11
RD65 1 @ 2 0_0402_5% DDRA_DM1 E2 A1 RD66 1 @ 2 0_0402_5% DDRA_DM3 E2 A1 RD67 1 MD@
2 34.8_0402_1%
RD68 1 @ 2 0_0402_5% DDRA_DM0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD69 1 @ 2 0_0402_5% DDRA_DM2 E7 NF/UDM_N/UDBI_N VDDQ1 C1
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRA_MA12 RD70 1 MD@ 2 34.8_0402_1%
DDRA_BS0# N2 VDDQ3 F2 DDRA_BS0# N2 VDDQ3 F2 DDRA_MA13 RD71 1 MD@ 34.8_0402_1%
5 DDRA_BS0# DDRA_MA14_WE# RD72 1 MD@ 2
DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_BS1# N8 BA0 VDDQ4 J2 2 34.8_0402_1%
5 DDRA_BS1# BA1 VDDQ5 F8 BA1 VDDQ5 F8 DDRA_MA15_CAS#RD73 1 MD@
DDRA_ACT# DDRA_ACT# 2 34.8_0402_1%
L3 VDDQ6 J8 L3 VDDQ6 J8
5 DDRA_ACT# DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_CS0# L7 ACT_N VDDQ7 A9
5 DDRA_CS0# DDRA_ALERT# P9 CS_N DDRA_ALERT# P9 CS_N DDRA_MA16_RAS#RD74 1 MD@
VDDQ8 D9 VDDQ8 D9 DDRA_BG0 2 34.8_0402_1%
5 DDRA_ALERT# ALERT_N VDDQ9 G9 +2.5V_DDR ALERT_N VDDQ9 G9 +2.5V_DDR RD75 1 MD@ 2
DDRA_BG0 VDDQ10 DDRA_BG0 VDDQ10 DDRA_BS0# 2 34.8_0402_1%
M2 BG0 M2 BG0 RD76 1 MD@ 34.8_0402_1%
5 DDRA_BG0 DDRA_BS1#
B1 B1 RD77 1 MD@ 2 34.8_0402_1%
DDRA_ODT0 K3 ODT VPP1 R9 DDRA_ODT0 K3 ODT VPP1 R9
5 DDRA_ODT0 VPP2 VPP2 DDRA_ACT# RD78 1 MD@ 2 34.8_0402_1%
DDRA_PAR T3 PAR M1 +VREF_CA_MD DDRA_PAR T3 PAR M1 +VREF_CA_MD DDRA_PAR RD79 1 MD@ 2 34.8_0402_1%

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
5 DDRA_PAR VREFCA VREFCA
TEN_UD1 N9 E1 1 1 TEN_UD2 N9 E1 1 1
RD94 1 MD@ 2 10K_0402_5% TEN VSS1 K1 CD@ RD95 1 MD@ 2 10K_0402_5% TEN VSS1 K1 MD@ MD@

0.1u_0201_10V6K

0.1u_0201_10V6K
MD@

.047U_0201_6.3V6K

.047U_0201_6.3V6K
CPU_DRAMRST# VSS2 1 1 CPU_DRAMRST# P1 VSS2 1 1
P1 N1 MD@ MD@ RESET_N N1 MD@ MD@
6,18 CPU_DRAMRST# RESET_N VSS3 T1 2 2 VSS3 T1 2 2
VSS4 B2 VSS4 B2

CD123

CD125
@ F1 @ F1

CD121

CD124
0.1u_0201_10V6K

0.1u_0201_10V6K
H1 VSSQ1 VSS5 G8 2 2 H1 VSSQ1 VSS5 G8 2 2
1 1
A2 VSSQ2 VSS6 E9 A2 VSSQ2 VSS6 E9 +1.2V

CD113

CD120

CD114

CD122
D2 VSSQ3 VSS7 K9 D2 VSSQ3 VSS7 K9
VSS8 M9 E3 VSSQ4 VSS8 M9
E3 VSSQ4
2 VSS9 2 A8 VSSQ5 VSS9 DDRA_ALERT# RD86 1 MD@ 2 49.9_0402_1%
A8 VSSQ5
CD47

CD48
D8 VSSQ6 T7 D8 VSSQ6 T7
NC NC
E8 VSSQ7 E8 VSSQ7
VSSQ8 VSSQ8
C9 VSSQ9
C9
H9 VSSQ9 H9
VSSQ10 VSSQ10
C F9 F9 C
ZQ ZQ
1

1
MD@ RD39 MT40A512M16HA083EA_FBGA96 RD40 MT40A512M16HA083EA_FBGA96
240_0402_1% MD@ 240_0402_1%
2

2
+1.2V (1uF_0402_6.3V) *16
Place 4 near each DRAM

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
UD3 @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
UD4 @ MD@ MD@ MD@ CD@ CD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@
DDRA_MA0 P3 G2 DDRA_DQ47
DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ41 DDRA_MA0 P3 G2 DDRA_DQ59
DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ43 DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ60 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2
DDRA_MA3 N7 A2 DQ2 DDRA_DQ40 DDRA_MA2 R3 A1 DQ1 DDRA_DQ63

CD126

CD127

CD130

CD134

CD135
H7 H3

CD128

CD129

CD131

CD132

CD133

CD136

CD137

CD138

CD139

CD140

CD141
DDRA_MA4 N3 A3 DQ3 DDRA_DQ46 DDRA_MA3 N7 A2 DQ2 DDRA_DQ56
H2 H7
DDRA_MA5 P8 A4 DQ4 DDRA_DQ44 DDRA_MA4 N3 A3 DQ3 DDRA_DQ62
H8 H2 CD@ CD@ CD@ CD@
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ42 DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ61
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ45 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ58
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ34 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ57
DDRA_MA9 R7 A8 DQ8 DDRA_DQ37 DDRA_MA8 R2 A7 DQ7 DDRA_DQ54
B8 A3
DDRA_MA10 M3 A9 DQ9 DDRA_DQ35 DDRA_MA9 R7 A8 DQ8 DDRA_DQ53
DDRA_MA11 DQ10 C3 DDRA_DQ32 DDRA_MA10 DQ9 B8 DDRA_DQ51
T2 A10/AP C7 M3 A9 C3
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ39 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ49 +1.2V (1OuF_0603_6.3V) *5 +1.2V
DDRA_MA13 T8 A12/BC_N DQ12 C8 DDRA_DQ33 DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ50 Place around the DRAMs
A13 DQ13 DDRA_DQ38 DDRA_MA13 T8 A12/BC_N DQ12 DDRA_DQ52
D3 C8
DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ36 A13 DQ13 DDRA_DQ55
DDRA_MA15_CAS# M8 WE_N/A14 DDRA_MA14_WE# L2 DQ14 D3 DDRA_DQ48
DQ15 D7
DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA15_CAS# M8 WE_N/A14 DQ15
RAS_N/A16 D1 DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRA_CLK0# K8 VDD1 J1 RAS_N/A16 D1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_CLK0 K7 CK_C VDD2 L1 DDRA_CLK0# K8 VDD1 J1
1 1 1 1 1 1 1
CK_T VDD3 R1 DDRA_CLK0 K7 CK_C VDD2 L1 CD@ CD@ MD@
B
DDRA_CKE0 MD@ CD109 CD110 B
K2 VDD4 B3 CK_T VDD3 R1
CKE DDRA_CKE0 22P_0402_50V8-J 22P_0402_50V8-J
VDD5 G7 K2 VDD4 B3 RF@
DDRA_DQS#5 CKE 2 2 2 2 2 2 2 RF@
F3 VDD6 B9 VDD5 G7
DDRA_DQS5 G3 LDQS_C DDRA_DQS#7

CD142

CD143

CD145
VDD7 J9 F3 VDD6 B9

CD144

CD146
DDRA_DQS#4 A7 LDQS_T DDRA_DQS7 G3 LDQS_C
DDRA_DQS4 VDD8 L9 DDRA_DQS#6 VDD7 J9
+1.2V B7 UDQS_C VDD9 T9 A7 LDQS_T CD@
UDQS_T VDD10 DDRA_DQS6 VDD8 L9
+1.2V B7 UDQS_C VDD9 T9
RD87 1 @ 2 0_0402_5% DDRA_DM4 E2 A1 UDQS_T VDD10
RD88 1 @ 2 0_0402_5% DDRA_DM5 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD89 1 @ 2 0_0402_5% DDRA_DM6 E2 A1
NF/LDM_N/LDBI_N VDDQ2 G1 RD90 1 @ 2 0_0402_5% DDRA_DM7 E7 NF/UDM_N/UDBI_N VDDQ1 C1
DDRA_BS0# N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1
DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_BS0# N2 VDDQ3 F2
BA1 VDDQ5 F8 DDRA_BS1# N8 BA0 VDDQ4 J2
DDRA_ACT# L3 VDDQ6 J8 BA1 VDDQ5 F8
DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_ACT# L3 VDDQ6 J8 (1OuF_0603_6.3V) *3
DDRA_ALERT# P9 CS_N DDRA_CS0# L7 ACT_N +2.5V_DDR Place around the DRAMs +2.5V_DDR
ALERT_N VDDQ8 D9
VDDQ9 DDRA_ALERT# VDDQ7 A9
G9 +2.5V_DDR P9 CS_N VDDQ8 D9
DDRA_BG0 M2 VDDQ10 ALERT_N VDDQ9 G9 +2.5V_DDR
BG0 B1 DDRA_BG0 M2 VDDQ10
DDRA_ODT0 K3 VPP1 R9 BG0 B1
ODT VPP2 DDRA_ODT0 K3 VPP1 R9

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_PAR T3 M1 +VREF_CA_MD ODT VPP2
1 1 1 1 1
1U_0402_6.3V6K

1U_0402_6.3V6K

PAR VREFCA DDRA_PAR T3 M1 +VREF_CA_MD

1 1 MD@ MD@ CD@ CD157 CD148

1U_0402_6.3V6K

1U_0402_6.3V6K
RD96 1 MD@ 2 10K_0402_5% TEN_UD3 N9 E1 CD@ PAR VREFCA
1 1 22P_0402_50V8-J 22P_0402_50V8-J
0.1u_0201_10V6K
.047U_0201_6.3V6K

VSS1 K1 RD97 1 MD@ 2 10K_0402_5% TEN_UD4 N9 E1 RF@

TEN 1 1 RF@

0.1u_0201_10V6K
MD@

.047U_0201_6.3V6K
CPU_DRAMRST# P1 VSS2 N1 TEN VSS1 K1 2 2 2 2 2
RESET_N VSS3 T1 MD@ MD@ CPU_DRAMRST# VSS2 N1 1 1
2 2 P1

CD152

CD156

CD147
VSS4 B2 RESET_N VSS3 T1 MD@ MD@ 2 2
@ F1
CD150

CD151
0.1u_0201_10V6K

VSSQ1 VSS5 2 2 VSS4 B2

CD154
H1 @ F1

CD155
1 G8
0.1u_0201_10V6K

A2 VSSQ2 H1 VSSQ1 VSS5 G8 2 2

CD149

VSS6 E9 CD@
CD115

1
D2 VSSQ3 A2 VSSQ2

CD153
CD@

CD116
VSS7 K9
VSS8 VSS6 E9
E3 VSSQ4 M9 D2 VSSQ3 VSS7 K9
2 VSS9 E3 VSSQ4 VSS8 M9
A8 VSSQ5
CD107

T7 2 A8 VSSQ5 VSS9
D8 VSSQ6
CD108

NC
E8 VSSQ7 D8 VSSQ6 T7
NC
C9 VSSQ8 E8 VSSQ7
H9 VSSQ9 VSSQ8
C9 VSSQ9
+0.6VS (1uF_0402_6.3V) *8 (1OuF_0603_6.3V) *2 +0.6VS
VSSQ10 H9 Place 2 near each DRAM Place around the DRAMs
F9 VSSQ10
ZQ F9
1

ZQ
1

RD43 MT40A512M16HA083EA_FBGA96

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
MD@ 240_0402_1% RD44 MT40A512M16HA083EA_FBGA96 1 1 1 1 1 1 1 1 1 1 1 1
MD@ 240_0402_1% MD@ MD@ CD@ CD@ MD@ MD@ MD@ CD168 CD169
A A
22P_0402_50V8-J 22P_0402_50V8-J
2

RF@ RF@
2

2 2 2 2 2 2 2 2 2 2 2 2

CD158

CD159

CD166

CD167
CD160

CD161

CD162

CD163

CD164

CD165
CD@ CD@ CD@

Securrritttii y Cllassifffiiici atttionii LC Futtture Centtter Secrettt Dattta Tiiitttllle

IIIssued Dattte 2016///12///14 Deciiipherrred Dattte 2017///12///13 DDR4 M emory Down

THISII SHEET OF ENGINII EERINII G DRAWINIIG ISITHE PROPRIETII ARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDIIENTIALII Siiize Documenttt Numberrr
AND TRADE SECRET INF I ORMATIOII N...THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIIIIIONIOF R D
& Re v
DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITII HER THISII SHEET NOR THE INIFORMATIOII N ITICONTAINII S
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CENTER...
Custttom
EG523 0..2

Dattte::: Tuesday,,, Aprrriiill 25,,,2017 Sheettt 17 o fff60

5 4 3 2 1
 5 4 3 2 1

+1.2V

DDR4 SO-DIMM DDRB_DQ[0..63]

DDRB_DQ[0..63] 6

1
DDRB_DQS#[0..7]
RD91
DDRB_DQS#[0..7] 6
+1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V 240_0402_1%
DDRB_DQS[0..7]
JDDR1A JDDR1B @
DDRB_DQS[0..7] 6

2
1 2 DDRB_MA3 131 132 DDRB_MA2
DDRB_DQ12 3 VSS_1 VSS_2 4 DDRB_DQ9 6 DDRB_MA3 DDRB_MA1 133 A3 A2 134 DDRB_EVENT# DDRB_MA2 6
5 DQ5 DQ4 6 6 DDRB_MA1 135 A1 EVENT_n 136
DDRB_DQ13 7 VSS_3 VSS_4 8 DDRB_DQ8 DDRB_CLK0 137 VDD_9 VDD_10 138 DDRB_CLK1
9 DQ1 DQ0 10 6 DDRB_CLK0 DDRB_CLK0# 139 CK0_t CK1_t 140 DDRB_CLK1# DDRB_CLK1 6
DDRB_DQS#1 11 VSS_5 VSS_6 12 6 DDRB_CLK0# 141 CK0_c CK1_c 142 DDRB_CLK1# 6
DDRB_DQS1 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRB_PAR 143 VDD_11 VDD_12 144 DDRB_MA0
15 DQS0_t VSS_7 16 DDRB_DQ11 6 DDRB_PAR Parity A0 DDRB_MA0 6
DDRB_DQ10 17 VSS_8 DQ6 18
D 19 DQ7 VSS_9 20 DDRB_DQ15 DDRB_BS1# 145 146 DDRB_MA10 D
DDRB_DQ14 21 VSS_10 DQ2 22 6 DDRB_BS1# 147 BA1 A10/AP 148 DDRB_MA10 6
23 DQ3 VSS_11 24 DDRB_DQ5 DDRB_CS0# 149 VDD_13 VDD_14 150 DDRB_BS0#
DDRB_DQ0 25 VSS_12 DQ12 26 6 DDRB_CS0# DDRB_MA14_W E# 151 CS0_n BA0 152 DDRB_MA16_RAS# DDRB_BS0# 6
27 DQ13 VSS_13 28 DDRB_DQ4 6 DDRB_MA14_W E# 153 W E_n/A14 RAS_n/A16 154 DDRB_MA16_RAS# 6
DDRB_DQ6 29 VSS_14 DQ8 30 DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15_CAS#
31 DQ9 VSS_15 32 DDRB_DQS#0 6 DDRB_ODT0 DDRB_CS1# 157 ODT0 CAS_n/A15 158 DDRB_MA13 DDRB_MA15_CAS# 6
33 VSS_16 DQS1_c 34 DDRB_DQS0 6 DDRB_CS1# 159 CS1_n A13 160 DDRB_MA13 6
35 DM1_n/DBl1_n/NC DQS1_t 36 DDRB_ODT1 161 VDD_17 VDD_18 162
DDRB_DQ7 37 VSS_17 VSS_18 38 DDRB_DQ1 6 DDRB_ODT1 163 ODT1 C0/CS2_n/NC 164 +VREF_CA_DIMM
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 DDRB_SA2
DDRB_DQ3 41 VSS_19 VSS_20 42 DDRB_DQ2 167 C1/CS3_n/NC SA2 168
@

0.1u_0201_10V6K

2.2U_0402_6.3V6M
43 DQ10 DQ11 44 DDRB_DQ32 169 VSS_53 VSS_54 170 DDRB_DQ36
DDRB_DQ18 VSS_21 VSS_22 DDRB_DQ20 DQ37 DQ36 172 1 1
45 46 171
47 DQ21 DQ20 48 DDRB_DQ33 173 VSS_55 VSS_56 174 DDRB_DQ37
DDRB_DQ16 49 VSS_23 VSS_24 50 DDRB_DQ21 175 DQ33 DQ32 176
51 DQ17 DQ16 52 DDRB_DQS#4 177 VSS_57 VSS_58 178 2 2
DDRB_DQS#2 53 VSS_25 VSS_26 54 DDRB_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180

CD1

CD2
DDRB_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 181 DQS4_t VSS_59 182 DDRB_DQ34
57 DQS2_t VSS_27 58 DDRB_DQ17 DDRB_DQ39 183 VSS_60 DQ39 184
DDRB_DQ22 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDRB_DQ35
61 DQ23 VSS_29 62 DDRB_DQ19 DDRB_DQ38 187 VSS_62 DQ35 188
DDRB_DQ23 63 VSS_30 DQ18 64 189 DQ34 VSS_63 190 DDRB_DQ45
65 DQ19 VSS_31 66 DDRB_DQ24 DDRB_DQ41 191 VSS_64 DQ45 192
DDRB_DQ27 67 VSS_32 DQ28 68 193 DQ44 VSS_65 194 DDRB_DQ44
69 DQ29 VSS_33 70 DDRB_DQ29 DDRB_DQ40 195 VSS_66 DQ41 196
DDRB_DQ28 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDRB_DQS#5
73 DQ25 VSS_35 74 DDRB_DQS#3 199 VSS_68 DQS5_c 200 DDRB_DQS5
+1.2V 75 VSS_36 DQS3_c 76 DDRB_DQS3 201 DM5_n/DBl5_n/NC DQS5_t 202
77 DM3_n/DBl3_n/NC DQS3_t 78 DDRB_DQ47 203 VSS_69 VSS_70 204 DDRB_DQ46
DDRB_DQ25 79 VSS_37 VSS_38 80 DDRB_DQ26 205 DQ46 DQ47 206
81 DQ30 DQ31 82 DDRB_DQ43 207 VSS_71 VSS_72 208 DDRB_DQ42
DDRB_DQ30 83 VSS_39 VSS_40 84 DDRB_DQ31 209 DQ42 DQ43 210
85 DQ26 DQ27 86 DDRB_DQ53 VSS_73 VSS_74 DDRB_DQ52
1

211 212
87 VSS_41 VSS_42 88 213 DQ52 DQ53 214
RD92 RD93
240_0402_1% 240_0402_1% 89 CB5/NC CB4/NC 90 DDRB_DQ48 215 VSS_75 VSS_76 216 DDRB_DQ49
91 VSS_43 VSS_44 92 217 DQ49 DQ48 218
93 CB1/NC CB0/NC 94 DDRB_DQS#6 219 VSS_77 VSS_78 220
2

DDRB_DQS#8 95 VSS_45 VSS_46 96 DDRB_DQS6 221 DQS6_c DM6_n/DBl6_n/NC 222

DDRB_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 223 DQS6_t VSS_79 224 DDRB_DQ55
99 DQS8_t VSS_47 100 DDRB_DQ54 225 VSS_80 DQ54 226
C 101 VSS_48 CB6/NC 102 227 DQ55 VSS_81 228 DDRB_DQ51 C
103 CB2/NC VSS_49 104 DDRB_DQ50 229 VSS_82 DQ50 230
105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDRB_DQ56
107 CB3/NC VSS_51 108 CPU_DRAMRST# DDRB_DQ60 233 VSS_84 DQ60 234
DDRB_CKE0 109 VSS_52 RESET_n 110 DDRB_CKE1 CPU_DRAMRST# 6,17 235 DQ61 VSS_85 236 DDRB_DQ61
6 DDRB_CKE0 111 CKE0 CKE1 112 DDRB_CKE1 6 DDRB_DQ57 237 VSS_86 DQ57 238
1
DDRB_BG1 113 VDD_1 VDD_2 114 DDRB_ACT# CD3 239 DQ56 VSS_87 240 DDRB_DQS#7
6 DDRB_BG1 DDRB_BG0 115 BG1 ACT_n 116 DDRB_ALERT# DDRB_ACT# 6 241 VSS_88 DQS7_c 242 DDRB_DQS7
0.1u_0201_10V6K
6 DDRB_BG0 117 BG0 ALERT_n 118 DDRB_ALERT# 6 243 DM7_n/DBl7_n/NC DQS7_t 244
@
DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 2 DDRB_DQ59 245 VSS_89 VSS_90 246 DDRB_DQ62
6 DDRB_MA12 DDRB_MA9 121 A12 A11 122 DDRB_MA7 DDRB_MA11 6 247 DQ62 DQ63 248
6 DDRB_MA9 123 A9 A7 124 DDRB_MA7 6 DDRB_DQ58 249 VSS_91 VSS_92 250 DDRB_DQ63
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 251 DQ58 DQ59 252
6 DDRB_MA8 DDRB_MA6 127 A8 A5 128 DDRB_MA4 DDRB_MA5 6 SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
6 DDRB_MA6 A6 A4 130 DDRB_MA4 6 7,40 2 SMB_CLK_S3 +VDD_SPD 255 SCL SDA 256 DDRB_SA0 SMB_DATA_S3 7,40
129
VDD_7 VDD_8 +3VS RD1 1
0_0603_5% 257 VDDSPD SA0 258
259 VPP_1 Vtt 260 DDRB_SA1 +0.6VS
1 1 VPP_2 SA1
ARGOS_D4AS0-26001-1P60 CD4 CD5 261 262
GND_1 GND_2
ME@ 2.2U_0402_6.3V6M 0.1u_0201_10V6K
2 2 ARGOS_D4AS0-26001-1P60
ME@

1 2 +VPP
+2.5V_DDR RD2
0_0603_5%

+1.2V

1
CD117 Note:
1

+0.6VS +2.5V_DDR
0.1u_0201_10V6K
2 VREF trace width:20 mils at least Layout Note:
RD3
1K_0402_1% Spacing:20mils to other signal/planes Place near DIMM
Place near DIMM scoket @
2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
B 1 1 1 1 1 1 1 1 B
RD4 1 2 +VREF_CA_DIMM CD@
5 DDR_SB_VREFCA
2_0402_5%
1
2 2 2 2 2 2 2 2

CD118
1
1

CD7

CD8
CD6
CD13

CD9

CD10

CD11

CD12
0.022U_0201_6.3V6-K RD5 CD14
2 1K_0402_1% 0.1u_0201_10V6K CD@ CD@
2
1

RD6
24.9_0402_1%

+1.2V
2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CD19

CD20

CD21

CD22

CD23

CD24

CD25

CD26

CD27

CD28

CD29

CD30

CD31

CD32

CD33

CD34
CD@ CD@ CD@ CD@

+3VS +3VS +3VS

+1.2V
1

RD7 RD8 RD9

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

0_0402_5% 0_0402_5% 0_0402_5%

@ @
RF@

RF@
0.1u_0201_10V6K

0.1u_0201_10V6K

33P_0402_50V8J

33P_0402_50V8J
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
2

1 1 1 1 1 1
DDRB_SA0 DDRB_SA1 DDRB_SA2
A A
2 2 2 2 2 2
CD15

CD16

CD17

CD18

CD36

CD37
1

RD10 RD11 RD12

0_0402_5% 0_0402_5% 0_0402_5%
@
For EMC
Near JDDRL1
2

Securityii Clasll siifici ationii LC Future Center Secret Data Title

DDR4 SO-DIMM
SPD Address = 2H Issued Date
THISII SHEET OF ENGINII EERINII G DRAWINII G ISITHE PROPRIETARII Y PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIALII
2015/08/20 Deciiiphered Date 2016/08/20

AND TRADE SECRET INIFORMATIOII N... THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIOIIIIIIN OF R&D Siiize Documenttt Number R ev
DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITII HER THISII SHEET NOR THE INIFORMATIOII N ITI CONTAINII S
MAY BE USED BY OR DISCIILOSED TO ANY THIRII D PARTY WITIIHOUT PRIOIIR WRITII TEN CONSENT OF LC FUTURE CENTER...
Custttom
EG521 0.. 2

Dattte::: Tuesday,,, Apriiilll 25,,, 2 0 1 7 Sheettt 18 o ff 60

5 4 3 2 1
 5 4 3 2 1

DVDD_IO +1.8VS +1.8V_AUDIO

+3VALW
2 0_0402_5%
RA213 1 2 0_0402_5% Digital power for HDA link RA225 1

+1.8VALW 8/29 Add +1.8VS Circuit for Audio wei

+3VS
2
RA226 1 @ 2 0_0402_5%
CA2
RA216 1 @ 2 0_0402_5% 0.1U_0201_6.3V6-K
Close to1 Pin7 UA1
DMIC_DATA RA19 1 2 0_0402_5% DMIC_DATA_R 1 30
33 DMIC_DATA DMIC_CLK RA18 1 2 0_0402_5% DMIC_CLK_R 2 HD-GPIO0/DMIC-DATA CR-GPIO 31 SD_CD#
33 DMIC_CLK HDA_SDOUT_AUDIO 3 HD-GPIO1/DMIC-CLK CR-SD-CD 32 SD_WP SD_CD# 31
8 HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO 4 HD-SDATA-OUT CR-SD-WP 33 SD_D1_R SD_WP 31
D 8 HDA_BITCLK_AUDIO 5 HD-BCLK CR-SD-DAT[1] 34 SD_D0_R SD_D1_R 31 D
Analog power for mixers, & IO ports Power supply for full-bridge left/Right channel HDA_SDIN0
CA1 1 2 2.2U_0402_6.3V6M
RA16 1 2 33_0402_5% SDATA_IN 6 HD-LDO3-CAP CR-SD-DAT[0] 35 SD_CLK_R SD_D0_R 31
+5VS +5VA +5VS +5VD 8 HDA_SDIN0 7 HD-SDATA-IN CR-SD-CLK 36 +5VA SD_CLK_R 31
DVDD_IO
EMC_NS@ HDA_SYNC_AUDIO 8 HD-DVDD-IO HD-AVDD1 37 LDO1_CAP CA43 1 2 2.2U_0402_6.3V6M CA48 1 2 1U_0402_6.3V6K
8 HDA_SYNC_AUDIO PC_BEEP 9 HD-SYNC HD-LDO1-CAP 38
LA25 1 2 BLM15PD600SN1D_2P RA205 1 2 100K_0402_1% CA44 1 2 1U_0402_6.3V6K
+3VS PLUG_IN 10 HD-PCBEEP HD-VREF 39
RA7 1 2 0_0603_5% RA204 1 2 200K_0402_1% JSENSE MICBIASB
RA10 1 EMC@ 2 0_0603_5% RING2_CONN 11 HD-JD1(HP/LINE1) HD-MIC2-VREFO 40 LINE1_VREF_L +1.8V_AUDIO
RING3_CONN 12 HD-MIC2-L(RING) HD-LINE1-VREFO-L 41 HPOUT_L
VDD_STB 13 HD-MIC2-R(SLEEVE) HD-HPOUT-L 42 HPOUT_R
0.1U_0201_6.3V6-K

1U_0402_6.3V6K

2 2
1 RA38 2 2.2K_0402_5% CA41 1 2 2.2U_0402_6.3V6M 14 HD-3V5V-STB HD-HPOUT-R 43 CA47 1 2 1U_0402_6.3V6K +1.8V_AUDIO

CA18 0.1U_0201_6.3V6-K

CA19 0.1U_0201_6.3V6-K
6K CA178
10U_0805_10V
1 2 2
CA42 CA20 LINE1_R 15 HD-MIC2-CAP HD-CPVEE 44
MICBIASB 1 RA37 2 2.2K_0402_5% LINE1_L 16 HD-LINE1-R HD-CBN 45 4.7U_0603_6.3V6K 2 1 CA4
1 1 17 HD-LINE1-L HD-CPVDD 46
2 1 1 18 HD-LINE2-R HD-CBP 47 HD_LDO2 CC167 1 2 10U_0402_6.3V6M @
SD_CMD_R 19 HD-LINE2-L HD-LDO2-CAP 48
31 SD_CMD_R SD_D3_R 20 CR-SD-CMD HD-AVDD2 49
31 SD_D3_R SD_D2_R 21 CR-SD-DAT[3] HD-PVDD1 50 SPK_L+
+5VD
Analog power for DACs, ADCs
31 SD_D2_R 22 CR-SD-DAT[2] HD-SPKOUT-LP 51 SPK_L-
CW1 1 2 1U_0402_6.3V6K 2
23 CR-SDREG HD-SPKOUT-LN 52 SPK_R- +3VS
CW2 1 2 1U_0402_6.3V6K 24 CR-TEST1 HD-SPKOUT-RN 53 SPK_R+ CC257
RW11 1 2 6.2K_0402_1% RREF 25 CR-V18-CAP HD-SPKOUT-RP 54 +5VD 10U_0402_6.3V6M
USB20_N5 RW12 1 USB20_N5_R 26 CR-RREF HD-PVDD2 55 SPKR_MUTE# 1
+3VALW 9 USB20_N5 USB20_P5 RW13 1
2 0_0402_5%
2 0_0402_5% USB20_P5_R 27 CR-DM HD-PDB 56 Digital power for digital I/O circuit
+3VS +3VS_CARD 9 USB20_P5 28 CR-DP HD-DVDD
+3VS_CARD 29 CR-3V3-IN
CARD_3V3 CR-SD-3V3
Power for card reader controller 1 1
GNDPAD
57 2 2
RA220 1 @ 2 0_0402_5% RTS5199-CG_QFN56_7X7 CA180 CA179

0.1U_0201_6.3V6-K

1U_0402_6.3V6K
CW18 CW19
4.7U_0402_6.3V6M 0.1u_0201_10V6K
1 1
2 2
RA219 1 2 0_0402_5%
1U_0402_6.3V6K

1
C206

@
2

C
2 C
DA4
EC_MUTE# 1 2 @ SPKR_MUTE#
44 EC_MUTE#

1
LRB751V-40T1G_SOD323-2 LINE1_L CA45 1 2 1U_0402_6.3V6K
RA35 1 @ 2 0_0402_5% RA43
10K_0402_5% LINE1_VREF_L RA41 1 2 4.7K_0402_5%
Power for combo jack depop circuit at system HPOUT_L RA21 1 2 51_0402_1% A_HP_OUTL_R
shutdown mode

2
HPOUT_R RA20 1 2 51_0402_1% A_HP_OUTR_R
+3VL
DA1 LINE1_VREF_L RA42 1 2 4.7K_0402_5%
RA203 1 2 0_0402_5% VDD_STB 2
44 BEEP#
1PC_BEEP1 1 @2 CA40 1 2 PC_BEEP LINE1_R CA46 1 2 1U_0402_6.3V6K
3 RA211 0_0402_5% 0.1U_0201_6.3V6-K
8 PCH_BEEP

1
To solve the background noise while combojack connecting to an
active speaker and system entry into S3/S4/S5 without analog power. LBAT54CWT1G_SOT323-3 RA14
10K_0402_5%
11/8 SIT Vendor suggestion form 47 ohm change to 51om wei

2
RA217 1 @ 2 0_0402_5% @1 TC203
8 HDA_RST_AUDIO#

JSPK1 ME@
RA223 1 CD@ 2 15_0402_5% SPK_R+ RA222 1 2 0_0402_5% SPK_R+_CONN 1
RA224 1 CD@ 2 15_0402_5% SPK_R- RA221 1 2 0_0402_5% SPK_R-_CONN 21
RA1 1 2 0_0402_5% RA32 1 CD@ 2 15_0402_5% SPK_L+ RA33 1 RA30 1 2 0_0402_5% SPK_L+_CONN 32
EMC_NS@ CD@ 2 15_0402_5% SPK_L- RA34 1 2 0_0402_5% SPK_L-_CONN 4 3
4
RA4 1 2 0_0402_5%
EMC_NS@ 5
LW2 6 GND1

470P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K
CA29

CA30
CA18

CA18
220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K
USB20_N5 1 2 USB20_N5_R GND2

1
CA3

CA32 EMC@

CA181

CA182 EMC@
B 1 2 2 2 2 2 B
RA9 1 2 0_0402_5% ACES_88231-04001

4
1 1 1 1
RA12 1 2 0_0402_5% USB20_P5 4 3 USB20_P5_R 11/8 SIT Cost down to 0ohm wei
4 3 11 11

EMC@
EMC_NS@

@
EMC
EXC24CH900U_4P 2 2 2 2
EMC_NS@
FOR EMI CD@ CD@ CD@ CD@

GND GNDA
8/16 Update Audio Jack P/N SP011509163 wei

Audio Jack JHP1 ME@

RING2_CONN 3
R3124 1 @ 2 C232 1 2 A_HP_OUTL_R 1 G/M
0_0402_5% @ 470P_0201_50V7-K L
RING3_CONN PLUG_IN 5
RING2_CONN 5
A_HP_OUTL_R DMIC_CLK HDA_SYNC_AUDIO 6
A_HP_OUTR_R HDA_SDOUT_AUDIO 6
PLUG_IN DMIC_DATA RA27 1 2 27_0402_5% HDA_BITCLK_AUDIO R3123 1 @ 2 C184 1 2 A_HP_OUTR_R 2
EMC@ HDA_SDIN0 0_0402_5% @ 470P_0201_50V7-K R
RING3_CONN 4
CA3

CA3

M/G
100P_0201_25V

100P_0201_25V
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

1 1
EMC_NS@

EMC_NS@

CA2
CA2

CA2

CA2
8

7
33P_0201_50V8-J
22P_0201_258J

22P_0201_258J

MS
33P_0201_50V8-J

6
1

EMC_NS 3

EMC_NS 4

EMC_NS@

1 1 1 1
47P_0201_25V8-J

1 DA5 DA6 DA7 DA8 DA9 SINGA_2SJ3095-140111F

1

100P_0201_25V8J

100P_0201_25V8J
8J

8J

2 2
EMC

C185 1 1
@

EMC_NS@
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

2 2 2 2 C182 C183
A
2 EMC@ EMC@ A
2 2
For EMI
2

2
2

8/16 Update Audio Jack P/N DC021608101 wei

Securiiity Clllassiiifiiicatiiion LC Future Center Secret Data Title

Issued Date 2015/08/20 Decipherii ed Date 2016/08/20 Codec & CR_RTS5199

THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIAI L
AND TRADE SECRET INIFORMATIONII .. THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R &
DDEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIZEII D BY LC FUTURE CENTER NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORII WRITTEII N CONSENT OF LC FUTURE CENTER...
C
EG521 0..2

Dattte::: Tuesday,,, Apriiilll 25,,, 2017 Sheett 30 off 60

5 4 3 2 1
 5 4 3 2 1

D D

CARD_3V3

SD / MMC

4.7U_0402_6.3V6M

0.1u_0201_10V6K
1 1
SD_D0_R RW 3 1 2 0_0402_5% SD_D0 CW 9 CW 17
30 SD_D0_R
CW 5 1 2 5.6P_0402_50V8-D @
2 2
EMC@

JREAD1 ME@
SD_D1_R RW 4 1 2 0_0402_5% SD_D1 SD_D3 1
30 SD_D1_R SD_CMD CD/DAT3
CW 6 1 2 5.6P_0402_50V8-D 2
3 CMD
4 VSS1
EMC@
SD_CLK 5 VDD
6 CLK
VSS2
30 SD_D2_R
SD_D2_R RW 5 1 2 0_0402_5% SD_D2 Close to Connector SD_D0
SD_D1
7
DAT0
CW 7 1 2 5.6P_0402_50V8-D 8
C SD_D2 9 DAT1 C

EMC@
DAT2

SD_CD# 10 12
SD_D3_R SD_D3 30 SD_CD# SD_W P CARDDETECT SH1
RW 6 1 2 0_0402_5% 11 13
30 SD_D3_R 30 SD_W P WRITEPROTECT SH2
CW 8 1 2 5.6P_0402_50V8-D 14
SH3 15
EMC@ SH4
T-SOL_5-251301001000-6_NR

SD_CMD_R SD_CMD
Close to Connector
RW 7 1 2 0_0402_5%
30 SD_CMD_R
CW 11 1 2 5.6P_0402_50V8-D

EMC@ CARD_3V3

8/16 Update Conn. P/N SP07000WG00 wei

1
SD_CLK_R RW 8 1 2 0_0402_5% SD_CLK
30 SD_CLK_R
CW 12 1 2 5.6P_0402_50V8-D DW 1

AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
EMC@

2
2
B B

FOR ESD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cardreader

THIS SHEET OF ENGINEERING DRAW ING IS T HE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL
AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D Siiize Document Number Rev
DEPARTMENT EXCEPT AS AUT HORIZED BY LC FUT URE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUT URE CENTER.
Custom
EG521 0.2

Date: T ues day, Apriiilll 25, 2017 Sheet 31 of 60

5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_TPM

RTPM1 1 TPM@ 2 0_0603_5% 1A

D D
1 1
1 CTPM3
CTPM4 CTPM1 0.1u_0201_10V6K
0.1u_0201_10V6K 10U_0603_6.3V6M TPM@
TPM@ 2 TPM@ 2
2

TPM
+3VS_TPM
UTPM1 TPM@
1 24
2 NC_1 VDD3 10
C 3 NC_2 VDD1 Reserve for Nationz TPM C
NC_3
RTPM12 1 TPM@ 2 7 28 RTPM2 1 TPM@ 2 4.7K_0402_5%
SERIRQ_TPM
PP LPCPD# RTPM5 1 TPM@ 2 0_0402_5%
0_0402_5% 27 SERIRQ 7,44
6 SERIRQ LPC_AD0_TPM RTPM6 1 TPM@ 2 0_0402_5%
26 LPC_AD1_TPM RTPM7 1 TPM@ 2 0_0402_5% LPC_AD0 7,44
Reserve for Nationz TPM 9 NC_4 LAD0 23 LPC_AD1 7,44
NC_7 LAD1 LPC_AD2_TPM
22 LPC_FRAME#_TPM RTPM9 11 TPM@
RTPM8 TPM@2 0_0402_5%
2 0_0402_5%
LFRAME# LPC_AD2 LPC_FRAME# 7,44
7,44
4 20
GND_1 LAD2 LPC_AD3_TPM RTPM10 1 TPM@ 2 0_0402_5%
11 17 LPC_AD3 7,44
+3VALW GND_2 LAD3
18
GND_3 25 +3VS_TPM
RTPM11 1 TPM@ 2 CLK_PCI_TPM 7
5 GND_4 21
0_0603_5% 8 NC_5 LCLK 19
12 NC_6 VDD2 15 TPM_CLKRUN# RTPM13 10_0402_5%
@ 2
NC_8 CLK_RUN# PM_CLKRUN# 7
Add for Nuvoton TPM 13 PLT_RST# 11,37,40,44
14
NC_9 16 Reserve for Nuvoton TPM

1
NC_10 LRESET#
Z32H320TC-LPC-T28-LT1_TSSOP28 RTPM4
0_0402_5%
TPM@
Nationz TPM Nuvoton TPM

2
B B

RTPM2 Stuff NC

RTPM12 Stuff NC

RTPM11 NC Stuff

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 32 o f 60

5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+3VS
CMOS Camera +3VS Need short +3VS_CMOS_R
+LCDVDD +LCDVDD_CON J1 @
1 2
U5 1 2
5 1 R263 1 2 W=60mils W=40 mils JUMP_43X39
IN OUT

RF_NS@
1 2 0_0805_5% +3VS_CMOS
GND

0.1u_0201_10V6K
@ LP2301ALT1G_SOT23-3

33P_0402_50V8J
4.7U_0402_6.3V6M
C1 PCH_ENVDD 4 3
EN OCB 1 1 1 W=40mils
0.1u_0201_10V6K Q7 3 1 @ R3 1 @ 2

D
2 SY6288C20AAC_SOT23-5 0_0603_5%

0.01U_0201_10V6K
@
1 1 1 1
D
2 2 2 D
C5 C3 C4
U5 EN PIN VIH MIN 1.5V

2G
0.1u_0201_10V6K 0.1u_0201_10V6K

C121

C122

C123
10U_0603_6.3V6M
@ CD@ @
2 2 2

C6
2
CMOS_ON# R5 1 @ 2
100K_0402_5%
For RF 1 1
C9 C10
V20B+ +LEDVDD 0.01U_0201_25V6-K 0.1u_0201_10V6K
2A 80 mil EMC_NS@ @
2A 80 mil 1
7 1 2 0_0805_5% 2 2
R For EMI
Close to R5

4.7U_0805_25V6-K

0.1U_0201_25V6-K
CD@

EMC@
1 1

2 2

C14

C15
EMI Request

PCH_ENVDD +3VS JEDP1

4 PCH_ENVDD
1
+LEDVDD 1
1

2
R1 3 2
3

2
100K_0402_5% 4
R9 R8 CPU_EDP_TX0+ C19 1 2 0.1u_0201_10V6K EDP_TX0+ 5 4
4 CPU_EDP_TX0+ CPU_EDP_TX0- EDP_TX0- 5
100K_0402_1% 100K_0402_1% C16 1 2 0.1u_0201_10V6K 6
4 CPU_EDP_TX0- 6
2

7
CPU_EDP_TX1+ C17 1 EDP_TX1+ 7
@ @ 2 0.1u_0201_10V6K 8
4 CPU_EDP_TX1+ 8

1
C CPU_EDP_TX1- EDP_TX1- C
C18 1 2 0.1u_0201_10V6K 9
+3VS 4 CPU_EDP_TX1- 9
10
EDP_AUX CPU_EDP_AUX 1 C20 EDP_AUX 10
2 0.1u_0201_10V6K 11
EDP_AUX# 4 CPU_EDP_AUX EDP_AUX# 11
CPU_EDP_AUX# C21 1 2 0.1u_0201_10V6K 12
4 CPU_EDP_AUX# 12
2

13
13
R10 DISPOFF# 14
14

2
PCH_ENBKL R11 1@ 2 4.7K_0402_5% 15
INVT_PW M 15
0_0402_5% @ R15 R13 16
16
100K_0402_1% 100K_0402_1% 17
17
1

+3VS 18
18
R12 1 @ 2 0_0402_5% DISPOFF# @ @ 19
44 BKOFF# 4 CPU_EDP_HPD 19

1
R21 1 @ 2 20
20
1 0_0402_5% 21
+LCDVDD_CON 21
R14 1 @ 2 0_0402_5% ENBKL 22
4 PCH_ENBKL ENBKL 44
EMC_NS@ C22
W=60mils 23
22
+3VS 23
1

680P_0402_50V7K 24
2 30 DMIC_DATA 24
R16 30 DMIC_CLK 25 25
100K_0402_5% 26 26
27 27
R296 1 @ 2 0_0402_5% CMOS_ON# 2 0_0402_5% USB20_P8_R 28
8 PCH_CMOS_ON# 9 USB20_P8 R182 1 28
2

1 2 0_0402_5% USB20_N8_R 29
9 USB20_N8 R183 29
+3VS_CMOS 30 30
R297 1 @ 2 0_0402_5% 31
44 EC_CMOS_ON# W=40mils 32
G1
1 G2
+3VS C24
.047U_0201_6.3V6K DRAPH_FC5AF301-3181H
EMC_NS@ ME@
2

2
R18
1K_0402_5%
EMI request
@
DMIC_CLK DISPOFF# INVT_PW M EMI request
1

INVT_PW M
470P_0201_50V7-K

470P_0201_50V7-K
R19 1 @ 2 0_0402_5%
100P_0201_25V8J

4 PCH_EDP_PW M
B 1 1 1 For EMI B
EMC_NS@

EMC_NS@
EMC@
1

L12 EMC_NS@
R20 USB20_N8 1 2 USB20_N8_R
100K_0402_5% 2 2 2 1 2
C11

C12

C13
USB20_P8 4 3 USB20_P8_R
2

4 3
EXC24CH900U_4P

Touch Screen
Touch Screen

USB20_P6_CONN
+5VS +5VS_TS
L15 USB20_N6_CONN
USB20_P6 1 2 USB20_P6_CONN
1 2
3

+5VS_TS R26 1 T S@ 2 0_0402_5%

1 JTS1 ME@
USB20_N6 4 3 USB20_N6_CONN C25 1
4 3
2 1
1

D2 0.1u_0201_10V6K 7
EXC24CH900U_4P T S@ R28 2 T S@ 1 0_0402_5% TS_RS 3 2 GND1
1

2 44 EC_TS_ON 4 3
EMC_NS@ 8
R23 1 T S@ 2 0_0402_5% USB20_N6_CONN 5 4 GND2
9 USB20_N6 R24 1 T S@
D1
2 0_0402_5% USB20_P6_CONN 6 5
9 USB20_P6 6
AZC199-02S.R7G_SOT23-3
2

CVILU_CI1806M2HR0-NH
A For EMI AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@ A
2

EMC_NS@
1

For ESD

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 en

eDP/CMOS/Touch screen
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF LC FUTURE CENTER... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: Tu e s d a y, Apriiilll 2 5 , 2 0 1 7 Sheet 33 o f 60

5 4 3 2 1
 5 4 3 2 1

L2 EMC@ EMC_NS@
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2
1 2
C26 3.3P_0402_50V8-C
EMC_NS@ +3VS
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2
4 3 C27 3.3P_0402_50V8-C
EXC24CH900U_4P
D L3 EMC@ EMC_NS@ D3 D
HDMI_TX0-_C 1 2 HDMI_TX0-_CON HDMI_DET 1 1 HDMI_DET
1 2 1 2 10 9

5
C28 3.3P_0402_50V8-C

G
HDMIDAT_R 2 2 HDMIDAT_R
EMC_NS@ Q1B 9 8
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2
4 3 HDMICLK_R 4 4 HDMICLK_R
C29 3.3P_0402_50V8-C 7 7
EXC24CH900U_4P 4 3 HDMICLK_R

S
4 DDPB_CLK +5VS_HDMI 5 5 +5VS_HDMI
6 6

D
L4 EMC@ EMC_NS@ 2N7002KDWH_SOT363-6
3 3

2
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2

G
1 2 C30 3.3P_0402_50V8-C Q1A 8
EMC_NS@
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2
4 3 C31 3.3P_0402_50V8-C 1 6 HDMIDAT_R

S
4 DDPB_DATA
AZ1045-04F_DFN2510P10E-10-9

D
EXC24CH900U_4P
2N7002KDW H_SOT363-6 EMC_NS@
L5 EMC@ EMC_NS@
HDMI_TX2-_C HDMI_TX2-_CON
1
1 2
2 1 2 For EMC
C32 3.3P_0402_50V8-C
EMC_NS@
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2
4 3 C33 3.3P_0402_50V8-C
EXC24CH900U_4P

+5VS
For EMC +3VS

2
D4
+5VS +5VS_HDMI_F +5VS_HDMI
D5
@ 2 @ F1

2
C 1 1 2 C
HDMI_CLK-_C R29 1 2 470_0402_5% BAT54S-7-F_SOT23-3 3
R35

1
2
Q12 D4 RB491D_SOT23-3 0.5A_6V_1206L050YRHF

G
HDMI_CLK+_C 1M_0402_5%
R30 1 2 470_0402_5%

1
HDMI_TX0-_C R31 1 2 470_0402_5% LP2301ALT1G_SOT23-3
HDMI_DET 1
3 1 C34
HDMI_TX0+_C 4 HDMI_HPD 1 3 Q22
R32 1 2 470_0402_5%

D
0.1u_0201_10V6K

2
1
2N7002KW _SOT323-3

2
HDMI_TX1-_C R33 1 2 470_0402_5% 2 RP1
R41 2.2K_0404_4P2R_5%

G
2
HDMI_TX1+_C R34 1 2 470_0402_5% 20K_0402_5%
46 SUSP

3
4
HDMI_TX2-_C R37 1 2 470_0402_5%

1
HDMI_TX2+_C R38 1 2 470_0402_5%
+5VS_HDMI
JHDMI1 ME@
1

D Q13
2 18 15 HDMICLK_R
+3VS G +5V_Power SCL HDMIDAT_R
2N7002KW _SOT323-3 16
SDA
S HDMI_TX0+ C38 2 1 0.1u_0201_10V6K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7
4 HDMI_TX0+
3

HDMI_TX0- C37 2 1 0.1u_0201_10V6K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 TMDS_Data0+ 13

4 HDMI_TX0- HDMI_TX1+ C40 2 1 0.1u_0201_10V6K HDMI_TX1+_C R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4 TMDS_Data0- CEC
R42 1 @ 2 17
4 HDMI_TX1+ HDMI_TX1- C39 2 1 0.1u_0201_10V6K HDMI_TX1-_C R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6 TMDS_Data1+ DDC/CEC_Ground 19 HDMI_DET
100K_0402_5% 4 HDMI_TX1- HDMI_TX2+ C42 2 1 0.1u_0201_10V6K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 TMDS_Data1- Hot_Plug_Detect
4 HDMI_TX2+ HDMI_TX2- C41 2 1 0.1u_0201_10V6K HDMI_TX2-_C R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3 TMDS_Data2+
4 HDMI_TX2- TMDS_Data2-
8 14
5 TMDS_Data0_Shield Utility
2 TMDS_Data1_Shield
B TMDS_Data2_Shield B
20
11 GND1 21
HDMI_CLK+ C36 2 1 0.1u_0201_10V6K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 TMDS_Clock_Shield GND2
4 HDMI_CLK+ 22
HDMI_CLK- C35 2 1 0.1u_0201_10V6K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 TMDS_Clock+ GND3
4 HDMI_CLK- GND4 23
TMDS_Clock-

ALLTO_C128S9-K1935-L

8/16 Update HDMIConn. P/N DC021608081 wei

Close to JHDMI1
D6 D7
HDMI_CLK+_CON 1 1 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 HDMI_TX1-_CON
10 9 10 9
HDMI_CLK-_CON 22 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 22 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON 44 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 44 7 7 HDMI_TX2-_CON

HDMI_TX0-_CON 55 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 55 6 6 HDMI_TX2+_CON

33 33

8 8

AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9

EMC_NS@ EMC_NS@
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 34 o f 60

5 4 3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising t i me( 10 %~90 %):
+3VALW +3VALW_LAN
0.5ms＜s pec＜ 10 0ms +3VALW_LAN +LAN_VDDREG
Need short
RL1 @
JL1 1
12
2@ width : 40 mils 1 2
JUMP_43X79 0_0603_5%
D D
1 1
+3VALW LP2301ALT1G_SOT23-3 CL4 CL5 CL1 CL2

0.1u_0201_10V6K

0.1u_0201_10V6K
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
1 1 CL6 1 CL7 1 4.7U_0402_6.3V6M 0.1u_0201_10V6K
Q14 3 1 @

0.01U_0201_10V6K
1
2 2

0.1u_0201_10V6K
RL2 1 CL8 CL9 1
2 2 2 2
100K_0402_5%

G
2
@
@ @
2

2 2
RL3 1 @ 2 @ @
44 LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS

+3VALW_LAN

2
@

2
RL4

G
manual change the Codec PN to RTL8111GUL-CG

2
10K_0402_5% QL1
RL5
10K_0402_5% UL1

1
@ LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# 10

S
1
2N7002KW _SOT323-3
RL7 1 @ 2 0_0402_5% RL6 1 PCIE_WAKE#_R
11,40,44 PCIE_W AKE#
40,44 LAN_WAKE# 2 0_0402_5%
33 RL18 1 @ 2 0_0402_5%
+3VALW_LAN GND CLK_PCIE_LAN#
C 32 16 C
AVDD33_2 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# 10
RL8 1
31 2 RSET 15
2.49K_0402_1% +LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N5 CLK_PCIE_LAN 10
30 14
LAN_XTALO AVDD10 HSIN PCIE_PTX_C_DRX_P5 PCIE_PTX_C_DRX_N5 9
29 13
28 LAN_XTALI CKXTAL2 HSIP 12 LAN_CLKREQ#_R PCIE_PTX_C_DRX_P5 9
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# RL121 @ 2 LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
25 LED1/GPIO MDIN3 9 LAN_MDI3+ LAN_MDI3- 38
0_0402_5% TL4 @ 1
LED2 MDIP3 LAN_MDI3+ 38
1

+LAN_REGOUT 24 8 +LAN_VDD10
+LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
RL9 LAN_MDI2- 38
+LAN_VDD10 22 VDDREG MDIN2 6 LAN_MDI2+
1K_0402_1% 38
PCIE_WAKE#_R 21 DVDD10 MDIP2 5 LAN_MDI1- LAN_MDI2+
20 LANW AKEB MDIN1 4 LAN_MDI1+ LAN_MDI1- 38
ISOLATE#
2

PLT_RST# 19 ISOLATEB MDIP1 3 +LAN_VDD10 LAN_MDI1+ 38

11,32,40,44 PLT_RST# PCIE_PRX_C_DTX_N5 18 PERSTB AVDD10_1 2 LAN_MDI0-
9 PCIE_PRX_DTX_N5 CL10 1 2 0.1u_0201_10V6K
ISOLATE# RL10 1 @ 2 LAN_PWR_ON# CL11 1 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_P5 17 HSON MDIN0 1 LAN_MDI0+ LAN_MDI0- 38
9 PCIE_PRX_DTX_P5 HSOP MDIP0 LAN_MDI0+ 38
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17

15K_0402_5%
@
2

RTL8111GUL-CG QFN 32P

8111GUL@

B B

LAN_XTALI
For RTL8111GUL(SWR mode, reserved)
LAN_XTALO_R 1 2 LAN_XTALO For RTL8111H (LDO mode)
RL21 1K_0402_5% +LAN_VDD10
YL1 LL1 1 2 8111GUL@
2.2UH_NLC252018T-2R2J-N_5%
1 4
OSC1 GND2 +LAN_REGOUT RL20 1 2 8111H@
2 3 0_0805_5%
GND1 OSC2
1 1 1 1 1 1 1 1
1 1
CL12 25MHZ_10PF_7V25000014 CL13 CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
12P_0402_50V8-J 15P_0402_50V8J 4.7U_0402_6.3V6M 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 1U_0402_6.3V6K 0.1u_0201_10V6K
2 2 2 2 2 2 2 2
2 2

Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)

Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 LAN_RTL8111H_CG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 37 o f 60

5 4 3 2 1
 5 4 3 2 1

DL1/DL2
1'S PN:SC300003M00
TL1
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0+ 23 2 LAN_MDO0+
37 LAN_MDI0+ MX1+ TD1+
DL1
LAN_MDI2+ 1 10 LAN_MDI2+ LAN_MDI0- 22 3 LAN_MDO0-
LINE1IN LINE1OUT 37 LAN_MDI0- MX1- TD1-

1
EMC@
LAN_MDI2- 2 9 LAN_MDI2- 21 4 MCT RL17
LINE2IN LINE2OUT MCT2 TCT2 20_0603_5%

1
8 LAN_MDI1+ 20 5 LAN_MDO1+
3 GND1 GND2 37 LAN_MDI1+ MX2+ TD2+ DL3

1
2
LAN_MDI3+ 7 LAN_MDI3+ LAN_MDI1- 19 6 LAN_MDO1- PDT5061_DO-214AA
4 LINE3IN LINE3OUT 37 LAN_MDI1- MX2- TD2- EMC@
LAN_MDI3- LAN_MDI3- EMC

2
5 6 18 7 MCT
LINE4IN LINE4OUT MCT3 TCT3

2
13 LAN_MDI2+ 17 8 LAN_MDO2+
11 GND3 GND5 37 LAN_MDI2+ MX3+ TD3+
LAN_MDI2- 16 9 LAN_MDO2-
12 GND4 37 LAN_MDI2- MX3- TD3-
AZ3133-08F.R7G_DFN3020P10E10 15 10 MCT
MCT4 TCT4
EMC_NS@ 1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL32 CL25
37 LAN_MDI3+ MX4+ TD4+ 0.022U_0603_50V7K 1000P_1206_2KV7-K
LAN_MDI3- 13 12 LAN_MDO3- EMC@ EMC@
37 LAN_MDI3- MX4- TD4-
1
2 2 EMC
C
DL2 CL24 C
LAN_MDI1- 1 10 LAN_MDI1- 0.01U_0201_25V6-K BOTH_GST5009 LF
LINE1IN LINE1OUT EMC@
LAN_MDI1+ 2 9 LAN_MDI1+ 2
LINE2IN LINE2OUT

3 GND1 GND2
8 EMC
LAN_MDI0- 7 LAN_MDI0- CHASSIS1_GND
4 LINE3IN LINE3OUT
LAN_MDI0+ 5 6 LAN_MDI0+
LINE4IN LINE4OUT
13
11 GND3 GND5

12 GND4
AZ3133-08F.R7G_DFN3020P10E10 JRJ1 ME@
EMC_NS@ 12
GND_4
11
GND_3
Place Close to TL1
10
LAN_MDO0+ 1 GND_2
EMC TX_DA+ 9
LAN_MDO0- 2 GND_1
TX_DA-
B B
LAN_MDO1+ 3
RX_DB+
CHASSIS1_GND
LAN_MDO2+ 4
BI_DC+
LAN_MDO2- 5 BI_DC-
LAN_MDO1- 6 RX_DB-
RL14 1 EMC@ 2 0_0603_5% LAN_MDO3+ 7
BI_DD+
RL15 1 EMC@ 2 0_0603_5% LAN_MDO3- 8 BI_DD-
RL16 1 EMC@ 2 0_0603_5%
ALLTO_C10235-10839-L
EMC
8/16 Update RJ45 P/N DC021608091 wei
CHASSIS1_GND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 LAN_Transformer

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number B R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER. EG521 0.2

Date: T u es d ay, April 25, 2 0 1 7 Sheet 38 of 60

5 4 3 2 1
 5 4 3 2 1

Close to U1 REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+

REMOTE2+ Near CPU core
1

1
REMOTE+_R C46 C
1 100P_0201_25V8J 2 Q16
C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- @ B MMBT3904W H_SOT323-3
2200P_0201_25V7-K 2 E @

3
@ REMOTE2-
2 REMOTE-_R

D REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: D

Trace width/space:10/10 mil

+3VALW
Near CPU
Trace length:<8"

1
R25
13.7K_0402_1%

NTC_V2
SMSC thermal sensor

12
placed near DIMM R288
100K_0402_1%_NCP15W F104F03RC
+3VS
U1 @

2
1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 7,44
REMOTE+_R 2 7 EC_SMB_DA2
1 D+ SDA EC_SMB_DA2 7,44
C47
0.1u_0201_10V6K REMOTE-_R 3 6
@
D- ALERT#
2 4 5
+3VS R51 2 @ 1 T_CRIT# GND
10K_0402_5%
NCT7718W _MSOP8

Address 1001_101xb for layout optimized, change the EC_AGND to GND

C C

+5VLP +5VLP
+5VLP

HW thermal sensor
2

2
1 R252 R253
C7 21.5K_0402_1% 21.5K_0402_1%
0.1u_0201_10V6K @ @
@
1

1
2
U4 @
8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1
1 NTC_V1 44
VCC TMSNS1
2 7 PHYST1 R6 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
44,54,55 EC_ON OT1 TMSNS2 NTC_V2 44
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8

B over temperature threshold: B

RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

FAN Conn
+5VS

JFAN1 ME@
R52 1 2 0_0603_5% +5VS_FAN 1
2 1
44 EC_FAN_SPEED 2
@ 44 EC_FAN_PW M
3
3

0.1u_0201_10V6K
1 1 4
C49 5 4
10U_0805_10V6K 6 GND1
GND2
2 2 ACES_85205-04001

C50
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Thermal sensor/FAN CONN

ONN
THIS SHEET OF ENGINEERING DRAW ING IS T HE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL
AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D Siiize Document Number Rev
DEPARTMENT EXCEPT AS AUT HORIZED BY LC FUT URE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUT URE CENTER.
Custom
EG521 0.2

Date: T ues day, Apriiilll 25, 2017 Sheet 39 o f 60

5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
+3VS
+3VS_WLAN

+3VS +3VS_WLAN JWLAN1 ME@

Need short

1
1 2
J2 @
9 USB20_P7 3 GND1 3.3VAUX1 4 R258 R259
1 USB_D+ 3.3VAUX2 1 @ T2
2 9 USB20_N7 5 6 49.9K_0402_1% 49.9K_0402_1%
1 2 USB_D- LED1#
7 8
JUMP_43X79 GND2 PCM_CLK/I2S_SCK
1 9 10

2
11 SDIO_CLK PCM_SYNC/I2S_WS
1 1
C53 12
0.1u_0201_10V6K 13 SDIO_CMD PCM_IN/I2S_SD_IN 14
SDIO_DATA0 PCM_OUT/I2S_SD_OUT 1 @ T3
@ 15 16
2 17 SDIO_DATA1 LED#2 18
SDIO_DATA2 GND11
19 20
+3VALW 21 SDIO_DATA3 UART_WAKE# 22 UART_RX_DEBUG_R R256 1 2 0_0402_5%
UART_RX_DEBUG 8
23 SDIO_WAKE# UART_RXD
LP2301ALT1G_SOT23-3 SDIO_RESET#

Q36 3 1

D
AOAC@ KEY E
25 PIN24~PIN31 NC PIN 24

0.1u_0201_10V
1 1
C2083 27 26

6K C2082
2G
@ @ 29 28
0.1u_0201_10V6K 31 30
2 2
33 32 UART_TX_DEBUG_R R257 1 2 0_0402_5%
AOAC_ON# 1 AOAC@2 GND3 UART_TXD UART_TX_DEBUG 8
9 PCIE_PTX_C_DRX_P6 35 34
44 AOAC_ON# PETP0 UART_CTS 36
R4677 100K_0402_5% 37
9 PCIE_PTX_C_DRX_N6 PETN0 UART_RTS EC_TX_RSVD
1 39 38 R62 1 @ 2 0_0402_5%
41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD R63 1 @ 2 0_0402_5%
C2081 AOAC@ 9 PCIE_PRX_DTX_P6 PERP0 VENDOR_DEFINED2 42
43
9 PCIE_PRX_DTX_N6 PERN0 VENDOR_DEFINED3
0.1u_0201_10V6K 45 44 R88 1 2 0_0402_5%
GND5 COEX3 46 EC_RX 44
2 47
10 CLK_PCIE_WLAN REFCLKP0 COEX2
10 CLK_PCIE_WLAN# 49 48
51 REFCLKN0 COEX1 50 SUSCLK_R R55 1 2 0_0402_5%
WLAN_CLKREQ_Q# GND6 SUSCLK 52 PLT_RST# SUSCLK 10
10 WLAN_CLKREQ# R61 1 2 0_0402_5% 53
PCIE_WAKE#_WLAN CLKREQ0# PERST0# BT_OFF# PLT_RST# 11,32,37,44
R262 1 @ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%
11,37,44 PCIE_WAKE# PEWAKE0# W_DISABLE2# 56 WLAN_OFF# PCH_BT_OFF# 8
3/17 SDV Add AOAC Function wei R57 1 @ 2 0_0402_5%
57
GND7 W_DISABLE1#
R56 1 @ 2 0_0402_5%
PCH_WLAN_OFF# 8
37,44 LAN_WAKE#
59 58 WLAN_SMB_DATA R58 1 @ 2 0_0402_5%
RSRVD/PETP1 I2C_DATA WLAN_SMB_CLK SMB_DATA_S3 7,18
61 60 R59 1 @ 2 0_0402_5%
RSRVD/PETN1 I2C_CLK SMB_CLK_S3 7,18
63 62
GND8 ALERT# EC_TX_R R89 1 2 0_0402_5%
65 64 EC_TX 44
67 RSRVD/PERP1 RSRVD 66
69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3VS_WLAN
GND9 UIM_POWER_SNK/CLKREQ1#

1
2 71 70 2
73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 R186
RSRVD/REFCLKN1 3.3VAUX3
75 74 100K_0402_5%
GND10 3.3VAUX4
77 76

2
GND15 GND14

ARGOS_NASE0-S6701-TS40

8/16 Update Conn. P/N SP070013200 wei

Optane Memory +VS_SSD

JSSD1 ME@

1 2
GND_1 3.3V_1
3 4
9 PCIE_PRX_DTX_N9 5 GND_2 3.3V_2 6
+3VS +VS_SSD PERN3 N/C_2
9 PCIE_PRX_DTX_P9 7 8
9 PERP3 N/C_3 10
Need short MAX 1.5A 9 PCIE_PTX_C_DRX_N9 11 GND_3 DAS/DSS#/LED1# 12
J14 1 2 @ PETN3 3.3V_3
12 9 PCIE_PTX_C_DRX_P9 13 14
15 PETP3 3.3V_4 16
JUMP_43X79 GND_4 3.3V_5 +VS_SSD
17 18
0.1u_0201_10V

0.1u_0201_10V

0.01U_0201_10V

0.01U_0201_10V
22U_0603_6.3V6-

22U_0603_6.3V6-

9 PCIE_PRX_DTX_N10
19 PERN2 3.3V_6 20
3 3
6K C207

6K C2048

6K C2049

6K C2050

1 1 1 1 1 1 9 PCIE_PRX_DTX_P10
21 PERP2 N/C_4 22
M C137

M C146

GND_5 N/C_5
9 PCIE_PTX_C_DRX_N10 23 24
25 PETN2 N/C_6 26

2
2 2 2 2 2 2 9 PCIE_PTX_C_DRX_P10 PETP2 N/C_7
OPTANE

OPTANE

OPTANE

OPTANE

OPTANE

OPTANE

27 28 R3099
29 GND_6 N/C_8 30
@ 10K_0402_5%
9 PCIE_PRX_DTX_N11
31 PERN1 N/C_9 32
@

9 PCIE_PRX_DTX_P11 PERP1 N/C_10

33 34

1
9 PCIE_PTX_C_DRX_N11 35 GND_7 N/C_11 36
PETN1 N/C_12 R3100 1 2 10K_0402_5%
37 38
9 PCIE_PTX_C_DRX_P11
39 PETP1 DEVSLP 40
OPTANE@
9 PCIE_PRX_DTX_P12 41 GND_8 N/C_13 42
PERN0/SATA_B+ N/C_14
9 PCIE_PRX_DTX_N12 43 44
45 PERP0/SATA_B- N/C_15 46
GND_9 N/C_16
9 PCIE_PTX_C_DRX_N12 47 48
+VS_SSD
9 PCIE_PTX_C_DRX_P12 49 PETN0/SATA-A- N/C_17 50 PLT_RST#
51 PETP0/SATA-A+ PERST# 52 SSD_CLKREQ_Q# R3098 1 2 0_0402_5% SSD_PCIE_CLKREQ# 10
GND_10 CLKREQ#
10 CLK_PCIE_SSD# 53 54 @1 OPTANE@
55 REFCLKN PEWAKE# 56
10 CLK_PCIE_SSD REFCLKP N/C_18
1

R3102 8/24 CPU side 10K PU wei 57

GND_11 N/C_19
58 TP264

10K_0402_5% @ 59 NC NC 60
61 NC NC 62
63 NC NC 64 +VS_SSD
2

65 NC NC 66
SSD_DET# 67 68
9 SSD_DET# SSD_DET# N/C_1 SUSCLK 70
69
PEDET 3.3V_7
71 72
GND_12 3.3V_8 74
1

73
GND_13 3.3V_9
75
10K_0402_5% @ SSD_DET# GND_14
R3101 0--SATA 77
PEG1 PEG2
76
1--PCIE
2

ARGOS_NASM0-S6701-TSH4

4 4

Securiiity Clllassiiifiiicatiiion LC Future Center Secret Data Title

Issued Date 2016/12/14 Decipherii ed Date 2017/12/13 NGFF WLAN&SSD

THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIAI L
AND TRADE SECRET INIFORMATIONII .. THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R &
DDEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIZEII D BY LC FUTURE CENTER NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORII WRITTEII N CONSENT OF LC FUTURE CENTER...
C
EG523 0..2

Dattte::: Tuesday,,, Apriiilll 25,,, 2017 Sheett 40 o ff60

A B C D E
 A B C D E

+USB_VCCA

C55 1 2

+
220U_6.3V_M

C1117 1 2
@ 47U_0805_6.3V6-M
LEFT SIDE USB3.0 PORT x2 C125 1 2
@ 1U_0402_10V6K

+5VALW +USB_VCCA C127 1 2

U2 @ 1U_0402_10V6K
5 1
1 IN OUT JUSB1 ME@ 1
1
C128 2
GND USB30_TX_P1 C126 1 2 0.1u_0201_10V6K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9
1U_0402_6.3V6K 9 USB30_TX_P1
4 3 USB_OC1# 1 StdA_SSTX+
2 44 USB_ON# ENB OCB USB_OC1# 9 USB30_TX_N1 C124 1 2 0.1u_0201_10V6K USB30_TX_C_N1 R96 1 2 0_0402_5% USB30_TX_R_N1 VBUS
@ 8
SY6288D20AAC_SOT23-5 9 USB30_TX_N1 9 R97 1 USB20_P1_R StdA_SSTX-
1 @ 2 0_0402_5% 3
USB20_P1 7 D+
C140
USB20_N1 R93 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
1000P_0201_50V7-K 9 USB20_N1 USB30_RX_R_P1
EMC_NS@ USB30_RX_P1 R94 1 @ 2 0_0402_5% 6 D- GND_2 11
Low Active 2A 2
9 USB30_RX_P1
4 StdA_SSRX+ GND_3 12
USB30_RX_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
9 USB30_RX_N1 StdA_SSRX- GND_5

ALLTO_C190AG-10939-L

09/05 Update USBConn. P/N DC021609011 wei

L13 EMC@
USB30_RX_N1 1 2 USB30_RX_R_N1
1 2

USB30_RX_P1 4 3 USB30_RX_R_P1
4 3
EXC24CH900U_4P USB20_P1_R
+USB_VCCA
USB20_N1_R D12 EMC@
L16 EMC@ USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1
USB30_TX_C_N1 1 2 USB30_TX_R_N1

AZ5725-01F.R7GR_DFN1006P2X2
1 2

2
D11 USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1
D13

1
USB30_TX_C_P1 4 3 USB30_TX_R_P1 AZC199-02S.R7G_SOT23-3 USB30_TX_R_N1 7 7 4 4USB30_TX_R_N1
4 3
EMC@
EXC24CH900U_4P USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1

3 3

2
2 EMC@ 2

2
L8 EMC@ 8
USB20_P1 1 2 USB20_P1_R
1 2 AZ1045-04F_DFN2510P10E-10-9

1
USB20_N1 4 3 USB20_N1_R
4 3
EXC24CH900U_4P
EMC
EMC

+USB_VCCA

C2060 1 2
@ 1U_0402_10V6K

C2059 1 2
@ 1U_0402_10V6K

L30 EMC@ JUSB3 ME@

USB30_RX_N3 1 2 USB30_RX_R_N3
1 2 USB30_TX_P3 C2058 1 2 0.1u_0201_10V6K USB30_TX_C_P3 R311 1 @ 2 0_0402_5% USB30_TX_R_P3 9
9 USB30_TX_P3 9 1 StdA_SSTX+
USB30_RX_P3 4 3 USB30_RX_R_P3 USB30_TX_N3 C2057 1 2 0.1u_0201_10V6K USB30_TX_C_N3 1 @ 2 0_0402_5% USB30_TX_R_N3 8 VBUS
4 3 9 USB30_TX_N3 R311 2 0_0402_5% USB20_P3_R StdA_SSTX-
6 @ 3
EXC24CH900U_4P 9 USB20_P3 USB20_P3 R3103 1 7 D+
USB20_N3 R942 1 @ 2 0_0402_5% USB20_N3_R 2 GND_DRAIN 10
9 USB20_N3 USB30_RX_P3 R3117 1 @ 2 0_0402_5% USB30_RX_R_P3 6 D- GND_2 11
L29 EMC@ 9 USB30_RX_P3 4 StdA_SSRX+ GND_3 12
3 USB30_TX_C_N3 1 2 USB30_TX_R_N3 USB30_RX_N3 R3114 1 @ 2 0_0402_5% USB30_RX_R_N3 5 GND_1 GND_4 13 3
1 2 9 USB30_RX_N3 StdA_SSRX- GND_5

USB30_TX_C_P3 4 3 USB30_TX_R_P3 ALLTO_C190AG-10939-L

4 3
EXC24CH900U_4P
09/05 Update USBConn. P/N DC021609011 wei
L17 EMC@
USB20_P3 1 2 USB20_P3_R
1 2

USB20_N3 4 3 USB20_N3_R
4 3
EXC24CH900U_4P
FOR ESD Close to Connector
D45 EMC@
USB30_RX_R_N3 9 10 1 1USB30_RX_R_N3
USB20_P3_R +USB_VCCA
USB30_RX_R_P3 8 9 2 2 USB30_RX_R_P3
USB20_N3_R
USB30_TX_R_N3 7 7 4 4USB30_TX_R_N3
3

D43 USB30_TX_R_P3 6 6 5 5 USB30_TX_R_P3

AZ5725-01F.R7GR_DFN1006P2X2
AZC199-02S.R7G_SOT23-3

1
EMC@ 3 3
D34

1
8
EMC_NS@
AZ1045-04F_DFN2510P10E-10-9
2
2
1

4 4

Securiiity Clllassiiifiiicatiiion LC Future Center Secret Data Title

Issued Date 2015/08/20 Decipherii ed Date 2016/08/20 USB3.0 PORT (LEFT)

THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIAI L
AND TRADE SECRET INIFORMATIONII .. THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R &
DDEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIZEII D BY LC FUTURE CENTER NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORII WRITTEII N CONSENT OF LC FUTURE CENTER...
C
EG521 0..2

Dattte::: Tuesday,,, Apriiilll 25,,, 2017 Sheett 41 o ff60

A B C D E
 A B C D E F G H

SATA HDD Conn.

1 1

JHDD1
+5VS_HDD
10
SATA_PTX_DRX_P0 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 9 10
9 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 9
9 SATA_PTX_DRX_N0 C67 1 2 0.01U_0201_10V6K 8
7 8 12
1 1 1 1 1 7 GND2
C74 C76 C75 C77 C78 SATA_PRX_DTX_N0 C68 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N0 6
33P_0201_50V8-J 33P_0201_50V8-J 0.1u_0201_10V6K 10U_0805_10V6K 10U_0805_10V6K 9 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 5 6
RF@ RF@ @ 9 SATA_PRX_DTX_P0 4 5
2 2 2 2 2 3 4 11
2 3 GND1
1 2
+5VS +5VS_HDD 1
Need short ELCO_006809610010846
For EMC J3 1 2 @ JUMP_43X79 ME@
12

2 2

+5VS +5V_ODD

Need Short
J4 @
1 2
1 2
JUMP_43X79
10U_0603_10V6K

0.1u_0201_10V6K

1 1
CD@
C85

2 2
C86

FOR 15" 17''

SATA ODD FFC Conn
3 3
SATA_PTX_DRX_P1 JODD2
9 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 1 ME@
9 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 1
15@ C79 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_15 2
SATA_PRX_DTX_N1 SATA_PTX_DRX_N1 15@ C80 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N1_15 3 2
9 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 4 3
9 SATA_PRX_DTX_P1 SATA_PRX_DTX_N1 15@ C81 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_15 5 4
SATA_PRX_DTX_P1 15@ C82 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_15 6 5
7 6
+5V_ODD 8 7
8
9
10 GND1
GND2
HIGHS_FC5AF081-2931H

8/16 Update Conn. P/N SP01001YV00 wei

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDD/ODD CONN

THIS SHEET OF ENGINEERING DRAW ING IS T HE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL
AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D Siiize Document Number Rev
DEPARTMENT EXCEPT AS AUT HORIZED BY LC FUT URE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUT URE CENTER.
Custom
EG521 0.2

Date: T ues day, Apriiilll 25, 2017 Sheet 42 o f 60

A B C D E F G H
 5 4 3 2 1

D D

USB30_TX_N2
9 USB30_TX_N2 USB30_TX_P2
9 USB30_TX_P2

USB30_RX_N2
9 USB30_RX_N2 USB30_RX_P2
9 USB30_RX_P2

+3VALW
+3V_MUX +5VALW +5V_MUX
R133 1 2 0_0402_5% R173 1 2 0_0402_5%
U27 @ VBUS_P0
6 1
+3VS +5VS +5VALW IN OUT VBUS_P0
R134 1 @ 2 0_0402_5% R174 1 @ 2 0_0402_5% 3.3K_0402_1% 1 @ 2 R418 5

VBUS_EN 4
ISET GND 2

TYPE_C_OCP#
3A
EN/ ENB OCB 3

Iset =6800/3.3k=2.06A SY6861B1ABC_SOT23-6

U26 11/16 SIT Reserve Power switch for OPC# flip issue wei
TYPE_C_OCP# 2 2
16

25
G ND 5 2 6
G ND 6 2 7
VBUS_EN 15 OCP_ DET JP1
CC1271 CC1272 ME@

G ND 7 2 8
VBUS_EN 220P_0201_25V7-K 220P_0201_25V7-K
1 1

GND8
C
VMON 17
VMON CC1
12
14
CC1
CC2
A5
B5 +5VALW 1.5A VBUS_P0
24
Power_GND_B12 GND_A1
1
C
CC2 C_RX1_P_C 2 C_TX1_P_C
1 23
SSRXp1_B11 SSTXp1_A2
1
11 MUX_TX2_N C2076 1 2 0.1U_0201_6.3V6-K B3 + C1333 C_RX1_N_C 22 3 C_TX1_N_C
C_TX2_1P/2N 10 MUX_TX2_P C2075 1 2 0.1U_0201_6.3V6-K C_TX2_P B2 C213 150U_B2_6.3VM_R35M SSRXn1_B10 SSTXn1_A3
C_TX2_1N/2P 47U_0805_6.3V6-M @ 21 4
C2068 1 2 0.1U_0201_6.3V6-K USB30_RX_N2_M 4 24 C_RX2_N A10 2 2 VBUS_ B9 VBUS_A4
USB30_RX_P2 C2067 1 2 0.1U_0201_6.3V6-K USB30_RX_P2_M 5 SSRX_1P/2N C_RX2_1P/2N 1 C_RX2_P A11
20 5 CC1
SSRX_1N/2P C_RX2_1N/2P U6 SBU2_B8 CC1_A5
USB30_TX_N2 USB30_TX_N2_M
10Gbps 2:1 MUX C_DM C_DP
C2065 1 2 0.1U_0201_6.3V6-K 6 8 MUX_TX1_N C2073 1 2 0.1U_0201_6.3V6-K A3 19 6
USB30_TX_P2 C2066 1 2 0.1U_0201_6.3V6-K USB30_TX_P2_M SSTX_1P/2N C_TX1_1P/2N MUX_TX1_P 2 0.1U_0201_6.3V6-K C_TX1_P A2 A1 A3 Dn2_B7 Dp1_A6
7 9 C2074 1
SSTX_1N/2P C_TX1_1N/2P VIN1 VO UT1 B3 C_DP C_DM
B1 18 7
C_RX1_N VIN2 VO UT2 Dp2_B6 Dn1_A7
2 B10 C1 C3
C_RX1_1P/2N 3 C_RX1_P B11 VIN3 VOUT3
CC2 17 8
C_RX1_1N/2P VBUS_EN D3 D1 TYPE_C_OCP# CC2_B5 SBU1_A8

GND3
ON OC_F LAGB TYPE_C_OCP# 9

C2 G ND 2
B2 G ND 1
+5V_MUX D2 16 9
ISET VBUS_B4 VBUS_A9
13
VCON_IN C_TX2_N_C C_RX2_N_C

1
FPF2595UCX_WLCSP12 15 10
Realtek SSTXn2_B3 SSRXn2_A10

A2
23 +3V_MUX R604
M1 21 NC 19 523_0402_1% C_TX2_P_C 14 11 C_RX2_P_C

10U_0805_10V6K
22 RP_SEL_M1 RTS5449 5V_IN SSTXp2_B2 SSRXp2_A11

0.1u_0201_10V6K
M0 2 2
RP_SEL_M0 20
C2063 Rset 528 Min 1800mA Type 2000mA Max 2200mA 13 12

C2077
LDO_3V3

2
GND_B1 GND_A12
Rset 469 Min 2025mA Type 2250mA Max 2475mA
0.1u_0201_10V6K
4.7U_0402_6.3V6M

3 1 GND1 2
3 0 GND1 1
2 9 GND1 0
GND9
1 2
18 25 1 1
C2064
CC1273

REXT E-PAD
2

HIGHS_UB11246-15A0C-1H
VBUS_P0

32
R3150 RTS5449-GR_QFN24_4X4 2 1
6.2K_0402_1% VBUS_P0
ClosePin13
1

1
Close Pin19 09/02 Update Type-C Conn. DC021608291 wei

AZ5725-01F.R7GR_DFN1006P2X2
R3155

10U_0805_25V6K

4.7U_0805_25V6-K
200K_0402_1% D38

0.47U_0402_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K
1 1

1
2

C918

C919

C922

C921

C920

C1334
EMC_NS@
Rp configuration VMON

2 1

2 1
2 1

2 1
+3V_MUX +3V_MUX @
2 2

2
2

Rp:1.5A (now) R3149

2
R3139 R3142 10K_0402_1%
10K_0402_5% @ 10K_0402_5%
B
M1 M0 Note B
1

Rp:900mA 0 1 R3144/R3142 mount

1

M1 M0
Rp:1.5A 1 0 R3139/R3143 mount
2

R3144 R4674
Rp:3.0A 1 1 R3139/R3142 mount
@ 10K_0402_5% 10K_0402_5%
1

R943 1 @ 2 0_0402_5% R3135 1 @ 2 0_0402_5%

CC1 C_DP
L23 EMC@ L31 EMC@
1 2 C_DP C_RX1_N 4 3 C_RX1_N_C CC2 C_DM
9 USB20_P2 1 2 4 3

2
+3V_MUX
For C_VBUS C_DM C_RX1_P C_RX1_P_C
D47 EMC_NS@ D48 EMC_NS@
4 3 1 2
power switch enable pin 9 USB20_N2 4 3 1 2
2

EXC24CH900U_4P EXC24CH900U_4P
R3146 R3137 1 @ 2 0_0402_5%
@ 10K_0402_5% R91 1 @ 2 0_0402_5%

Note R3136 1 @ 2 0_0402_5%

Power switch enable pin
1

R944 2 @ 1 0_0402_5%
VBUS_EN L32 EMC@
Low Active R3146 mount L24 EMC@ C_TX1_P 4 3 C_TX1_P_C
C_TX2_N C_TX2_N_C 4 3
2

3 4 AZC199-02S.R7G_SOT23-3 AZC199-02S.R7G_SOT23-3
High Active R3141 mount 3 4

1
R3141
10K_0402_5% 1 2
C_TX2_P C_TX2_P_C 1 2
2 1
2 1
EXC24CH900U_4P
1

EXC24CH900U_4P
C_TX1_N R3138 1 @ 2 0_0402_5% C_TX1_N_C

R3107 2 @ 1 0_0402_5%

+3V_MUX
For C_VBUS R100 2 @ 1 0_0402_5%

PH at CPU side 09/06 wei power switch OCP pin L25 EMC@
C_RX2_P C_RX2_P_C
2

3 4 D36 EMC_NS@ D20 EMC_NS@

R3147 3 4 C_TX2_P_C 9 10 C_TX2_P_C C_TX1_P_C 9 10 C_TX1_P_C
1 1 1 1
@ 10K_0402_5%
C_RX2_N C_RX2_N_C C_TX2_N_C 8 9 C_TX2_N_C C_TX1_N_C 8 9 C_TX1_N_C
2
2 1
1 2 2 2 2
Power switch OCP pin Note
1

C_RX1_N_C 7 7 C_RX1_N_C C_RX2_N_C 7 7 C_RX2_N_C

EXC24CH900U_4P 4 4 4 4
A TYPE_C_OCP# A
Low Active R3147 mount R101 2 @ 1 0_0402_5% 5 5 C_RX1_P_C C_RX2_P_C 6 6
5 5
C_RX2_P_C
C_RX1_P_C 6 6
High Active R3140 mount 3 3
3 3
2

R3140 8 8
@ 10K_0402_5%
AZ1045-04F_DFN2510P10E-10-9
For ESD AZ1045-04F_DFN2510P10E-10-9
1

Securiiitytt Clllassiiifiiiff catttiiion LC Future Center Secret Data Tiiitllle

IIIssued Dattte 2015/08/20//// Deciiiphered Dattte 2016/08/20//// 3D Camera

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF LC FUTURE CENTER... AND CONTAIIINS CONFIIIDENTIIIAL Re v
Siiize Documenttt Numberrr
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CENTER...
Custttom
EG521 0..2

Dattte::: Tuesday,,, Aprrriil 25,,, 2017 Sheettt 43 o ff 60

5 4 3 2 1
 5 4 3 2 1

For ESD For EMI RE1 1 2 0_0603_5% +3VL V20B+

PLT_RST# CLK_PCI_EC RE2 1 2 33_0402_5%
EMC@

1
RE3 1 @ 2 0_0603_5%
1
CE1 CE2
1 Close EC +3VALW
RE261
220P_0201_25V7-K 22P_0402_50V8-J +3VL_EC_R 470K_0402_5%
EMC@ EMC@ +3VL_EC +3VL_EC @
2 2 CE3 1 2 VCOREVCC

2
LE1 1 @ 2 0_0603_5% B+_Track
0.1u_0201_10V6K +3VL_EC All capacitors close to EC

1
1 1

0.1u_0201_10V6K
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
CD
1 1 1 @1 @1 CE4 CE5 +3VL_EC R260

@
1
0.1u_0201_10V6K 1000P_0201_50V7-K 47K_0402_5%
+3VS +3VL_EC_R @
2 2

2
Change RE6 to 0ohm jump

1
D 2 2 2 2 2 2 LE2 1 @ 2 0_0603_5% EC_AGND D

CE1

CE1
CE9
RE5

CE

CE

CE

1
RE6 1 @ 2 0_0402_5% 10K_0402_5%

8
EC_AGND

2
LAN_WAKE#
minimum trace width 12 mil LAN_WAKE# 37,40

114
121
127
26
50
92

74
12

11
3
UE1
+3VS

VCC
VCORE

VSTBY
1 VSTBY2
VSTBY3
VSTBY4
VSTBY5

AVCC
VSTBY(PLL)
VBAT
EC_FAN_SPEED RE10 1 2 10K_0402_5%

EC_FAN_PWM RE11 1 @ 2 10K_0402_5%

WRST# PWR_LED#
RE56 2 @ 1 0_0402_5% 4 24
7 KBRST# KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# 45 LPC_FRAME# 2 10K_0402_5%
RE59 2 @ 1 0_0402_5% 5 RE7 1 @
+3VL_EC 7,32 SERIRQ 2 0_0402_5% LPC_FRAME#_EC SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# 45
RE60 1 6 28
7,32 LPC_FRAME# LPC_AD3_EC BATT_LOW_LED# 45
RE61 1 2 0_0402_5% 7 LFRAME#/GPM5 PWM2/GPA2 29 EC_VCCST_PWRGD ENBKL RE9 1 @ 2 100K_0402_5%
7,32 LPC_AD3 2 0_0402_5% LPC_AD2_EC LAD3/GPM3 PWM3/GPA3 EC_VCCST_PWRGD 11
DE1 1 2@ RE62 1 8 PW M 30
7,32 LPC_AD2 2 0_0402_5% LPC_AD1_EC 9 LAD2/GPM2 PWM4/GPA4 31 EC_FAN_PWM SYS_PWROK 11 CPU_VR_READY 2 10K_0402_5%
RE63 1
7,32 LPC_AD1 LPC_AD0_EC LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 39
RB751V-40_SOD323-2 2 0_0402_5% 10 RE270 1
7,32 LPC_AD0 CLK_PCI_EC LAD0/GPM0 PWM6/SSCK/GPA6 34 EC_VCCST_EN_R BEEP# 30 EC_VCCST_EN EC_CMOS_ON# 2 10K_0402_5%
RE64 1 13 LPC RE54 1 2 RE275 1 @
EC_VCCST_EN 13
1 2 7 CLK_PCI_EC WRST# 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120
LAN_WAKE# 0_0402_5%
RE8 WRST# TMRI0/GPC4 SUSP# EC_LID_OUT# RE277 1 @ 2 10K_0402_5%
1 9 EC_SMI# 15 124 SUSP# 46,54
100K_0402_5%
40 EC_RX
EC_RX 16 ECSMI#/GPD4 TMRI1/GPC6
CE12 EC_TX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66 NTC_V1 39
1U_0402_6.3V6K 40 EC_TX PLT_RST# LPCPD#/GPE6 ADC0/GPI0 67
11,32,37,40 PLT_RST#
22 NTC_V2 39 For PMIC +3VALW +3VL_EC
2 23 LPCRST#/GPD2 ADC1/GPI1 68 BATT_TEMP
BATT_TEMP 52,53
4 EC_SCI# EC_RTCRST#_ON ECSCI#/GPD3 ADC2/GPI2
126 ADC 69 PM_SLP_SUS# 11
IT8586E/AX
GA20/GPB5 ADC3/GPI3 70

1
ADC4/GPI4 71 CPU_VR_READY 59
ADP_I 53 RE273 RE274
ADC5/DCD1#/GPI5 B+_Track
LQFP-128L 72 +3VL_EC 0_0402_5% 0_0402_5%
ADC6/DSR1#/GPI6 73 0_0402_5% 1 2 RE276 PSYS 53,59 @
KSI[0..7] KSI0 ADC7/CTS1#/GPI7
45 KSI[0..7] 58

2
KSI0/STB#

1
KSI1 59 78 SUSWARN# 11
KSO[0..17] KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 RPE4
45 KSO[0..17] SUSACK# 11 RE65
KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC EC_SMB_DA3 1 4
C KSI3 61
KSI3/SLIN# DAC DAC4/DCD0#/GPJ4 81
80 100K_0402_5%
EC_SMB_CK3
C
KSI4 62 ENBKL 33 2 3
KSI5 KSI4 DAC5/RIG0#/GPJ5
63

2
+3VL_EC 64 KSI5 85 EC_ON_GPIO 0_0402_5% 1 2 RE57 2.2K_0404_4P2R_5%
KSI6 EC_ON 39,54,55
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86
KSI7
KSI7 PS2DAT0/TMB1/GPF1 EC_SMB_CK3 PBTN_OUT# 11 +5VALW
KSO0 36 87
EC_SMB_CK1 KSO0/PD0 GPF2 88 EC_SMB_DA3 EC_SMB_CK3 55
RPE2 PAD 1 @ KSO1 37 Int.K/B PS2
EC_SMB_DA1 EC_SMB_DA1 @ IT1 KSO1/PD1 GPF3 89 EC_SMB_DA3 55 USB_ON#
2 3 PAD 1 KSO2 38 1 TE1 @ RE15 1 2 100K_0402_5%
1 4 EC_SMB_CK1 PAD 1 @ IT2 KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 EC_LID_OUT#
90
PAD 1 @ IT3 KSO4 40 KSO3/PD3 PS2DAT2/GPF5 EC_LID_OUT# 45
2.2K_0404_4P2R_5% PAD 1 @ IT4 KSO5 41
KSO4/PD4
EXTERNAL SERIAL FLASH 96 +3VL_EC
IT5 KSO5/PD5 GPH3/ID3 97 CAPS_LED# 45
KSO6 42 PCH_PWR_EN 46,55
KSO6/PD6 GPH4/ID4
KSO7 43 98 EC_BKL_EN 45
44 KSO7/PD7 GPH5/ID5 99
KSO8 PCH_PWROK 11
+3VS KSI7 PAD 1 KSO9 45 KSO8/ACK# GPH6/ID6 SUSP# RE18 1 @ 2 100K_0402_5%
@ IT6
KSI6 PAD 1 KSO10 KSO9/BUSY 101 EC_SPI_CS0#
@ IT7 46
WRST# PAD 1 KSO11 51 KSO10/PE NC1 102 EC_SPI_SI SUSP# RE19 1 2 100K_0402_5%
RPE3 @ IT8 NC2
4 EC_SMB_CK2 KSO11/ERR# EC_SPI_SO
1
EC_SMB_DA2
KSO12 52
KSO12/SLCT SPI Flash ROM 103
NC3 105 EC_SPI_CLK SYSON_R
2 3 KSO13 53 RE21 1 2 100K_0402_5%
KSO13 NC4
For factory EC flash KSO14 54
KSO14 EC_VCCST_EN
2.2K_0404_4P2R_5% KSO15 55 RE269 1 @ 2 100K_0402_5%
KSO16 56 KSO15 108 ACIN#
KSO16/SMOSI/GPC3 AC_IN# LID_SW# EC_VCCIO_EN
KSO17 57 UART 109 RE268 1 @ 2 100K_0402_5%
KSO17/SMISO/GPC5 LID_SW# LID_SW# 45

45 ON/OFF ON/OFF 110 82

EC_ON PWRSW# EGAD/GPE1 83 AOAC_ON# 40
RE58 2 @ 1 0_0402_5% 111 SM Bus
EC_SMB_CK1 XLP_OUT EGCS#/GPE2 EC_VPP_PWREN VDDQ_PGOOD 55 Add to fix Reset&PWRGD test fail issue
52,53 EC_SMB_CK1 115 84 EC_VPP_PWREN 55
EC_SMB_DA1 116 SMCLK1/GPC1 EGCLK/GPE3
52,53 EC_SMB_DA1 PECI_EC SMDAT1/GPC2 VDDQ_PGOOD 1 CE51
2
RE24 1 2 43_0402_5% 117 GPIO 77 0.01U_0201_10V6K
4 H_PECI SMCLK2/PECI/GPF6 GPJ1 EC_MUTE# 30
37 LAN_PWR_ON# 118 100 GPG2
EC_SMB_CK2 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106
7,39 EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 104 EC_CMOS_ON# 33 PM_SLP_S4#
95 CE50 1 2 EMC_NS@
+3VL 7,39 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 SYSON_R ME_FLASH 8
RE271 1 2 0_0402_5% SYSON 1000P_0201_50V7-K
DTR1#/SBUSY/GPG1/ID7 119 BKOFF# SYSON 55
CRX0/GPC0 BKOFF# 33 EC_VCCIO_EN PM_SLP_S3#
123 RE55 2 @ 1 0_0402_5% EC_VCCIO_EN CE21 1 2 EMC_NS@ 1000P_0201_50V7-K
112 CTX0/TMA0/GPB2 18 13
RE27 1 @ 2 0_0402_5%
VSTBY0 RI1#/GPD0 PM_SLP_S3# 11,13
RE272 1 2 0_0402_5% 125 21 PM_SLP_S4#
B 59 EC_VR_ON GPE4 RI2#/GPD1 76 11 B
WAKEUP NOVO# 45 SYSON CE13 1 2 EMC_NS@ 1000P_0201_50V7-K
PM_SLP_S3# DE2 1 2 TACH2/GPJ0 48
@ RB751V-40_SOD323-2 TACH1A/TMA1/GPD7 EC_FAN_SPEED EC_TS_ON 33
47 EC_FAN_SPEED 39
USB_ON# 33 TACH0A/GPD6 19 @1 TE3
41 USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 EMC Request

2
11 DPWROK_EC 35 GPIO 20 NUM_LED# 45
93 RTS1#/GPE5 L80LLAT/GPE7
11 EC_RSMRST# CLKRUN#/GPH0/ID0

PCIE_WAKE# 2 DE3
11,37,40 PCIE_WAKE#

1
CK32KE/GPJ7 RB751V-40_SOD323-2
11 AC_PRESENT 128
CK32K/GPJ6 Clock
+3VL @
PM_SLP_S4#

RE34 1 2 H_PROCHOT# 4,55

RE35 1 @ 2 10K_0402_5% ON/OFF 53,59 VR_HOT# 0_0402_5%
AVSS
VSS1

EC_RTC_RST# 10
VSS

VSS

VSS

VSS

VSS

1
2

RE36 1 @ 2 10K_0402_5% BKOFF# RE38 2 1

IT8586E-AX_LQFP128_14X14 RE267 CE14
1

27
49
91
113
122

75

1 100K_0402_5% LID_SW# 100_0402_5% 47P_0201_25V8-J

EMC_NS@

1
2 QE3 D
EC_RTCRST#_ON

1 2
2
RE40 1 2 10K_0402_5% BKOFF# QE1 D G
EC_AGND H_PROCHOT#_EC 2 +3VL
G @ S 2N7002KW_SOT323-3

3
1
2N7002KW_SOT323-3 S RE50
for EC version update to EX, manual modify PN to FX

2
100K_0402_5%
RE42 @
100K_0402_5%

2
1
+3VL +3VS ACIN# RE262 1 2 0_0402_5%
PECI_EC 11 ACIN#
EMC_NS@ CE15 1 2 47P_0201_25V8-J
+3VL_EC

1
BATT_TEMP EMC_NS@ CE16 1 2 100P_0201_25V8J D QE2
1
A GPG2 RE43 2 @ 1 10K_0402_5% CE19 2 A
G ACIN 53
ACIN# EMC_NS@ CE17 1 2 100P_0201_25V8J 0.1u_0201_10V6K
GPG2 RE44 2 1 10K_0402_5% EC_SPI_CS0# RE45 2 @ 1 0_0402_5% SPI_CS0#
SPI_CS0# 7 NOVO# ON/OFF @ CE18 1 2 1U_0402_6.3V6K 2 S 2N7002KW_SOT323-3

3
GPG2 RE46 2 @ 1 10K_0402_5% @
EC_SPI_SI RE47 2 @ 1 0_0402_5% SPI_SI
SPI_SI 7
when mirror, GPG2 pull high
when no mirror, GPG2 pull low EC_SPI_SO RE48 2 @ 1 0_0402_5% SPI_SO
SPI_SO 7 1
CE48
0.01U_0201_10V6K Title
REC_SPI_CLK E49 2 @ 1 0_0402_5% EMC_NS@ Securiiity Clllassiiifiiicatiiion LC Future Center Secret Data
SPI_CLK SPI_CLK 7 2 Issued Date 2015/08/20 Decipherii ed Date 2016/08/20 EC ITE8586LQFP
THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIAI L
AND TRADE SECRET INIFORMATIONII .. THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R &
DDEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIZEII D BY LC FUTURE CENTER NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORII WRITTEII N CONSENT OF LC FUTURE CENTER...
C
EG521 0..2

Dattte::: Tuesday,,, Apriiilll 25,,, 2017 Sheettt 44 off 60

5 4 3 2 1
 5 4 3 2 1

ON/OFF switch +3VL +3VALW

Novo button NOVO_BTN#

2
SW2

1
R82 R83 4 D24

1
100K_0402_5% 100K_0402_5% AZ5123-01F.R7GR_DFN1006P2X2
@ 5 EMC@
R261 1 0_0402_5% 2

2
NTC325-EKJ-A160T_3P

2
NOVO# D15 2 8/16 Del Power Button wei
44 NOVO#
1 NOVO_BTN#
ON/OFFBTN#
ON/OFF R85 1 @ 2 0_0402_5% 3 @

8/31 Update the P/N SN100008W00 wei

AZ5123-01F.R7GR_DFN1006P2X2
BAT54CW_SOT323-3

1
D25

1
D D

+3VALW +3VL

LID switch

2
2

2
EMC@

2
R111 R114
100K_0402_5% 100K_0402_5%
@

1
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF 1
ON/OFF 44
C1104
U14 100P_0201_25V8J
J5 1 2 @ 1
GND 2
1 LID_SW#
SHORT PADS C1105 3
0.01U_0201_10V6K OUTPUT LID_SW# 44
J6 1 2 @
2 2 +VCC_LID 2
+3VL R264 1 VCC
SHORTPADS 0_0402_5%
AH9247-W-7_SC59-3

K/B Connector KSI[0..7]

KSI[0..7] 44 KB Backlight Connector
KSO[0..17] JKB1
KSO[0..17] 44
+5VS
32 33
ON/OFFBTN# 31 32 GND1 34
PWR_LED# 31 GND2 +5VALW
R285 1 2 0_0402_5% 30 +VCC_KB_LED
EMC_NS@ NUM_LED#_R 30
PWR_CAPS_LED C133 1 2 100P_0201_25V8J R279 1 15@ 2 0_0402_5% 29
44 NUM_LED# KSO17_R 29 Q31
KSO17 R281 1 15@ 2 0_0402_5% 28

1
KSO16_R 28 R265 LP2301ALT1G_SOT23-3
KSO16 R280 1 15@ 2 0_0402_5% 27
27 10K_0402_5% KBL@
KSI1 26 3 1
26

D
25 KBL@
KSI7
25
KSI6 24
24 1 1
KSO9 23

2
23 R266 C1106 C1107

G
KSI4 22

2
22 1 2 10U_0603_6.3V6M 0.1u_0201_10V6K
KSI5 21
21 KBL@ KBL@
KSO0 20 2 2
EMC@ 20 100K_0402_5% 1
C117 1 KSI2 19
2 100P_0201_25V8J 19 KBL@ C1108
KSI3 18
18 0.01U_0201_10V6K
NUM_LED#_R C118 1 KSO5 17
C 2 100P_0201_25V8J 17 KBL@ C
KSO1 16 2
EMC_15@ 8/23 PWR LED function under check KSI0 15
16
15
KSO2 14
KSO4 13
14 To be confirm Pin define
13
KSO7 12

1
12 D
KSO8 11 EC_BKL_EN 2
11 Q32
CAPS_LED# NUM_LED#_R PWR_LED# KSO6 10 44 EC_BKL_EN G
10 2N7002KW_SOT323-3 JKBL1 ME@
KSO3 9 +VCC_KB_LED 1
9 KBL@
KSO12 8 S 2 1
8 1
KSO13 7

3
3 2 6
7 C1109
KSO14 6 4 3 GND2 5
6 0.1u_0201_10V6K
KSO11 5 4 GND1
1

5 KBL@ 1
KSO10 4 2
D22 D23 D46 4 C1110 CVILU_CF50041D0RN-10-NH
1

KSO15 3
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 CAPS_LED# 3 0.1u_0201_10V6K
EMC@ R275 1 2 0_0402_5% CAPS_LED#_R 2
EMC@ EMC_15@ 44 CAPS_LED# PWR_CAPS_LED 1 2 @
2
+3VALW R84 1 1
2
200_0402_1%
2

CVILU_CF32321D0RONH
ME@
2

8/31 Update KBL Conn. P/N SP011608241 wei

For EMC

Finger Print Connector TP/B Connector

+3VS TP_PWR
FP_PWR
To be confirm Pin define R141 1 2
0_0402_5%
+3VS
JFP1 JTP1 ME@

0.1u_0201_10V6
1
R3120 1 2 1 R4675 1 2 0_0402_5% EC_LID_OUT#_R 1
USB20_N4 R3122 1 FP@ 2 0_0402_5% USB20_N4_CONN 44 EC_LID_OUT#
0_0402_5% 2 1 R4676 1 2 0_0402_5% TP_INT# 2 1 7
9 USB20_N4 USB20_P4 R3121 1 FP@ 2 0_0402_5% USB20_P4_CONN 3 2 8 PCH_TP_INT# 3 2 GND1

K C114
FP@ 9 USB20_P4 3
4 2 TP_I2C_SDA0 4 3 8
0.1u_0201_10V6

1 4 8 TP_I2C_SDA0 TP_I2C_SCL0 GND2

5 5 4
6 5 8 TP_I2C_SCL0 6 5
6 TP_PWR 6
FP@ 7
K C2061

2 8 7

100P_0201_25V8

100P_0201_25V8
ELCO_04-6809-606-110-846-+

EMC_NS@

EMC_NS@
USB20_N4_CONN 8 1 1
9
10 GND1 TP_I2C_SCL0
USB20_P4_CONN GND2 TP_I2C_SDA0 2 2

C115

C116
J

J
B B
HIGHS_FC5AF081-2931H

2
3

DT1
DT2
EMC_NS@
EMC_NS@
8/23 Update FG Conn. P/N SP01001YV00 wei
11/16 SIT change to 6Pin I2C interface T/P wei

AZC199-02S.R7G_SOT23-3

1
AZC199-02S.R7G_SOT23-3
For EMC
1

9/7 Add for ESD wei

BATT_LOW_LED#
44 BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5% +3VALW
L-C192JFCT-LCFC_SUPER_AMBER
1

D18
1

AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
2
2

BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5% +5VALW

44 BATT_CHG_LED#
L-C192WDT-LCFC_WHITE
1

D19
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@
2
2

A A

PWR_LED#
PWR_LED# 2
44 PWR_LED# LED4 1 R4672 1 2 1.5K_0402_5% +5VALW
1

L-C192WDT-LCFC
D16
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@

PWR_LED Change to M/B (310->320) 08/17

2
2

Securiiittty Clllassiiifffiiicatttiiion LC Future Center Secret Data Tiiitllle

IIIssued Dattte 2015///08///20 Deciiiphered Datett 2016///08///20 onn.

KBD/PWR/IO/LED/TP Conn.
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF LC FUTURE CENTER... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SEC RET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Documenttt Numberrr Rev
DEPARTMEN T EXCEPT AS AUTHORIIIZED BY LC FUTUR E CENTER NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CENTER...
Custttom
EG521 0..2

Datt e:: Tuesday,,, Aprrriiill 25,,,2017 Sheettt 45 offf 60

5 4 3 2 1
 A B C D E

1 1

+3VALW
+5VALW

1 1 1
C2078 C2080 C2079
0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K
@ @ @
2 2 2

EMC

+5VALW
+3VALW Need short +3VALW_PCH +1.8VALW +1.8VS
2 2
J7 @ Q35 0.6A
1

1 2
1 2 1

D
3
R155
100K_0402_5% JUMP_43X79 LP2301ALT1G_SOT23-3 1
1
@

C201
0.1u_0201_10V6K

C203
0.1u_0201_10V6K
G
1
2

2
C1103
PCH_PWR_EN#_R R158 1 @ 2 100K_0402_5% PCH_PWR_EN#
22U_0603_6.3V6-M LP2301ALT1G_SOT23-3 Id=3.2A
@ 2 2
2 1 1
Q29 3 1 @

C204
0.1u_0201_10V6K

C205
0.1u_0201_10V6K
1

Q30 D SUSP 1 2
PCH_PWR_EN 2 R201 0_0402_5%
44,55 PCH_PWR_EN 1 2 2
G C130

2 G

1
0.01U_0201_10V6K 1
@ S 2N7002KW_SOT323-3 @ R202

C202
0.1u_0201_10V6K
3
1

2 @ 470K_0402_5%

R162 PCH_PWR_EN#_R 2

2
100K_0402_5%
@ 1
2

C131
0.1u_0201_10V6K
@

1
2
R87
100K_0402_5%
@
8/29 Add +1.8VS Circuit for Audio wei

2
3 3

+5VLP +5VALW
For DisCharge
1

R156 R157 +0.6VS +2.5V_DDR

100K_0402_5% 100K_0402_5%
@ 1

1
2

R159 R278
SUSP 47_0603_5% 200_0402_5%
34 SUSP
@ @
2

2
1

1
Q10 D D Q11 D Q33
2 2 SUSP 2 SUSP
44,54 SUSP# G G G

S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3

3

3
@ @

4 4
08/29: Need double check enable signal and the resistance

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DC V TO VS INTERFACEE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
EG521 0.2

Date: T uesday, Apriiilll 25, 2017 Sheet 46 o f 60

A B C D E
 5 4 3 2 1

VIN
EMC@
HCB2012KF-121T50_0805
JDCIN1 PF101 PL101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 3 7A_24VDC_ F1206HI7000V024TM EMC_NS@
GND2 4
HCB2012KF-121T50_0805

1000P_0201_50V7-K
GND3 5

470P_0201_50V7-K

470P_0201_50V7-K
1000P_0201_50V7-K
GND4 PL102
6

EMC@ PC102
1 2
GND5

1
2

2
1
D D

EMC@ PC103
EMC@ PC101

EMC@ PC104
7
GND6

2
1

1
2
HIGHS_PJSS0026-8B01H
ME@

+3VL

1
PR102
1.5K_0402_1%

VCCRTC 2
1

PR103
C C
45.3K_0402_1%
RTC_VCC
2

1
JRTC1
3 2 PR101 1 1
2 1
PD101 1K_0603_5% 3 2
2

@ BAT54CW _SOT323-3 4 GND1

PC105 GND2
1U_0402_6.3V6K
1

HIGHS_WS33020-S0351-HF
ME@

RTC_VCC 20MIL
+3VL 20MIL
VCCRTC 20MIL

B B

No charge RTC with 35mm cable

RTC Battery for GCM BOM

(2nd source and quoted price )

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 e

PWR-DCIN / RTC charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Siiize Document Number
r R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
CG411 0.1

Date: T uesday, Apriiilll 25, 2017 Sheet 51 o f 60

5 4 3 2 1
 5 4 3 2 1

VBAT
D JBATT1
EMC@ BATT+ D
HCB2012KF-121T50_0805
1 PL201
1
2 1 2
2 EC_SMCA
9
10
GND1 3
3
4 EC_SMDA
PR202 1
1
2100_0402_1%
2
EC_SMB_CK1 44,53
EC_SMB_DA1 44,53 1 2 2S1P polymer battery
GND2 4
5
5
6
PR201 100_0402_1%
PL202
voltage level: +6V ~
6
7
7 HCB2012KF-121T50_0805 8.4 V

2
8 EMC@
8

1
PC201 PC202
ME@ 1000P_0201_50V7-K 0.01U_0201_25V6-K
EMC@ EMC@

2
SUYIN_125022HB008M202ZL

PD201
AZC199-02S.R7G_SOT23-3

1
EMC_NS@

PR209
1 2
+3VALW
100K_0402_1%

PR213
C BATT_TEMP_IN 1 2 C
BATT_TEMP 44,53
10K_0402_5%
1
1

PD202
AZ5215-01F_DFN1006P2E2
EMC_NS@
2
2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 OTP

PWR-BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCIILOSED TO ANY THIRID PARTY WITIHOUT PRIOI R WRITI TEN CONSENT OF LC FUTURE CENTER...
Custom
CG411 0.1

Date: T uesday, Apriiilll 25, 2017 Sheet 52 o f 60

5 4 3 2 1
 5 4 3 2 1

AON6414AL_DFN8-5 PQ312
PQ311
AON7408L_DFN8-5 N2
N1
PR301
VIN 1 1 PJ301 @ 0.01_1206_1%
2 2 JUMP_43X118 V20B+
5 3 3 5 1 2 1 4
12
2 3
D D

10U_0603_25V6-

10U_0603_25V6-
470P_0201_50V7

4700P_0402_50V7

6800P_0402_25V7
220P_0402_50V

470P_0402_50V

680P_0402_50V
0.022U_0402_25V
PC301

0.01U_0201_25V6-
1

1
1 4

PC303

PC304
EMC_NS@

EMC_NS@

EMC@ PC329

EMC@ PC330

EMC@ PC331

EMC@ PC332

EMC@ PC333

EMC@ PC334
PC302

1 2

1 2

2 1

2 1

2 1

2 1

2 1

2 1
PR302

2
4.7_0603_5%

7K

7K

7K

5
0.1U_0201_25V6-K

M
-K

7K

-K

-K
2

K
PC305 PQ314
AON6324_DFN8-5
1 2

BQ24780_BATDRV 4

2
PC306
PC307 0.1U_0201_25V6-K

1
1U_0603_25V6K

3
2
1
2
PR303
499K_0402_1% PC308
0.01U_0201_25V6-K

1
VIN BATT+

2
BAT54CW_SOT323
PD301
V20B+

3
PR313 PR315 :432K and 64.9k

2200P_0201_25V7
-3
VIN

10U_0805_25V6
1

2
10U_0805_25V
PC313
change to 43k and 7.15k.

EMC@ PC310
4.02K_0603_1%
4.02K_0603_1

PC314
PR310

PR31

AC

AC

1 2

1 2
N
P
vin detect volatege level:16.8V

1
2
1

PC309:0.1u change to 0.01u

5
PR314 BQ24780_VDD
2

1
PR313 10_1206_5%

6K
decrease ACDET deassert time
C C

-K

K
%

7.15K_0402_1% 1U_0603_25V6K

ACN
ACP
1 2 43K_0402_1% PC315

1
PR315 780_VCC 28 24 1 2 PQ316
21

2
VCC REGN 2.2U_0603_10V6-K PC316 4
1 2 ACDET 6 AON7408L_DFN8-5
PC309 ACDET PR316 PC318
0.01U_0402_25V7K 25 BST_CHG1 22 1
BTST 2.2_0603_5% PR317

3
2
1
BQ24780SRUYR_QFN24_4X4 0.047U_0603_16V7K 0.01_1206_1%
3 26 DH_CHG PL302 BATT+
CMSRC HIDRV
1 2 CHG 1 4
2 PR339 @120K_0402_1% 4 4.7UH_PCMB063T-4R7MS_5.5A_20%
ACDRV

1
2 3

5
27 LX_CHG
BQ24780_VDD 100K_0402_1% 2 PR324 @1 PHASE PR321
2.2_0805_5%

10U_0805_25V6
2
ACIN_R

2
PR325 1 2 0_0402_5% 5 EMC_NS@

10U_0805_25V
PC319
44 ACIN ACOK

PC320
PR320 1 2 0_0402_5% EC_SMB_DA1_R 11

1
1
SDA 23 DL_CHG

1 2
44,52 EC_SMB_DA1 PU301 PQ317 4
LODRV
PR322 1 2 0_0402_5% EC_SMB_CK1_R 12 22 AON7408L_DFN8-5 PC321

6K
SCL GND

K
44,52 EC_SMB_CK1 1000P_0402_50V7K

2
EMC_NS@

3
2
1
PR323 1 2 0_0402_5% ADP_I_R 7 29
44 ADP_I IADP PAD

0.1U_0201_25V6

0.1U_0201_25V6
IDCHG 8 18 BQ24780_BATDRV

PC322

PC323
IDCHG BATDRV

1 2

1 2
9 PR338 10_0603_5% 1
59 Psys PMON 17 2
BATSRC
SRP_R
2

20 2 1

-K

-K
100P_0201_25V

100P_0201_25V

SRP
SRP 10_0603_5%

0.1U_0201_25V6
10 PR328
20K_0402_1%

44,59 VR_HOT# PROCHOT#

2

2
PC324

PC325

PR340

PC327
1

100P_0201_25V

13
CMPIN

1
BATPRES#
TB_STAT#
@ 14
PC341
1

CMPOUT
8J

8J

19 SRN_R 2 1 SRN
1

B SRN 10_0603_5% B

-K
ILIM 21 PR329
ILIM
8J

PR330

16

15
0_0402_5%
1

1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
PR331 14.7K_0402_1%
316K_0402_1% PR332
1
0.1U_0201_25V6
PC328

PR333
1 2

100K_0402_1%
2
-K

A A

Securiiity Clllassiiifiiicatiiion LC Future Center Secret Data Title

Issued Date 2015/08/20 Decipherii ed Date 2016/08/20 PWR-CHARGER

THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIAI L
AND TRADE SECRET INIFORMATIONII .. THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R &
DDEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIZEII D BY LC FUTURE CENTER NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORII WRITTEII N CONSENT OF LC FUTURE CENTER...
C
CG411 0..1

5 4 3 2
 5 4 3 2 1

V20B+
+5VLP
@
1.5A 2
PJ3501
+3VALW_VIN
21
1
PU3501 Vout=3.3V± 5%

25
LV5083AGQUF_UQFN36_5X4
Vset=3.37V± 1.5%

0.1U_0201_25V6
JUMP_43X79

1
1
EMC@
PR3511 PC3541

10U_0805_25V

10U_0805_25V
PC3535
+3VALW

VDDSW
3 +3VALW_BS 1 2 1 2 OCP=12A

PC3534

PC3536
BOOT1

2 1
11 10_0603_5%

2
2
VIN1
D
1 +3VALW_LX
0.1U_0603_25V7-M
1 2 +3VALW_P 2
PJ3502
1 8A OVP=(1.15~1.25)*Vout D
PR3507
LX1_1 2 21
UVP=(0.55~0.65)*Vout

-K
0_0402_5% PL3501

6K

6K
+3VALW_EN LX1_2

22U_0603_6.3V6-

22U_0603_6.3V6-

22U_0603_6.3V6-

22U_0603_6.3V6-
1 2 10 35 1.5UH_PCMB053T-2R2MS_5.5A_20% JUMP_43X79
39,44,55 EC_ON EN1 LX1_3 @
Fsw=500Khz

1
@ 6 +3VALW_P

PC3539

PC3543

PC3544

PC3542
VOUT1

2 1
+3VALW_PG

21

21

21
PC3537 9
0.1U_0201_25V6-K PGOOD1 +3VALW

2
PC3538
4

M
V20B+ 1 2 7
VBYP3
VCC1 +3VLP
@ 1U_0402_25V6-K 100mA
2.5A PJ3503 5 1 2 +3VL
2
21
1 +5VALW_VIN LDO3 PC3545 +3VLP @
4.7U_0603_6.3V6K PJ3505

0.1U_0201_25V6-K
JUMP_43X79 2 1
21

1
PR3512 PC3554

EMC@

10U_0805_25V

10U_0805_25V
PC3546

PC3547

PC3548
14 22 +5VALW_BS 1 2 1 2
2 1 VIN2 BOOT2 JUMP_43X39 +5VALW

2 1
2.2_0603_5%
+3VALW

2
23
LX2_1 24 +5VALW_LX
0.1U_0603_25V7-M
1
PL3502
2 +5VALW_P
PJ3504
2 1
8A Vout=5V± 3%
PR3510 21
LX2_2 36
0_0402_5% 1.5UH_PCMB063T-2R2MS_8A_20% Vset=5.1V± 1.5%

6K

6K
+3/5VALW_EN LX2_3

22U_0603_6.3V6-

22U_0603_6.3V6-

22U_0603_6.3V6-

22U_0603_6.3V6-
1 2 15 JUMP_43X79
EN2
OCP=12A

1
[44,62,66] EC_ON 19 +5VALW_P @
VOUT2

PC3555

PC3552

PC3553

PC3551
OVP=(1.15~1.25)*Vout
1

21

21

21
+5VALW

2
2

PC3549 16
PGOOD2
UVP=(0.55~0.65)*Vout
2
100K_0402_5

100K_0402_5

0.1U_0201_25V6-K
PR3513

M
PR3514

@
PC3550 VBYP5
21 Fsw=500Khz
1

1 2 18 +5VLP
%

@
1

VCC2
ALW_PWRGD 55 100mA

1 +3VALW_LX

1 +5VALW_LX
1U_0402_6.3V6-K 20 1 2
G
+3VALW_P

LDO5
+3VALW PC3559
4.7U_0603_6.3V6K
C 33 C
VINSW1
22U_0603_6.3V6-

@ +3VS
PJ3506 PR3508 PR3509
29 +3VS_SW 1 2 2.2_0805_5% 2.2_0805_5%
PC3566

VOUTSW1 12
2 1

22U_0603_6.3V6-
EMC_NS@ EMC_NS@
JUMP_43X79
31 3VS_SS

1+5VALW_SN 2
Need Short

PC3564
2 1
SS1

1 +3VALW_SN 2
M

2
1 2 +3VS_EN 30
[44,62,66] SUSP# PR3517 ENSW 1 PC3562
0_0402_5% +5VALW 2200p_0402_25V7-K @ +5VS

M
1
PJ3507
34 28 +5VS_SW 1 2
VINSW 2 VOUTSW2 1 2
22U_0603_6.3V6-

PC3530 PC3533
1 2

22U_0603_6.3V6-
1U_0402_25V6-K JUMP_43X79 PC3532 1000P_0402_50V7K

2
26 5VS_SS 1000P_0402_50V7K EMC_NS@
PC3565

2
SS2
2 1

EMC_NS@

PC3563
2 1
PGND_2

PGND_1

AGND_2

AGND_3

AGND_1
27
ENSW2 PC3561

1 2
2200p_0402_25V7-K
M

1 2 +5VS_EN

M
0_0402_5%
8
13

12

17

32
2

PR3518
PC3531
1U_0402_25V6-K
1

B B

A A

Securiiity Clllassiiifiiicatiiion LC Future Center Secret Data Title

Issued Date 2015/08/20 Decipherii ed Date 2016/08/20 PWR_3VALW/5VALW

THISI SHEET OF ENGINI EERINI G DRAWINIIG ISITHE PROPRIEII TARY PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIAI L
AND TRADE SECRET INIFORMATIONII .. THISI SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIIONIOF R &
DDEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIZEII D BY LC FUTURE CENTER NEITHII ER THISI SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISICLOSED TO ANY THIRI D PARTY WITHI OUT PRIORII WRITTEII N CONSENT OF LC FUTURE CENTER...
C
CG411 0..1

Dattte::: Tuesday,,, Apriiilll 25,,, 2017 Sheettt 54 o ff60

5 4 3 2 1
 5 4 3 2 1

PMIC_VCC PR521 1 2 0_0402_5%

EC_ON 39,44,54

PR522
0_0402_5%
D 1 2 +3VALW D
ALW _PW RGD 54
+5VALW @

+5VLP PR502 @
1 2
10_0603_5%
VDDQ_EN
PR501 1 2 0_0402_5% PR520

100K_0402_5%
44 SYSON 1 2

PMIC_EN

1
10_0603_5%

PR513
R_0402
VTT_E N
PR503 1 2 0_0402_5% PC500 1
5 CPU_D RAMPG_C N TL 2
PR505
+1.8VALW _L_EN VD D Q_P 1 2
PR504 1 2 2.2U_0603_6.3V6K

2
0_0402_5%
10_0402_5%

VSYS_PMIC
+1.0VALW _EN
PR506 1 2 0_0402_5% PC502

1 2
44,46 PC H_PW R_EN 0.1u_0201_10V6K

PR507 2 1 +1.8VALW _B_EN

1M_0402_5%

41
EC _VPP_PW REN 2 +2.5V_DDR_EN PU500

9
27
PR508 1
44 EC _VPP_PW REN 0_0402_5%

GND
PMI C _EN
VD D Q_PGOOD 44

VSYS

VCC
+2.5V_DDR_EN 29 PMIC_SMB_D AT1 PR510 1
25

28
2 0_0402_5%

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
EN_LD O1 SDA EC_SMB_DA3 44

2
PC504

PC506

PC507

PC503

PC508
+1.8VALW _L_EN 1 PMIC_SMB_CLK1
EN_LD O2 S CL 26 PR511 1 2 0_0402_5% EC_SMB_CK3 44
+1.0VALW _EN 11 PMIC_ALERT#

1
E N _V 1P0A T_ALE R T_B 24 PR512 2 1 @ 0_0402_5% H_PROC H OT# 4,44
@ @ @ @ @
+1.8VALW _B_EN 16 +1.0VALW _PG
22 1 PAD @ PTC501
E N _V 1P8A POK_V1P0A
VDDQ_EN +1.8VALW _B_PG PAD @ PTC502
31 21 1
E N _V D D Q POK_V1P8A
2A VTT_E N VD D Q_PGOOD
36 23
EN_VTT P OK _ V D D Q
+5VALW TDC-6A OCP-10A OVP-135%
PJ500 @ 12 PL500 PJ501 @
+1.0VALW _B_VIN LX_V1P0A_12 LX_1P0 +1.0VALW _FB

22U_0603_6.3V6-M
2 1 7 13 1 2 2 1
LX_V1P0A_13 2 1
2 1 8 VI N_V1P0A_7 0.47UH_C MMB062D- R47MS_15A_20% +1.0VALW

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
LV5028RPC_VQFN40_5X5
V I N_V1P 0A _8 14
LX_V1P0A_14 15 JUMP_43X7 9
JUMP_43X3 9 LX_V1P0A_15

2 1

2 1
2 1

2 1
PC 510

PC513

PC514
PC511

PC512

PC515

PC516
PC509

2 1
+1.0VALW _FB

2 1

2 1

2 1
0.1u_0201_10V6K 10
VO_V1P0A
EMC _NS@
@ @
17
LX_V1P8A_17

LX_1P0
19 18
VI N_V1P8A_19 LX_V1P8A_18

20
VO_V1P8A_20
C C
UG_VD D Q

1
33
+1.2V_P 38 U G A TE_V D D Q
PC 5171 2 10U_0603_10V6K PR526 PC518 PR525
VI N_VTT 32 BST_VD D Q 1 2 2 1 4.7_0603_5%
B O O T_V D D Q
PJ508 @ 1 EMC_NS@
2 39 0_0603_5% 0.1U_0603_25V7- M
+0.6VS 2 1 VTT 34
LX_VDDQ
P H A S E_V D D Q
2A

1 2
22U_0603_6.3V6-M
JUMP_43X39 LG_VDDQ
40 35

PC519
VSNS_V TT LGATE_VD D Q

2 1
PC534
+1.2V_P
PR515 @ 37 1200P_0402_50V7-K

2
30 V S N S _V D D Q EMC_NS@
1 2
600mA
C S _V D D Q
33K_0402_1%
1A PJ502 @ PJ503 @
2 1 +2.5V_DDR_VI N 5 6
+2.5V_P 2
1
+3VALW 2 1 V I N_LD O 1 LD O 1 2 1 +2.5V_DDR
PC521 1 2
JUMP_43X3 9 2 1 JUMP_43X3 9
PC520 22U_0603_6.3V6-M
600mA
600mA PJ504 @ 1
10U_0603_10V6K
LD O 2
3 +1.8VALW _L_P 2
PJ505 @
2 1
1
+1.8VALW
2 +1.8VALW _L_VIN 4
+3VALW 2 1 VI N_LD O2 2
FB _LD O 2 JUMP_43X39

22U_0603_6.3V6-M
105K_0402_1%
JUMP_43X39

PR516
PC523

PC522
2 1

2 1
10U_0603_10V6K

+1.8VALW_L_FB
2A

1
PJ506
VD D Q_P
2 1
2 1 V20B+

5
JUMP_43X3 9

0.1U_0201_25V6-K

10U_0805_25V6K

10U_0805_25V6K
@

EMC@ PC524

1
PC525

PC526
2 1
PQ500
UG_VDD Q 4

2
2
PR517 AON7408L_DFN 8-5
75K_0402_1% TDC-6A OCP-10A OVP-120%

3
2
1
PJ 507
PL501
LX_VDDQ 1 2 +1.2V_P 2
1
0.47UH_C MMB062D- R47MS_15A_20% 2 1
+1.2V
JUMP_43X7 9

22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M
AON7506_D FN @ @

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PR518 @

2 1

2 1

2 1
B 2.2_0805_5% B

PC530

PC531
PC527

PC528
PC535

PC529

2 1
2 1

2 1
PQ501 EMC_NS@
LG_VDDQ 4

2
1
PC533
1000P_0402_50V7K

3
2
1

2
EMC_NS@

A A

Securrriitytt Clal ssiifffiicatioitt n LC Futtture Centtter Secrettt Dattta Tiitttllle

IIIssued Dattte 2015/0// 8/2// 0 Deciiipherrred Dattte 2016/0// 8/2//0 LW/1.8ALW

PWR PMIC-DDR4/1.0ALW/1.8ALW
THIIISSHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF LC FUTURE CENTER... AND CONTAIIINS CONFIIIDENTIIIAL R ev
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D DEPARTMENT Siiize Documenttt Numberrr
EXCEPT AS AUTHORIIIZED BY LC FUTURE CENTER NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF LC FUTURE CENTER...
D
CG411 0..1

Dattte::: Tuesday,,, Aprrriiill25,,,2017 Sheettt 55 offf 60

5 4 3 2 1
 5 4 3 2 1

SVID Specification
Config +VCCST_CPU

Vmin(V) 0
Vmax(V) 1.52 V20B+ +5VS
Vstep(mV) 5

1
+VCCST_CPU

1K_0402_1%

100_0402_1%
2.2_0603_5%

45.3_0402_1%
1

1
@

PR901

PR902

75_0402_1%
1U_0402_6.3V6K
PC903

PR908

PR910
RFsw Core/GT SA

PR909
2 1
2

2
28.7K 550K 550K

2
2.2U_0603_10V7K
0.01U_0402_25V7K
PC901

PC902
VR_VRMP

VR_VCC
2 1

2 1
D
+VCCST_CPU D
RVboot Core GT SA @ @

1K_0402_1%
2 PR903 1

2 PR904 1
54.9_0402_1%
PR912
10_0402_1%
VR_SVID_DAT_1
35.7K 0V 0V 1.05V @ 2 1

12

13
VR_SVID_DAT 12

2 PR905 1
1K_0402_1%
PR915
0_0402_5%
VR_SVID_ALRT#_1

VCC
VRMP
2 1
VR_SVID_ALRT# 12
PR906
49.9_0402_1%
VR_SVID_CLK_1
2 1
PR911 VR_SVID_CLK 12
1 2 VR_EN 37 38
44 EC_VR_ON EN VR_RDY CPU_VR_READY 44
0_0402_5%
VR_SVID_ALRT#_1 33 31
ALERT# VR_HOT# VR_HOT# 44,53

VR_SVID_CLK_1 34 35
SCLK DRVON DRON 60

VR_SVID_DAT_1 32 22 PW M_1A
SDIO PW M_1A PW M_1A 60

46 29 GT_CSP PR917 1 2 7.5K_0402_1%

PSYS CSP_1A GT_PH 60
44,53 Psys need change to 3900P

PH901

3300P_0402_50V7-K

0.022U_0402_25V7K
GT_CSP_1

PC904

PC905
1 2 1 2
+VCC_GT 12,60
PR919 1 2 3.3K_0402_1% PR918

2 1
2 1
PU901 22K_0402_1% 100K_0402_1%_TSM0B104F4251RZ

1 2 GT_VSP_1 1 2 GT_VSP 24 NCP81218MNTXG_QFN48_6X6

12 VCCGT_VCC_SEN 3.3K_0402_1% VSP_1A
PC906
PR907 1000P_0402_50V7K
1

PR961
PC907
1000P_0402_50V7K PR920 1 2 1K_0402_1% 28 1 2
2

CSN_1A
C C
PC908 1 2 330P_0402_50V7K GT_VSN 25 23 10_0402_1%
12 VCCGT_VSS_SEN VSN_1A TSENSE_1PH PC935

2 1
2200P_0402_50V7K

PR923 PC910
2.7K_0402_1% 1500P_0402_50V6-K GT_TSENSE 1 2 PR922 1 2 8.25K_0402_1%
1 2 GT_COMP_1 1 2 GT_COMP 26 PR921
COMP_1A
0_0402_5%
PC911 1 2 15P_0402_50V8J PH902 1 2 100K_0402_1%_TSM0B104F4251RZ
PC909
Place close to MOSFET

2 1
.1U_0402_10V6-K
PC912 1 2 1000P_0402_50V7K

PR924 1 2 34K_0402_1% GT_ILIM 27

ILIM_1A
16 PW M1_2PH
PW M1_2PH PW M1_2PH 60

PC913 1 2 470P_0402_50V7K GT_IOUT 30

IOUT_1A PW M2_2PH
17 PW M2_2PH 60
PW M2_2PH
PR927 1 2 64.9K_0402_1%

10 IA_CSP1 PR928 1 2 1.78K_0402_1%

CSP1_2PH IA_PH1 59,60
47
12 VCORE_VCC_SEN VSP_2PH 9 IA_CSP2 PR929 1 2 1.78K_0402_1%
CSP2_2PH IA_PH2 59,60
1

PC914

1
1000P_0402_50V7K
PR930 1 2 1K_0402_1% PC915 PC916
2

0.1U_0402_10V7K 0.1U_0402_10V7K

2
PC917 1 2 3300P_0402_50V7-K IA_VSN 48
12 VCORE_VSS_SEN VSN_2PH IA_CSREF
8 PR932 1 2 10_0402_1%
CSREF_2PH +CPU_CORE 12,59,60
PC918 1 2 470P_0402_50V7K

1
1 2 24.3K_0402_1% IA_IOUT 1 PR934 1 2 10_0402_1%
PR933 +CPU_CORE 12,59,60
IOUT_2PH PC919
0.1U_0402_10V7K

2
B B

PR936
86.6K_0402_1%
IA_DIFFOUT 2 7 IA_CSSUM 1 2
DIFFOUT_2PH CSSUM_2PH IA_PH1 59,60
IA_FB 3
FB_2PH
PC920 1 2 680P_0402_50V7K

PR937 PC922 PR938 PC923 PC921 1 2 150P_0402_50V8-J

49.9_0402_1% 470P_0402_50V7K 4.75K_0402_1% 2200P_0402_50V7K PR942
IA_FB_1 2 IA_COMP_1 1 2 IA_COMP 4 PR939
1 2 12 1 86.6K_0402_1%
COMP_2PH 6 IA_CSCOMP 1 2 IA_CSCOMP_1 1 2 1 2
1 2 1K_0402_1% CSCOMP_2PH IA_PH2 59,60
PR940 PC924 1 2 22P_0402_50V8-J 75K_0402_1%
PR941
5 IA_ILIM 1 2 1 2 154K_0402_1%
ILIM_2PH
PH903
PR944 1 2 1.5K_0402_1% PR943 220K_0402_5%_TSM0B224J4702RE
19.6K_0402_1%
PR945
1 2 SA_VSP_1 PC925 1 2 SA_VSP 45
13 VCCSA_VCC_SEN VSP_1B
1.5K_0402_1%
1000P_0402_50V7K
11 IA_TSENSE 1 2 PR947 1 2 8.25K_0402_1%
TSENSE_2PH
1

PC926 PR946
1000P_0402_50V7K 0_0402_5%
1

PR948 1 2 499_0402_1% PH904 1 2 100K_0402_1%_TSM0B104F4251RZ

2

PC927
.1U_0402_10V6-K Place close to MOSFET
2

PC928 1 2 220P_0402_50V7K SA_VSN 44

13 VCCSA_VSS_SEN VSN_1B
PR950 36 PW M_1B
PW M_1B PW M_1B 60
1.5K_0402_1% PC929
1 2 SA_COMP_1 1 2 0.015U_0402_25V7-K SA_COMP 43 40 SA_CSP PR951 1 2 7.5K_0402_1%
COMP_1B CSP_1B SA_PH 60
2700P_0402_50V7-K
8200P_0402_25V7-K

PC930 1 2 15P_0402_50V8J
SA_CSP_1
PC931

PR952 1 2 22K_0402_1% 1 2
PC933
1

+VCCSA 13,60
ROSC_COREGT

PR953 1 2 15.8K_0402_1% SA_ILIM 42

ADDR_VBOOT

ILIM_1B
2 1

A A
ICCMAX_2PH

PH905
ROSC_SAUS

2
ICCMAX_1A

ICCMAX_1B

PC932 1 2 1000P_0402_50V7K PR954 100K_0402_1%_TSM0B104F4251RZ

PR962
1 2 47K_0402_1% SA_Iout 39 41 1 2
IOUT_1B CSN_1B
TAB

PC934 1 2 470P_0402_50V7K
10_0402_1%
49

PC936
2 1

2200P_0402_50V7K
102K_0402_1%

100K_0402_1%
28.7K_0402_1%

28.7K_0402_1%

19.6K_0402_1%

35.7K_0402_1%
2 PR958 1 19
2 PR955 1 14

2 PR956 1 15

2 PR957 1 18

2 PR959 1 20

2 PR960 1 21

Securityii Clasll siifici ationii LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciiiphered Date 2016/08/20 PWR-CPU_CORE
THISII SHEET OF ENGINII EERINII G DRAWINII G ISITHE PROPRIETARII Y PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIALII
AND TRADE SECRET INIFORMATIOII N... THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIOIIIIIIN OF R&D Siiize Documenttt Number R ev
DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITII HER THISII SHEET NOR THE INIFORMATIOII N ITI CONTAINII S
MAY BE USED BY OR DISCIILOSED TO ANY THIRII D PARTY WITIIHOUT PRIOIIR WRITII TEN CONSENT OF LC FUTURE CENTER...
A2
CG411 0.. 1

Dattte::: Tuesday,,, Apriiilll 25,,, 2 0 1 7 Sheettt 59 o ff 60

5 4 3 2 1
 5 4 3 2 1

+VCC_GT
+5VS V20B+

0.1U_0201_25V6-K
PC1001

10U_0603_25V6-M
1 1

10U_0805_25V6K

10U_0805_25V6K

10U_0603_25V6-M
2 1

PC1003

PC1004
1 2 1 2

10U_0603_25V6-M

10U_0603_25V6-M
+ PC1005 +

PC1426
EMC@
PR1001 PC1422

PC1002

PC1425
2

2 1

2 1
1

1
2.2_0603_5% 0.22U_0603_16V7K 68U_25V_M 22U_25V_M

PC1423

PC1424
GT_BST

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2 1
PR1002
2

2
2.2_0603_5% @ @ 2
@

PC1006

PC1007

PC1008

PC1009

PC1010

PC1011

PC1012

PC1013

PC1014

PC1015
PQ1001
PU1001

2 1

2 1

2 1

2 1

2 1

2 1
2 1

2 1

2 1

2 1
1
1 GT_HG 1 @ @
GT_VCC 4 BST
VCC
DRVH
8 +VCC_GT
2 0.15UH_PCME063T-R15MS0R907_37A_20% @ @ @ @
1U_0402_10V6K

59 PW M_1A PW M 7 GT_PH 7 GT_PH 1 2

SW
PC1016

3 PL1001
59,60 DRON EN GT_LG 6
D 5 D
DRVL
2 1

1
9 1 1
FLAG 6 PR1004
GND

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2.2_0805_5% +
+ 220U_D2_2VM_R6M 330U_2.0V_M

1
NCP81253MNTBG_DFN8_2X2 AON6982_DFN8-7 EMC_NS@ PC1027 PC1084

3
4
5

PC1017

PC1018

PC1019

PC1020

PC1021

PC1022
2

2 1

2 1

2 1

2 1
2 1
2 3 2
+VCC_GT 12,59

2
1
PC1029
1200P_0402_50V7-K
GT_PH 59

2
EMC_NS@

V20B+
+5VS

10U_0805_25V6K

10U_0805_25V6K

10U_0603_25V6-M

10U_0603_25V6-M
0.1U_0201_25V6-K
PC1030

2 1

PC1032

PC1033

PC1418

PC1419
1 2 1 2
2

PQ1003

EMC@
PR1007

PC1031

2 1

2 1

2 1

2 1
PR1008 2.2_0603_5% 0.22U_0603_16V7K

IA_BST2
AON6380_DFN8-5
2.2_0603_5%
@ @
PU1002 4
+CPU_CORE
1

NCP81151MNTBG_DFN8_2X2
IA_VCC2 4 1
VCC BST
2 8 IA_HG2
1U_0402_10V6K

3
2
1
59 PW M2_2PH PW M DRVH 0.15UH_PCME063T-R15MS0R907_37A_20%
IA_PH2 1 2
PC1034

3 7
59,60 DRON EN SW
PL1002
IA_LG2
2 1

5
9 5
FLAG DRVL PQ1004

1
6 AON6324_DFN8-5 1 1
+CPU_CORE

330U_D2_2V_Y
GND
PR1010
2.2_0805_5% + 330U_2.0V_M +

PC1036
C C
4 EMC_NS@ PC1056

2
2 2
+CPU_CORE 12,59,60

1
3
2
1
PC1037
1200P_0402_50V7-K IA_PH2 59

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
EMC_NS@

PC1042

PC1043

PC1044

PC1045

PC1046

PC1047

PC1048

PC1049

PC1050

PC1051

PC1052

PC1053

PC1054
2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1
2 1

2 1

2 1

2 1
+5VS

5
PC1038

10U_0603_25V6-M
10U_0805_25V6K

10U_0805_25V6K

10U_0603_25V6-M
1 2 1 2

0.1U_0201_25V6-K
PQ1005
IA_BST1

2 1

1
PC1040

PC1041

PC1421
PR1013 AON6380_DFN8-5

PC1420
2

EMC@
2.2_0603_5% 0.22U_0603_16V7K

PC1039

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2 1

2 1

2 1
PR1014

2
2.2_0603_5% 4 @ @
+CPU_CORE

PC1057

PC1058

PC1059

PC1060

PC1061

PC1062

PC1063

PC1064

PC1065

PC1066

PC1067
PU1003

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1
2 1

2 1
NCP81151MNTBG_DFN8_2X2
IA_VCC1 4 1
VCC BST
1U_0402_10V6K

3
2
1
2 8 IA_HG1
59 PW M1_2PH PW M DRVH
PC1055

0.15UH_PCME063T-R15MS0R907_37A_20% @ @ @ @
3 7 IA_PH1 1 2
21 1

59,60 DRON EN SW
PL1003
IA_LG1
5

9 5
FLAG DRVL

1
PQ1006 1
6 AON6324_DFN8-5 PR1016
GND 2.2_0805_5% + 220U_D2_2VM_R6M
EMC_NS@ PC1035
4

2
23

1 +CPU_CORE 12,59,60
PC1068
3
2
1

1200P_0402_50V7-K
2

B EMC_NS@ IA_PH1 59 B

@
PJ1003
SA_VIN 2 1
2 1 V20B+

10U_0805_25V6K

10U_0805_25V6K
5

0.1U_0201_25V6-K
JUMP_43X79
+5VS

2 1

PC1071

PC1072
PC1069
1 2 1 2

EMC@
PC1070

2 1

2 1
PR1019
2

2.2_0603_5% 0.22U_0603_16V7K PQ1007

SA_BST

PR1020 4
2.2_0603_5% AON7408L_DFN8-5
PU1004
+VCCSA
1

1
3
2
1

SA_VCC 4 BST
0.47UH_PCMB053T-R47MS_13A_20%
VCC 8 SA_HG PL1004
2 DRVH 1 2
59 PW M_1B
1U_0402_10V6K

PW M 7 SA_PH
SW

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PC1073

3 EN
59,60 DRON SA_LG
1

5
DRVL
2 1

PC1076

PC1077

PC1078

PC1079

PC1080

PC1081

PC1082
9 FLAG AON7506_DFN PR1022

2 1

2 1

2 1

2 1

2 1

2 1

2 1
6 2.2_0805_5%
GND
EMC_NS@
NCP81253MNTBG_DFN8_2X2 PQ1008
2

A 4 A
+VCCSA 13,59
1

PC1083
1200P_0402_50V7-K
2

EMC_NS@
SA_PH 59
3
2
1

Securityii Clasll siifici ationii LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciiiphered Date 2016/08/20 PWR-CPU_CORE
THISII SHEET OF ENGINII EERINII G DRAWINII G ISITHE PROPRIETARII Y PROPERTY OF LC FUTURE CENTER... AND CONTAINII S CONFIDII ENTIALII
AND TRADE SECRET INIFORMATIOII N... THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIOIIIIIIN OF R&D Siiize Documenttt Number R ev
DEPARTMENT EXCEPT AS AUTHORIZII ED BY LC FUTURE CENTER NEITII HER THISII SHEET NOR THE INIFORMATIOII N ITI CONTAINII S
MAY BE USED BY OR DISCIILOSED TO ANY THIRII D PARTY WITIIHOUT PRIOIIR WRITII TEN CONSENT OF LC FUTURE CENTER...
A2
CG411 0.. 1

Dattte::: Tuesday,,, Apriiilll 25,,, 2 0 1 7 Sheettt 60 o ff60

5 4 3 2 1
 5 4 3 2 1

CPU Thermal Holex3 GPU Thermal Holex2 PCB Fedical Mark PAD
Close to RJ45 Close to Audio jack
H1 H2 H3 H6 H7
HOLEA HOLEA HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4 FD5 FD6

D 1 D

1
pad_c6p0d4p0 pad_c6p0d4p0 pad_c6p0d4p0 CHASSIS1_GND
pad_ct7p0b8p0d3p0 pad_ct7p0b8p0d3p0

WLAN Standoff
H10 H11 H12 H13 H15 H16
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
C C
pad_ct5p5d2p5 pad_ct7p0b6p0d3p3 pad_ct7p0d3p0 pad_ct7p0d3p0 pad_ct5p0d2p5 pad_cb5p5d2p5

H17
H18
HOLEA
H19
HOLEA H20 H22
Optane Standoff
HOLEA HOLEA HOLEA H21
HOLEA
1

1
1

1
PAD_CT7P0D3P0 PAD_CT7P0D3P0
pad_o2p6x2p9d2p6x2p9n pad_c3p3d3p3n PAD_C2P6D2P6N
pad_ct7p0b6p0d3p3

SH1 ME@ SH2 ME@ SH3 ME@

SH7 ME@ SH8 ME@ SH14 ME@
1 1 1 SH12 ME@
B 1 1 1 B
1 1 1
1 1 1
1
1
SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
SPRING_FINGER_6.2X1.64

SH4 ME@ SH5 ME@ SH6 ME@

1 1 1 SH13 ME@ SH9 ME@

1 1 1 SH10 ME@ SH11 ME@
1 1
1 1
1 1
1 1
SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

SPRING_FINGER_6.2X1.64 SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

SHIELDING_SUL-35A2M_9P2X3P3_1P
USB3.0 Shielding
DDR4 Shielding
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Hole

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number B R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER. EG521 0.2

Date: T u es d ay, April 25, 2 0 1 7 Sheet 49 of 60

5 4 3 2 1