Digital Systems II Chapter 5
Digital Signal Interfacing and Processing.
Introduction
-This chapter introduces analog-to-digital and digital-to-analog
conversion methods for connecting digital and analog systems.
Digital signal processing is a technology that is utilized
extensively in a variety of applications, including automotive,
consumer, graphics/imaging, industrial, instrumentation,
medical, military, telecommunications, and voice/speech.
-Digital signal processing uses mathematics, software, and
hardware to modify analog signals.
Analog-to-Digital Conversion
Sampling and Filtering
An anti-aliasing filter and sample-and-hold circuit are used in
digital signal processing systems. The sample-and-hold function
performs two actions. The first is sampling. Sampling involves
capturing a sufficient number of discrete values at specific places
on a waveform to characterize its shape. Take additional samples
for more precise waveform definition. Sampling transforms an
analog signal into impulses, each indicating its amplitude at a
certain moment.
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Illustration of the sampling process.
Prior to sampling, filter the analog input with a low-pass anti-
aliasing filter. The filter removes frequencies over a sampling
rate-determined limit.
The Sampling Theorem
To fully understand the requirement for an anti-aliasing filter,
understand the sampling theorem: In order to recover a signal,
the sampling rate must be greater than twice the highest
frequency in the signal.
The frequency 𝑓𝑎(𝑚𝑎𝑥) is known as the Nyquist frequency.
𝑓𝑠𝑎𝑚𝑝𝑙𝑒 > 2𝑓𝑎(𝑚𝑎𝑥)
𝑓𝑠𝑎𝑚𝑝𝑙𝑒 = Sampling frequency
𝑓𝑎(𝑚𝑎𝑥) = highest harmonic in the analog signal
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-Under sampling the signal results in frequencies that deviate
significantly from the original signal during recovery. These
“masquerading” signals are called aliases.
-Filtering occurs to eliminate harmonics above the Nyquist
frequency. When analogue signals exceed the Nyquist frequency,
aliasing occurs.
-Aliasing occurs when the sampling frequency is less than twice
the signal frequency.
Applications: Audio sampling rates: 32kHz, 44.1kHz, 48kHz.
Audio signal: 20Hz t0 20kHz. (the number of samples per
second).
44.1 kHz is sufficient for audio CD’s.
A basic illustration of the condition 𝑓𝑠𝑎𝑚𝑝𝑙𝑒 > 2𝑓𝑎(𝑚𝑎𝑥)
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After low-pass filtering, the frequency spectra of the analog and the sampling signals do not
overlap, thus eliminating aliasing error.
-+
Holding the Sampled Value
The sample-and-hold function's second phase is holding. After
filtering and sampling, maintain the sampled level until the next
sample. Time is required for the ADC to process the sampled
value.
Illustration of a sample-and-hold operation.
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Analog-to-Digital Conversion
-The analog-to-digital conversion converts the sample-and-hold
circuit output into binary codes that indicate the amplitude of the
analog input at each sample time.
The first step in converting a signal to digital form is to use a
sample and- hold circuit. This circuit samples the input signal at
a rate determined by a clock signal and holds the level on a
capacitor until the next clock pulse.
A positive half-wave from 0-10 V is shown in blue. The sample-
and hold circuit produces the staircase representation shown in
red.
The second step is to quantize these staircase levels to binary
coded form using an analog-to-digital converter (ADC). The
digital values can then be processed by a digital signal processor
or computer.
What is the maximum unsigned binary value for the waveform?
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10 V = 10102 V. The table lists the quantized binary values for
all of the steps.
-Most signals feature high-frequency noise and harmonics. Most
ADCs pick sampling and filter cutoff frequencies to reconstruct
desired signals without unwanted harmonics or noise.
-Digital audio CDs have adequate sampling rates. For audio CDs,
sampling occurs at 44.1 kHz due to inaudible frequencies over 20
kHz.
What cutoff frequency should an anti-aliasing filter have for a
digital audio CD?
Less than 22.05 kHz.
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Analog-to-Digital Conversion
The analog-to-digital conversion converts the sample-and-hold
circuit output into binary codes that indicate the amplitude of the
analog input at each sample time. With the sample-and-hold
technique, the analog input signal amplitude remains constant
between pulses, allowing for consistent analog-to-digital
conversion instead of analog signal changes between conversion
intervals.
Basic function of an analog-to-digital converter (ADC) (The binary codes and number of bits are
arbitrarily chosen for illustration only). The ADC output waveform that represents the binary
codes is also shown.
Many ICs have two or more channels and execute both
functionalities on a single chip. The AD1871 is a stereo audio
ADC suitable for audio applications.
Quantization
Quantization encodes analog values. As part of the quantization
process, the ADC transforms analog signal values to binary codes.
More bits utilized to represent a sampled value increase accuracy.
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Sample-and-hold output waveform with four quantization levels. The original analog waveform is
shown in light gray for reference.
Two-bit quantization for the waveform
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The reconstructed waveform in the Figure above uses four quantization levels (2 bits). The
original analog waveform is shown in light gray for reference.
Sample-and-hold output waveform with sixteen quantization levels. The original analog
waveform is shown in light gray for reference.
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Four-bit quantization for the waveform in Figure above
The reconstructed waveform in Figure above using sixteen quantization levels (4 bits). The
original analog waveform is shown in light gray for reference.
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Basic block diagram of a typical digital signal processing system.
Methods of Analog-to-Digital Conversion
-As previously discussed, analog-to-digital conversion converts
analog quantities to digital form. Digitizing measured quantities
is essential for processing, presentation, and storage. The next
section examines common types of analog-to-digital converters
(ADCs).
-ADC settings include resolution (bit count) and throughput
(sample rate in sps).
A Quick Look at an Operational Amplifier
Before discussing analog-to-digital converters (ADCs), let's
examine a common ingredient found in most ADCs and DACs.
This component is the operational amplifier (op-amp). A brief
overview of the op-amp.
𝑉𝑜𝑢𝑡 𝑅𝑓
=−𝑅
𝑉𝑖𝑛 𝑖
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Flash (Simultaneous) Analog-to-Digital Converter
-High-speed comparators are used in the flash technique to
compare reference voltages with analog input voltages. A
comparator generates a HIGH when the input voltage exceeds the
reference voltage.
-Figure below illustrates a 3-bit converter with seven comparator
circuits, excluding the all-0s condition. The 4-bit converter needs
15 comparators.
-For conversion to an n-bit binary code, typically 2𝑛 −
1 comparators are needed. Bit count determines ADC resolution.
-One drawback of flash ADC is the need for several comparators
to generate a decent binary integer. Its main benefit is its rapid
conversion time due to high throughput (measured in samples per
second).
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-Resistive voltage-divider circuits set comparator reference
voltages. Each comparator's output feeds the priority encoder. A
pulse on the EN input activates the encoder, which generates a 3-
bit code encoding the input value.
-Binary code is determined by the highest-order input with a
HIGH level.
A 3-bit flash ADC.
The ADC's input accuracy depends on the frequency of enable
pulses and the amount of bits in the binary code. A signal is
sampled whenever the enabled pulse is active.
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Determine the binary code output of the 3-bit flash ADC in Figure
above for the input signal in Figure below and the encoder enables
pulses shown. For this example, 𝑉𝑅𝐸𝐹 = +8 V.
Sampling of values on a waveform for conversion to binary code.
The resulting digital output sequence is listed as follows and
shown in the waveform diagram of the Figure below in relation
to the enabled pulses:
Resulting digital outputs for sample-and-hold values. Output D0 is the LSB of the 3-bit binary
code.
*Related problem
14
If the enabled pulse frequency in Figure above were halved,
determine the binary numbers represented by the resulting digital
output sequence for 6 pulses. Is any information lost?
Dual-Slope Analog-to-Digital Converter
Digital voltmeters and other measuring tools use dual-slope
ADCs. The dual-slope feature is generated by a ramp generator
(integrator). Figure following displays a block schematic of a
dual-slope ADC.
Basic dual-slope ADC.
The figure below shows the dual-slope conversion. Assume the
counter is reset and the integrator output is zero. Assume a
positive input voltage is applied via the switch (SW) specified by
the control logic. If 𝐴1 inverting input is at virtual ground and 𝑉𝑖𝑛
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remains constant, steady current will flow via the input resistor R
and capacitor C.
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-As the current is constant, capacitor C will charge linearly,
resulting in a negative voltage ramp on 𝐴1 output (Figure (a)).
-Once the counter reaches a certain count (n), it resets (R) and the
control logic switches the negative reference voltage (-𝑉𝑅𝐸𝐹 ) to
the 𝐴1 input (Figure b). At this moment, the capacitor is charged
to a negative voltage (-V) corresponding to the input analog
voltage.
-The continuous current from the (-𝑉𝑅𝐸𝐹 ) causes the capacitor to
discharge linearly, as seen in Figure (c). The linear discharge
results in a positive ramp on the 𝐴1 output, commencing at -V
and maintaining a constant slope regardless of charge voltage.
-As the capacitor discharges, the counter advances from RESET.
Time for capacitor discharge to zero relies on initial voltage -V
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(proportional to Vin) as the discharge rate (slope) remains
constant.
When the integrator (𝐴1 ) output voltage hits zero, the comparator
(𝐴2 ) switches to LOW, disabling the counter clock. One
conversion cycle is completed by latching the binary count. The
binary count is proportional to 𝑉𝑖𝑛 as the capacitor discharge
duration is solely influenced by -V, which the counter records.
Successive-Approximation Analog-to-Digital Converter
One of the most popular analog-to-digital conversion methods is
successive approximation. While quicker than dual-slope
conversion, it is slower than the flash approach. Additionally, the
conversion time is constant regardless of the analog input value.
-The input bits of the DAC are enabled (set to 1) one by one,
starting with the most significant bit (MSB).
-Enabling each bit results in the comparator output indicating if
the input signal voltage exceeds the DAC output.
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Successive-approximation ADC.
-When the DAC output exceeds the input signal, the comparator
output is LOW, resetting the register bit. If the output is smaller
than the input signal, the register retains 1 bit.
-The system starts with the MSB, then the next most important
bit, etc. Once all DAC bits are tested, the conversion cycle is
complete.
Implementation: analog-to-digital converter
An integrated circuit successive approximation ADC is the
ADC804. This popular ADC is an 8-bit converter that completes
a conversion in 64 clock periods (100 𝜇s).
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The ADC0804 analog-to-digital converter.
The completion is signaled by the 𝐼𝑁𝑇𝑅 line going LOW.
Sigma-Delta Analog-to-Digital Converter Sigma-delta is a
common analog-to-digital conversion technique, especially in
audio signals in telecommunications. The delta modulation
technique quantizes a difference between two subsequent samples
(increase or decrease).
-Other ADC techniques used sample absolute values. 1Bit delta
modulation quantization.
-Delta modulators provide a single-bit data stream with the
relative number of 1s and 0s indicating the input signal's
amplitude. The signal amplitude is determined by the number of
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1s at a certain clock cycle interval. A maximum of 1s indicates
the highest positive input voltage.
A simplified illustration of sigma-delta analog-to-digital conversion.
Figure below following shows the basic block diagram for the
conversion shown above. The summing 𝛴 point receives the
analog input signal and the converted quantized bit stream from
the DAC in the feedback loop.
After integrating the difference (𝛥) signal from the 𝛴, the 1-bit
ADC adjusts the number of 1s accordingly. This operation aims
to match the entering analog input with the quantized signal upon
return. A comparator and latch comprise the 1-bit quantizer.
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Partial functional block diagram of a sigma-delta ADC.
Testing Analog-to-Digital Converters
Figure shows an ADC testing procedure. A DAC converts ADC
output to analog form for comparison with test input in the test
setup.
One type of sigma-delta ADC.
A method for testing ADCs.
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Analog-to-Digital Conversion Errors
-Again, a 4-bit conversion is used to illustrate the principles. Let’s
assume that the test input is an ideal linear ramp.
Missing Code
The stairstep output in Figure (a) below indicates that the binary
code 1001 does not appear on the output of the ADC. Notice that
the 1000 value stays for two intervals and then the output jumps
to the 1010 value. In a flash ADC, for example, a failure of one
of the op-amp comparators can cause a missing-code error.
Illustrations of analog-to-digital conversion errors.
Incorrect code
The stairstep output in Figure (b) shows that certain binary code
words from the ADC are erroneous. This analysis shows that the
21 -bit line is locked in the LOW (0) condition.
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Offset
Offset conditions are shown in (c). In this situation the ADC
interprets the analog input voltage as greater than its actual value.
A 4-bit flash ADC is shown in Figure (a) below. It is tested with
a setup of testing ADC. The resulting reconstructed analog output
is shown in Figure (b). Identify the problem and the most probable
fault.
*Related problem
Reconstruct the analog output in a test setup like in Figure 12–23
if the ADC in Figure 12–25(a) has comparator 8 stuck in the
HIGH output state. (book)
Methods of Digital-to-Analog Conversion
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Converting digital data to analog is crucial to digital processing.
Digital data is converted to analog form after processing.
Examine the theory of operation and performance characteristics
of two fundamental types of digital-to-analog converters (DACs)
in this section.
Binary-Weighted-Input Digital-to-Analog Converter
In the binary-weighted-input DAC, the input current in each
resistor is proportional to the column weight in the binary
numbering scheme. Accuracy demands precise resistors and
equivalent high-level voltages.
A 4-bit DAC with binary-weighted inputs.
The MSB is represented by the largest current, so it has the
smallest resistor. To simplify analysis, assume all current goes
through 𝑅𝑓 and none into the op-amp.
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If the waveforms representing a succession of 4-bit numbers in
Figure (b) above are applied to the inputs, determine the DAC
output in Figure (a). The least important bit is 𝐷0 .
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Output of the DAC in Figure 12–27.
The R/2R Ladder Digital-to-Analog Converter
The R-2R ladder requires only two values of resistors. By
calculating a Thevenin equivalent circuit for each input, you can
show that the output is proportional to the binary weight of inputs
that are HIGH.
𝑉𝑠
Each input that is HIGH contributes to the output: 𝑉𝑜𝑢𝑡 =
2𝑛−1
where Vs = input HIGH level voltage
n = number of bits
i = bit number
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For accuracy, the resistors must be precise ratios, which is easily
done In integrated circuits.
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Performance Characteristics of Digital-to-Analog Converters
29
Determine the resolution, expressed as a percentage, of the
following:
(a) an 8-bit DAC
(b) a 12-bit DAC
The Digital Signal Processor (DSP)
A digital signal processor (DSP) is a real-time microprocessor
that processes data. Its applications involve processing digital
data representing analog signals. A DSP, like a microprocessor,
features a central process unit (CPU), memory, and several
interface capabilities. Every mobile phone use involves a DSP,
among its numerous applications.
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The DSP has a digital input and produces a digital output.
DSP Programming
-DSPs are usually coded in C or assembly language. DSPs
employ assembly language more than general-purpose
microprocessors due to their quicker execution speed, which is
crucial for most DSP applications.
-DSP programs are typically shorter than regular microprocessor
programs due to their specific uses and high redundancy. DSP
instruction sets are often smaller than microprocessors.
DSP Applications
-Unlike general-purpose microprocessors, DSPs process data
almost immediately. In applications that require rapid DSPs,
delays are not acceptable.
-In addition to mobile phones, DSPs enhance signal quality in
other devices such as computers, video recorders, CD players,
hard disk drives, and digital radio modems. Television uses DSPs.
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DSP is used in television converters to provide compatibility with
different standards.
The DSP in a Cellular Telephone
-A DSP is used in digital cellular phones. Below is a simplified
block diagram of a digital mobile phone. Voice codecs
(coder/decoders) include ADC and DAC features for converting
analog voice signals to digital formats. Most cell phone
applications employ sigma-delta conversion.
-The microphone voice signal is transformed to digital during
transmission by the ADC in the codec and processed by the DSP.
The digital signal is modulated and sent to the radio frequency
(rf) portion from the DSP.
Simplified block diagram of a digital cellular phone.
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The antenna demodulates and converts incoming voice data from
RF to digital. After being processed by the DSP, the digital signal
is converted to the original voice signal via the codec and DAC.
It is amplified and sent to the speaker.
Basic DSP Architecture
As previously mentioned, a DSP is a fast microprocessor
optimized for real-time data processing. The Harvard
architecture, which includes a CPU and two memories (one for
data and one for program), is commonly used in DSPs.
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Many DSPs use the Harvard architecture (two memories).
-DSPs are produced by firms like Texas Instruments, Motorola,
and Analog Devices. DSPs handle fixed-point and floating-point
data. As mentioned in Chapter 2 (book), various systems differ in
how numbers are stored and manipulated.
-All floating-point DSPs can handle fixed-point numbers. In
general, fixed-point DSPs are cheaper and quicker than floating-
point ones. Even within a family, DSP architectural specifics
might differ greatly. Let's examine a specific DSP series to
illustrate its typical organization.
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General block diagram of the TMS320C6000 series DSP.
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