Copyright © 2017 American Scientific Publishers Journal of

All rights reserved Low Power Electronics

Printed in the United States of America Vol. 13, 1–18, 2017

Back to the Future: Digital Circuit Design in the

FinFET Era
Xinfei Guo∗ , Vaibhav Verma, Patricia Gonzalez-Guerrero, Sergiu Mosanu, and Mircea R. Stan
Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, 22904, USA

(Received: 3 June 2017; Accepted: 13 June 2017)

It has been almost a decade since FinFET devices were introduced to full production; they allowed
scaling below 20 nm, thus helping to extend Moore’s law by a precious decade with another decade
likely in the future when scaling to 5 nm and below. Due to superior electrical parameters and unique
structure, these 3-D transistors offer significant performance improvements and power reduction
compared to planar CMOS devices. As we are entering into the sub-10 nm era, FinFETs have
become dominant in most of the high-end products; as the transition from planar to FinFET tech-
nologies is still ongoing, it is important for digital circuit designers to understand the challenges
and opportunities brought in by the new technology characteristics. In this paper, we study these
aspects from the device to the circuit level, and we make detailed comparisons across multiple tech-
nology nodes ranging from conventional bulk to advanced planar technology nodes such as Fully
Depleted Silicon-on-Insulator (FDSOI), to FinFETs. In the simulations we used both state-of-art
industry-standard models for current nodes, and also predictive models for future nodes. Our study
shows that besides the performance and power benefits, FinFET devices show significant reduction
of short-channel effects and extremely low leakage, and many of the electrical characteristics are
close to ideal as in old long-channel technology nodes; FinFETs seem to have put scaling back on
track! However, the combination of the new device structures, double/multi-patterning, many more
complex rules, and unique thermal/reliability behaviors are creating new technical challenges. Mov-
ing forward, FinFETs still offer a bright future and are an indispensable technology for a wide range
of applications from high-end performance-critical computing to energy-constraint mobile applica-
tions and smart Internet-of-Things (IoT) devices.
Keywords: FinFET, FDSOI, Planar, VLSI, Scaling, Sizing, Digital Design.

1. INTRODUCTION devices became attractive for sub-30 nm nodes3, 4 because

The continuous scaling of planar CMOS devices has of their unique channel structure with good gate control
delivered increasing performance and transistor densities. that enables a much improved short channel control, thus
However, it also reached a point where increased leak- requiring little or no doping in the channel. The thresh-
age current, fluctuation of device characteristics and short old voltage Vt can be scaled down in FinFETs for both
channel effects became serious obstacles to further scal- improved device performance and a much lower opera-
ing. This was mainly because deeply-scaled planar devices tion voltage. Lower channel doping also reduces dopant
became increasingly influenced by the drain potential as ion scattering, thus leading to better drive currents and
the gate lost the ability to fully control the channel; this decreases random dopant fluctuations (RDF).5–7 FinFETs
led to transistors that were never fully off and leaked back-end-of-line (BEOL) fabrication is fully compatible
continuously. To solve this problem, gate oxides were with planar devices in both bulk and SOI varieties, which
aggressively thinned and high-k dielectric gate materi- reduces the need for new, FinFET-specific developments
als were adopted to increase the gate-channel capaci- in that area. However, the introduction of FinFETs has
tance, but the gate-related issues, such as gate leakage and brought a few changes and challenges in digital circuit
gate-induced drain leakage (GIDL) increased.1, 2 FinFET design due to their unique gate structure and electrical
properties. This has also impacted the circuit design deci-
∗
Author to whom correspondence should be addressed. sions and some of the available design tradeoffs. For exam-
Email: [email protected] ple, FinFET devices have a significant amount of parasitics

J. Low Power Electron. 2017, Vol. 13, No. 3 1546-1998/2017/13/001/018 doi:10.1166/jolpe.2017.1489 1

Back to the Future: Digital Circuit Design in the FinFET Era Guo et al.

that need to be modeled precisely and be carefully consid- Gate Drain

Drain
Gate
ered in the layout of all circuits, especially in SRAM and L
analog circuits. From a circuit design aspect, in addition to L
the extra effort needed to address the impact of parasitics
at the layout level, new circuit techniques are needed in
the area of body-biasing and memory read/write assist in Source
H fin
SRAMs to replace techniques that worked well in planar Gate Dielectric
Gate Dielectric
but are inefficient for FinFET. The double/multipatterning Source
W Fin Width (t)
also requires tool vendors and designers to work together (a) (b)
to make sure the layout coloring is correct (colors refer
to different exposures of the same layer while perform- Fig. 1. Illustration of structural differences (no substrate): (a) planar
device; (b) FinFET device.
ing multipatterning). New constraints have been added
to FinFET design, such as width quantization and self- With this structure, the gate is able to fully deplete the
heating effects, for which designers need to make early channel thus having much better electrostatic control over
decisions in the design cycle. In this paper, we analyze the channel.
these aspects at both the device and circuit levels. To study FinFETs can be classified by gate structure or type of
these challenges, we simulate across multiple technology substrate. Different gate structures lead to two versions
nodes which cover a wide range of gate lengths and also of FinFET—Shorted-gate (SG) FinFETs and Independent-
substrates including both SOI and Bulk. For FinFET, we gate (IG) FinFETs. In SG devices, the left and right sides
simulate with both 1 × nma industry-standard node and a are connected together in a wrap-around structure as in
7 nm predictive node. This paper aims to provide a detailed Figure 1; this can serve as a direct replacement for the
analysis and global view of how FinFETs differ from pre- planar devices which also have one gate, a source and
vious technology nodes and what are the implications on a drain (three terminal-devices). In IG FinFETs, the top
circuit design. We restrict our focus to digital circuits, but part of the wraparound gate structure is etched out and
several of the findings can be applied to analog design this results two separate left and right sides that can act
as well. as independent gates and can be controlled separately.8, 9
The paper is organized as follows. Section 2 discusses Although IG FinFETs offer more design options, the fab-
the FinFET basics and how FinFETs are different from rication costs are also higher in general. Depending on the
planar technologies at the device level. We address the substrate, the FinFETs can be either SOI or bulk FinFETs
changes and challenges FinFETs have introduced for cir- as illustrated in Figure 2. SOI FinFETs are built on SOI
cuit design in Section 3. In Section 4, we summarize all wafers and have a lower parasitic capacitance and slightly
the challenges from the designers’ perspective. Section 5 less leakage. Bulk FinFETs are more familiar to design-
concludes the paper. ers, the fabrication costs are relatively lower, and they also
have better heat transfer rate to the substrate compared to
2. FINFET DEVICE SOI FinFETs,8 thus bulk FinFETs are usually preferred
2.1. Scaling and Sizing for most digital applications. The fabrication of both types
of FinFET devices is compatible with those of the con-
2.1.1. FinFET Structure
ventional planar devices fabricated on either bulk or SOI
Compared to conventional planar devices (bulk or SOI),
wafers.
FinFET devices have unique 3-D gate structures that
enable some special properties for FinFET circuit design
2.1.2. Device Geometry and Sizing
which will be detailed in the following sections. Illus-
Unlike planar technologies for which the transistor width
trated in Figure 1 is a planar device and a FinFET device
is a continuous value fully under the control of the cir-
(the substrate is not included in the figure). While the
cuit designer, in FinFET technologies device widths are
channel of the planar device is horizontal, the FinFET
quantized into units of whole fins. The effective gate width
channel is a thin vertical fin with the gate fully “wrapped”
around the channel formed between the source and the
drain. The current flows parallel to the die plane whereas G G
the conducting channel is formed around the fin edges.
Buried Oxide
a
In advanced technology nodes the “numbering” scheme is somewhat Silicon Substrate
Silicon Substrate
arbitrary, while in older technologies the node “number” used to denote
the smallest feature size, usually the transistor gate length, in modern (a) (b)
technologies the node number does not refer to any one feature in the
process, and foundries use slightly different conventions; we use 1× to Fig. 2. Cross section view of structural differences between (a) Bulk
denote the 14 nm–16 nm FinFET nodes offered by several foundries. FinFET and (b) SOI FinFET.

2 J. Low Power Electron. 13, 1–18, 2017

Guo et al. Back to the Future: Digital Circuit Design in the FinFET Era

of a FinFET device is roughly n(2Hfin + t, where n is the An example of such involvement can be to analyze the
number of fins, t is the fin width and Hfin is the fin height design space of current versus capacitance for different fin
as illustrated in Figure 1(b). Since the gate of a FinFET heights. As the technology node approaches the sub-10 nm
device is designed to achieve good electrostatic control over scale, this type of analysis is more and more important
the channel, and because of the etching uniformity require- since the fabrication difficulties are increasing, and the
ments, the fin dimensions (e.g., height Hfin ) are not under design tradeoffs might drastically change.16
designer control, and thus the device width cannot have an
arbitrary value as in planar technologies. Wider transistors 2.2. Bulk versus FDSOI versus FinFET Devices
with higher on-currents are obtained by using multiple fins, In this section, we present some study results across mul-
but the range of choices is limited to integer values. This is tiple technology nodes (from 130 nm to 7 nm) which
known as the width quantization issue.10–12 This quantiza- include both real technology nodes that are used in indus-
tion issue doesn’t allow flexibility in terms of device sizing try, and also predictive nodes which are widely used in
which becomes problematic especially in analog design and academia but not tied to any specific foundry. As for the
SRAMs. The designers need to adapt to this new constraint 7 nm node, we use a recently released predictive 7 nm
during the design phase.13 An alternative solution would PDK17 which is based on current realistic assumptions for
be for the foundry to provide the designers with multiple the 7 nm technology node but is not tied to or verified by a
versions of FinFET with different fin heights.14 For exam- specific foundry. We believe that this analysis will provide
ple,15 did an early attempt by exploring the design space of us with a good insight on how FinFET devices are right
FinFETs with double fin heights and showed that the lack now (with industry PDKs) and how good these devices are
of continuous sizing can be somewhat compensated; this likely to be in the future (with predictive PDKs) as we
method though has many uncertainties from both fabrica- move forward compared to the planar devices.
tion costs and manufacturing difficulties, so it is unlikely to From a digital circuit designer’s perspective, whether
become widely available. In summary, for digital circuits, the technology is planar or FinFET, whether it is bulk or
width quantization might not be a big issue since most of SOI, the parameters of interest are the same—how much
the cell designs can be adapted to use the limited choice of current can one transistor drive, leakage, DIBL, GIDL and
device widths available. so on. Summarized in Table I are device parameters we
extracted based on extensive simulation results across mul-
2.1.3. FinFET Device Scaling—Fin Height tiple technology nodes.
As discussed in the last section, fin height determines the
overall width of a device. This is a very important parame- 2.2.1. Device Models
ter for circuit designers but they don’t actually have control Device models are critical for circuit designers to run
over it. Smaller fin heights offer more flexibility in terms simulations and make design decisions. They need to
of sizing, but this would lead to more fins, which means be accurate and efficient in terms of simulation time
more silicon area. In contrast, FinFET devices with taller and complexity. The fact that fins are 3D structures
fins offer less flexibility with sizing but have a smaller that rise above the substrate means that they are more
silicon footprint and the increasing fin heights for suc- strongly affected by their immediate environment than pla-
cessive FinFET nodes combines with the lateral scaling nar devices. This results in a number of challenges dur-
to actually accelerate “Moore’s Law”—style scaling; but ing the modeling process. For example, the interaction
this might also result in larger short-channel effects and between the device and its surroundings needs to be accu-
some structural instabilities.1, 8 In addition, taller devices rately modeled. Besides, the unique gate structure leads to
could also lead to an increase in unwanted capacitance. increased gate capacitance and also to more components
This indicates that there are some opportunities for device- when modeling the parasitic capacitance and resistance
circuit codesign that are unlikely to become available compared to the planar devices.19, 20 These capacitance
for fabless companies but could become important for and resistance values are crucial since the inaccuracy
vertically-integrated companies that have their own fabs. caused during extracting R and C parasitic will lead to

Table I. Summary of device parameters across multiple technology nodes (extracted from I –V curves).

Physical length Nominal In /Ip Subthreshold DIBL GIDL Channel length

Technology Lg (nm) Vdd (V) (Saturation) slope (mV/dec) parameter slope (mV/dec) modulation  (/V)

130 nm bulk 120 1.2 4.24 92.07 0.53 3346 0.246

Bulk18 a 45 1.0 1.45 98.3 1.61 286 0.387
28 nm FDSOI 30 1.0 3.21 84.2 0.993 198.42 0.260
1 × nm bulk FinFET 14 0.8 0.99 71.1 0.485 429.79 0.256
7 nm bulk FinFET17a 20 0.7 0.90 67.6 0.745 2220.6 0.203

Note: a Predictive nodes.

J. Low Power Electron. 13, 1–18, 2017 3

Back to the Future: Digital Circuit Design in the FinFET Era Guo et al.

Planar, Bulk
FinFET, Bulk
Planar
FDSOI

OFF Current/Width (uA/um)

Leakage reduced
dramatically 106
Planar, Bulk
-2
10

ION/IOFF
105
Planar
FDSOI
FinFET, Bulk

10-3
104

130nm 45nm* 28nm 1xnm 7nm* 130nm 45nm* 28nm 1xnm 7nm*
(a) (b)

Fig. 3. (a) Leakage current with technology scaling; (b) Ion /Ioff ratio with technology scaling.
Note: ∗ Predictive technology nodes (45 nm and 7 nm).

mis-characterization and under/over-estimated design mar- simulation efficiency also matters and it depends on the
gins. Figure 4 shows an example of how FinFET para- levels of model complexity, but thanks to the fast solvers
sitic capacitance is accounted for a 2-finger device. It is and accurate extraction tools recently developed, the sim-
clear that more components contribute to both intrinsic ulation time has remained tractable.
capacitance (in the SPICE models) and extraction capaci-
tance (accounted during extraction). For example, the gate 2.2.2. Leakage
capacitance includes gate to top of fin diffusion, gate to One of the driving forces that leads the industry to move
substrate between fins, gate to diffusion inside channel, from bulk planar to FDSOI or FinFET technologies is the
gate to diffusion between fins, gate to contact, and so on. difference in leakage. With every new process generation
Similarly, the Fin-to-Fin capacitance is also newly intro- the doubling of gate density is also associated with a dou-
duced for FinFET devices. The complexity of modeling bling of the amount of leakage current.21 This is also clear
has been increasing as the device dimensions shrink. Cou- from the simulation results in Figure 3(a) where the sub-
pling and Miller effects are more pronounced in these threshold current (OFF current) per unit width is plotted
devices as well. for different technology nodes. It can be seen from the plot
The FinFET structure brings new modeling challenges. that, when scaling from 130 nm to 45 nm, the leakage cur-
In a planar device, the source and drain are self-aligned rent increases significantly, due to the fact that the channel
with the gate and often intrude slightly under it. In Fin- depth underneath the gate becomes larger and a significant
FET devices there is a spacer between the gate and the volume of the channel is too far away from the gate and
source and drain, which are usually raised and have a strain there is a subsequent loss of electrostatic control. FDSOI
caused by a SiGe layer that creates a lattice mismatch. This and FinFET on the other hand achieve much better leak-
means there are much more complex parasitic capacitance age results because the gate has much better control over
and resistance structures and more model calibrations are the channel in these technologies. Our simulations show
required to achieve good accuracy. As for the designer, the that 28 nm FDSOI and 7 nm FinFETs have comparable

Contact Contact
Fin

Gate Diffusion Gate Diffusion

Diffusion Diffusion Fin

Fin

Substrate

(a)
(b)

Fig. 4. Capacitance components for a FinFET device: (a) Cross-section view and (b) Top view.

4 J. Low Power Electron. 13, 1–18, 2017

Guo et al. Back to the Future: Digital Circuit Design in the FinFET Era

leakage numbers. However, 1 × nm bulk FinFET shows effect is the smallest and is as good as a relatively old
a reduction of leakage of at least 50%. This can be due long-channel technology (130 nm).
to the fact that FDSOI and FinFET use different mecha-
nisms to reduce leakage. In FDSOI, leakage reduction is 2.2.6. GIDL
achieved by making the channel thinner, by limiting its The introduction of high-k/metal-gate stacks in planar
depth with the help of an insulating layer, while in FinFET devices has led to substantial reduction in the gate leak-
it is achieved by making the gate wrap around the channel. age and has exposed other leakage mechanisms such
Another way of explaining the leakage reduction in Fin- as gate-induced drain leakage (GIDL) as primary gate-
FET devices is to look into the subthreshold slope. The related leakage mechanisms.23 GIDL occurs due to the
sub-threshold slope also measures how fast the device high reverse bias between the silicon body and the drain
can switch from OFF to ON, and the lower bound is junction (a PN-junction) near the gate edge at a nearzero
60 mV/dec at room temperature. Table I shows that, or a negative gate bias.24 GIDL usually increases as the
together with the move to FDSOI and FinFET, the sub- gate length (Lg ) decreases due to the floating body effect
threshold slope value has actually improved with scaling and is usually pronounced in short-channel devices. In this
and this has resulted in a significant benefit for continu- paper, we pick the GIDL slope to quantify this effect; the
ously improving frequency, active power, leakage power larger this slope the lesser GIDL effect the device has.
or a combination of the three over the past few years.22 Interestingly, the results in Table I indicate that as the tech-
nology switched to FinFET, GIDL has actually improved.
2.2.3. Ion /Ioff Ratio The suppression of GIDL can be explained by the light
The Ion /Ioff ratio is an important figure of merit for doping of the channel and better junction placement gradi-
having high performance (higher Ion ) and low leakage ent as suggested in Ref. [23]. In conclusion, FinFETs are
power (lower Ioff ) for the devices. Since the leakage superior to planar devices in terms of Ion /Ioff , DIBL, CLM,
current (Ioff ) has been significantly reduced in FinFET GIDL, and thus appear to be a true “back to the future”
devices, their Ion /Ioff ratio is superior to bulk, as shown reset of most of the metrics that were getting worse with
every new technology node for bulk planar technologies!
in Figure 3(b). This has also enabled a continuous perfor-
mance improvement.
2.2.7. Wp /Wn Ratio
2.2.4. DIBL Another interesting aspect for FinFET technologies is that
the pull up network (PUN) and the pull down network
Drain-Induced-Barrier Lowering (DIBL) is a short-channel
(PDN) can become very symmetric. PMOS and NMOS
effect that appears as the distance between the source and
devices with the same number of fins have very com-
drain decreases to the extent that they become electrostati-
parable driving strength, and the conventional 2:1 or 3:1
cally coupled. The drain bias affects the potential barrier to
sizing strategy is not be applicable (or necessary) in the
carrier flow at the source junction, resulting in subthresh-
FinFET case. This can be seen from the In /Ip ratio in
old current increase. To characterize it, we use the DIBL
Table I, which is very close to 1 for the FinFET nodes.
parameter, which is defined in Eq. (1) and corresponds to Figure 5 further demonstrates this. It plots the voltage
the change of leakage current due to Vds . The smaller this transfer curve (VTC) under different supply voltages for a
parameter, the better the DIBL behavior is. It is shown in FinFET inverter with Wp /Wn = 1. It shows that the small-
Table I that FinFETs achieve very good DIBL behaviors signal gain (which is the slope of the transfer curve when
compared to bulk devices. In particular, the 1xnm FinFET the input is equal to the mid-point voltage) is close to ideal
device has the lowest DIBL effect among all five technol- (very high gain), and the curves are very balanced in all
ogy nodes considered. cases which further demonstrates that the ratio of 1:1 is
optimal for FinFET logic.
 logIoff  = DIBL Parameter × Vds (1) The reason behind this fact is due to the unique fab-
rication process for FinFET. As opposed to planar struc-
2.2.5. Channel Length Modulation (CLM) tures which can only be fabricated in a single plane due
Channel length modulation (CLM) is another short- to process variation and interfaces traps, FinFETs can be
channel effect that is caused by large drain biases. It is fabricated with their channel along different directions
characterized by the CLM parameter  which is generally in a single die. This results in enhanced hole mobility.
proportional to the inverse of the channel length. Smaller The N type FinFETs implemented along plane 100 and
 means less CLM effect. Table I shows that CLM has the P type FinFETs fabricated along plane 110 lead to
been getting worse as the channel length shrinks in pla- faster logic gates since it combats the inherent mobility
nar devices even by increasing the doping density. When difference between electrons and holes.1, 25, 26 Moreover,
technology switched from planar to FDSOI and FinFET, since the gate has very good control over the channel,
CLM has been improved due to the better control over the doping concentrations can be much lower than in pla-
channel. Especially, in 7 nm technology node, the CLM nar devices, thus allowing to reduce the random dopant

J. Low Power Electron. 13, 1–18, 2017 5

Back to the Future: Digital Circuit Design in the FinFET Era Guo et al.

0.8 2.0
FinFET,Bulk
Vout = Vin

Velocity Saturation Index (Alpha)

1.8
0.6
1.6
Vout (V)

0.4 1.4 Planar

Vdd=0.8V FDSOI
Planar
Vdd=0.6V
1.2 Bulk
Vdd=0.4V
0.2 Vdd=0.2V
1.0

0.0 0.8
0.0 0.2 45nm 28nm 1xnm 7nm
0.4 0.6 0.8
Vin (V) Fig. 6. Velocity saturation index () for different technologies.

Fig. 5. VTC curves under different supply voltages for a 1xnm FinFET We performed Ids − Vgs simulations for the base NMOS
inverter (PMOS and NMOS are sized equally).
transistors of four different technologies and determined
their respective velocity saturation index . The results
fluctuations (RDF),7 mitigating the impact of mobility on
obtained, summarized in Figure 6, suggest that, as we
current.
switch to FinFETs, devices behave increasingly more
The symmetric PUN and PDN introduce ease in terms
according to the long-channel model, again, in a “back to
of physical design and sizing but it also brings slight
the future” way.
changes in design decisions and standard cell design.
2.3. FinFET Fabrication
2.2.8. Alpha-Power Law
In the previous section we studied the device parameters
The long-channel MOSFET model (Shockley model),
of FinFET versus planar technology nodes and found out
assumes that carrier mobility is independent of the applied
that FinFET devices stand out in almost all the metrics.
fields, since the lateral or vertical electric fields were low.27
However, for short-channel MOSFETs, the velocity of car- Besides, the process technology of FinFET is relatively
riers reaches a maximum saturation speed due to carri- straightforward and compatible with conventional planar
ers scattering off the silicon lattice. This also leads to a device fabrication process.29 But there are still challenges,
degradation in mobility that depends on the gate to source for example, fin shape control and recess of shallow trench
voltage Vgs . isolation (STI) oxide are still critical in the integration of
The drain current Id is quadratically dependent on the FinFETs. Due to the space limit and the focus of this
drain to source voltage (Vds2 ) in the long-channel regime paper, we list only a few fabrication advances and chal-
and linearly dependent on Vds when fully velocity saturated lenges in the FinFET era in this section.
due to an electric field higher than a critical electric field
Ec = Vc /Lg ,28 where Vc is the corresponding critical volt- 2.3.1. Double/Multi-Patterning
age and Lg is the gate length. A moderate supply voltage Although technologies keep scaling to the order of a few
is when the transistor operates between the long-channel nanometers, lithography still uses 193 nm wavelength light,
regime and velocity saturation. The complete model, called which makes printability and manufacturability more chal-
the -power law model, is presented in Eq. (2): lenging due to increased distortion. Beyond 20 nm the use
⎧ of multi-patterning is required for device fabrication. Using
⎪ 0 Vgs < Vt (Cutoff)
⎪
⎪ multi-patterning technology, a single layout is decomposed
⎨ Vds into two or more masks and manufactured through two or
Ids = Idsat  Vds < Vdsat (Linear) (2)
⎪
⎪ V more exposure steps. These masks are then combined to get
⎪
⎩
dsat
the original intended layout. By decomposing the layout
Idsat  Vds > Vdsat (Saturation)
into two or more masks as shown in Figure 7, the pitch size
where Idsat = Pc /2Vgs − Vt  and Vdsat = Pv Vgs − is effectively doubled thereby enhancing the resolution.30
Vt /2 . The exponent  is called the velocity saturation To achieve this, on the design side, color (mask) assign-
index, and ranges from 1 for fully velocity saturated tran- ments are used. Several techniques of multi-patterning
sistors to 2 for transistors with long channel or low supply include Litho-Etch-Litho-Etch Double Patterning (LELE
voltage. DP), Spacer-is-Metal Self-Aligned Double Patterning (SIM

6 J. Low Power Electron. 13, 1–18, 2017

Guo et al. Back to the Future: Digital Circuit Design in the FinFET Era

Fig. 7. Layout decomposition: A single layer is decomposed in two or more masks to enhance the resolution.

SADP), Litho-Etch-Litho-Etch-Litho-Etch Triple Pattern- necessary to provide better cell level connections with
ing (LELELE TP) and Spacer-is-Dielectric Double Pattern- restricted patterning capabilities and multipatterning.35 The
ing (SID SADP). To use these techniques the designer can introduction of MEOL increases the complexity of fab-
include the colored masks per layer that must be multi- rication and modeling as well. For circuit designers, the
patterned or use a colourless flow where the foundry per- added new parasitic effects from MEOL need to be consid-
forms the decomposition.31 ered during the design process since these parasitics have
been demonstrated to be one of the dominant sources.36
2.3.2. Fin Formation MEOL parasitics have been usually accounted at the logic
Although multipatterning brings new fabrication chal- gate-level parasitic extraction step using the standard EDA
lenges, some of the known fabrication steps from the pla- tools. For physical design engineers, the added MEOL
nar technology can be repurposed to achieve new required means more complex design rules and longer debugging
shapes like the 3D fins. Sidewall spacer deposition steps process, also, the layout tools must automate conformance
from planar processes are utilized to perform self-aligned to rules as much as possible.
double patterning (SADP). Similarly, the steps used to
form Shallow trench isolation (STI) can be extended to 2.4. Summary—What Have We Learned So Far?
fabricate fins by additional etching of STI areas and The studies discussed in the previous sections show that
thereby exposing Si fins. Fins are fabricated in a regu- FinFET devices outperform planar devices (bulk and SOI)
lar fashion over a large area. Thereafter unwanted fins are in almost all aspects. In particular, much less leakage cur-
excised and the remaining fins become a part of active rent enable a wide range of applications from high-end to
areas of the devices. Hence FinFET fabrication becomes energy-constrained applications. Better Ion /Ioff ratio have
compatible with old planar CMOS processes using repur- led to continuous performance improvement compared to
posing of existing steps, plus a few extra steps. planar at the same node. FinFET devices also provide
improved sub-threshold and short-channel behavior. An
2.3.3. Shape of the Fins added advantage of the FinFET is that it can be easily fab-
Several studies have shown that FinFET performance is ricated along different channel planes in a single die, and
affected by the cross-sectional area of the fin, therefore this makes sizing strategy simpler. The added MEOL made
the fin shape. Intel’s 22 nm node microprocessor was built the transition from planar devices to FinFETs slightly more
with FinFET sidewalls sloping at about 8 degrees from complex in terms of the fabrication and parasitics but the
vertical which makes more sturdy devices among other
advantages.26 Figure 8 shows the main types of fins ana-
lyzed in the literature. Experimental data shows that a Fin-
FET with a rectangular cross-sectional area has better short
channel effect metrics, in particular sub-threshold slope,
GIDL and DIBL if compared with a triangular or trape-
zoidal cross-sectional area.32 On the other hand a trian-
gular fin can reduce leakage current by 70% if compared
with a rectangular fin.33

2.3.4. Middle-End-of-Line (MEOL)

Middle-end-of-line (MEOL) is a new term introduced
in the FinFET era. It refers to the intermediate
Fig. 8. Left side: A fin with a vertical slope which presents better short
process steps that complete the transistor formation channel metrics.32 Middle: A standard fin with some degree of inclination
(Front-end-of-line: FEOL) before contacts and intercon- as the one used in the 22 nm Intel’s node.26 Right side: A fin with a
nect formation (Back-end-of-line: BEOL).34 MEOL is triangular cross-sectional area that can help to reduce the leakage.33

J. Low Power Electron. 13, 1–18, 2017 7

Back to the Future: Digital Circuit Design in the FinFET Era Guo et al.

back-end of the process is essentially the same, and there- 119 1xnm Bulk FinFET
fore the part of the design flow associated with the physical 7nm Bulk FinFET
implementation remains similar.7 118

117
3. FINFET CIRCUITS
Since FinFET devices have much better electrostatic prop-
116 ON current doesn't

ION(uA)
erties and other metrics than planar devices, new logic change with body bias
and wider design space exploration opportunities become
115
available. In this section, we discuss these new changes
that FinFETs have introduced at the circuit level.
114

3.1. Logic Styles

113
As discussed in Section 2.1.1, FinFETs come in two
flavors—short-gated (SG) and independent-gated (IG). For 112
IG FinFETs, the top part of the gate is etched out, result- –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0
ing in two independent gates. Because the two independent VBS (V)
gates can be controlled separately, IG-mode FinFETs offer
more design styles.8, 9 Although the gates are electrically Fig. 10. ON current versus Body bias for a 2-finger 1 × nm and 7 nm
NMOS transistor.
isolated, their electrostatics are highly coupled. The thresh-
old voltage of either of the gates can be easily influenced bulk or SOI processes receive little benefit from controlled
by applying an appropriate voltage to the other gate. Shown body effect because the channel in the FinFET is mostly
in Figure 9 is one example of different flavors of 2-input in the top of the fin, away from the body. Thus the body
NAND gate implemented using SG/IG gate or a hybrid bias techniques is not applicable to FinFET circuit design
of both (modified from Ref. [8]). In SG mode, FinFET anymore.38 To validate the above argument, we apply both
gates are tied together, so they work the same as the planar reverse and forward body bias to a 2-finger transistor and
devices; In IG mode, one device (with two gates) is driven simulate the ON current for both 1 × nm and 7 nm nodes,
by two independent signals, and some logic functions can with the results are shown in Figure 10. The ON current
be realized by one device; in IG-Low Power mode, one doesn’t change with the body voltage, as expected, and
gate is disabled and acts as the reverse-biased back-gate. it indicates that FinFET devices are largely insensitive to
The designers can even mix the two types of devices and the body effect. On one hand, this reduces the available
balance the tradeoff if it is allowed by the foundry. But IG design knobs, on another hand, this can mitigate the stack
gate requires one more step of etching in the fabrication effect. In the following sections, we present two solutions
step. to address these two separate aspects.

3.2. Body Effect 3.2.1. Gate Overdrive with Split-Circuit Biasing to

Adaptive Body Biasing (ABB) has been used by circuit Substitute for Body Biasing in FinFET
designers as an effective design technique to reduce the In this section, a circuit topology is presented which sub-
impact of die-to-die and within-die variations by changing stitutes body biasing, but doesn’t rely on the body (or back
the NMOS and PMOS threshold voltages independently in plane) voltage to do so. Additionally, the topology pre-
order to maximize performance.37 FinFETs fabricated in sented here does not require varying the voltage swing to
Vdd Vdd Vdd Vdd

b a a b a VHigh b a
b b a

a a a a a a

b b b b b b

SG IG IG - Low Power IG - Hybrid

Fig. 9. Different FinFET logic styles: 2-input NAND gate designs with SG and IG devices.

8 J. Low Power Electron. 13, 1–18, 2017

Guo et al. Back to the Future: Digital Circuit Design in the FinFET Era

(a) (b)

Fig. 11. (a) Static CMOS inverter with 2 fins per transistor and (b) Split-circuit inverter with split inputs, outputs, and supply rails.39

modulate performance and power as in DVS. The effect Under reverse bias, V will be negative. The power rail
is achieved by splitting the inputs, outputs, and supply voltages will be obtained by two off-chip supplies which
rails of a gate and applying a small difference between the have the same differential (Vdd ), and one on-chip charge
two sets of supply rails, which will either overdrive some pump to maintain the voltage separation between the two
device gates (in forward bias) or decrease the leakage cur- domains (V ). Figure 12 shows the performance and static
rent for ‘off’ transistors (in reverse bias).39 power response of a butterfly module of FFT for the 7 nm
Figure 11 shows an inverter implemented with the reg- and 20 nm FinFET nodes to the split-circuit biasing, which
ular topology and the proposed split-circuit biasing topol- enables a wide range of performance (For example, at a
ogy. The idea is to regulate Vgs to mimic the threshold forward bias of 0.2 V the delay of the butterfly module
shift achieved by body biasing. In order to do this, two reduced to 58% of the nominal delay with 7 nm). This
supply voltage domains are needed. One domain will be confirms that split-circuit biasing gives effective control
the nominal domain, with voltage swings from 0 to Vdd . over device current post-fabrication in FinFET technology
The second domain will have the same differential, but which cannot benefit significantly from controlled body
both the ground and supply rail will be shifted up by some effect.
bias voltage, V , such that the voltage swings of gates
receiving this supply domain will swing from 0 + V to 3.2.2. Stack Height as a Potential Design Knob in
Vdd + V . The inputs, outputs, and supply rails of a tra- FinFET Circuit Design
ditional CMOS topology are split such that the number of In some logic cells, NAND gate for example, several tran-
each are doubled. Any two corresponding inputs will carry sistors are connected in series and stacked. In planar CMOS
the same logic, but one is shifted up by some bias volt- circuit, stack height is limited by the body effect; due to
age, V . Under forward bias, the higher inputs will drive the body effect, the voltage between source and body of
the gates of the NMOS while the lower inputs will drive the top stacked transistor will increase the threshold volt-
the NMOS; this will result in a higher Vgs for half of the age and will lead to performance degradation; if the stack
NMOS and a higher absolute value of Vgs for half of the height keeps increasing, the pull down current will become
PMOS, and therefore a higher Ion for half of the devices. smaller and the circuit will become slower or might not

(a) (b)
40
Fig. 12. Simulation results (using the predictive FinFET nodes ) with the Split-biasing circuit for a FFT butterfly module (a) Normalized delay from
a change in inputs to a change in outputs; (b) Normalized static power in standby mode.39

J. Low Power Electron. 13, 1–18, 2017 9

Back to the Future: Digital Circuit Design in the FinFET Era Guo et al.

2x
2x
2x 2x 900
4x
800
2x
700
4x

Delay(ps)
2x 600
4x 2x
16 2x 500
4x
400
2x
4x 300
2x
2x 200
2x 1 4 16

2x
Stack Height
(a) (b)

Fig. 13. (a) 16-input AND gate implemented with different stack height (1, 4 and 16); (b) 16-input AND delay simulations with different stack height
(interconnect capacitance is considered).

even function correctly. For FinFET logic due to the insen- NMOS regions are symmetric. The standard cell template
sitivity to the body effect as discussed above, the stack height (in the number of M1 wiring tracks) usually comes
effect will be minimal and this can lead to higher stack in several flavours. For example, a high density library
logic cells with potential of increasing the fan-in and reduc- might be 9 tracks tall, a high performance library might
ing the logic depth, thus further reducing delay and leak- be 13 tracks tall, and a power optimized library might be
age paths. Our first attempt of simulating a 16-input AND 10.5 tracks tall. But in FinFET, the additional constraint of
gate confirms the above assumption. Shown in Figure 13(a) fitting a fixed number of fins within a cell complicates this
is a 16-input AND gate implemented with different stack Ref. [4]. Especially in most FinFET technologies, fin and
heights and logic depths. Figure 13(b) shows the simulated metal pitches are different and have not tended to line up.
delay in 1 × nm FinFET technology corresponding to dif- Power rail connections at the top and bottom of the cell
ferent stack height. The results suggest that a stack height typically force the removal of 1 fin each, and typically 2
of 16 and a corresponding logic depth of 2 stages achieves additional fin tracks must be removed in the center of the
the best performance. Another benefit of increasing the cell to accommodate gate input connections, all of these
stack height is the reduction of leakage. If we assume that make compact FinFET cell design very complex. In addi-
the leakage with stack height of 16 design is 16I , where tion,4 also pointed out that to meet the multiple patterning
I is the leakage of the unit-sized transistor, then the leak- requirement, the coloring process need to be conducted
age for a stack height of 2 is 16 + 8 + 4 + 2I , which is during the design of the standard cells, coloring also needs
much larger. In summary, due to the fact that the stack to meet density solutions (each color mask must have rea-
effect is weak in FinFET logic, designers can increase the sonably consistent density across the chip).
stack height with a relative relaxed margin to balance the
tradeoffs of area, delay and leakage. 3.4. Logical Effort
The logical effort method is an approximate, simplified
3.3. Standard Cell Libraries model to analyze the delay of a gate. The normalized delay
There are many tradeoffs that need to be considered when is expressed as:
developing standard cell libraries. For example, logic offer-
d = f +p = g·h+p (3)
ings such as the max number of logical inputs on com-
plex gates, flip-flop and latch offerings, clk buffers, drive where p is the parasitic delay, i.e., the delay of the
strength for each cell and so on. As discussed in the previ- gate driving no external load, and f is the effort delay,
ous sections, FinFET devices have several unique intrinsic expressed as the product of logical effort g and fanout h.
device characteristics, and these bring several changes to The logical effort g is proportional to the complexity of
the standard cell library designers. First, with planar tran- a gate as a more complex gate leads to higher gate delay.
sistors, designers can arbitrarily change transistor width in The fanout h is the ratio of the output load capacitance to
order to manage drive current. With FinFETs, due to the the input capacitance of a gate.
width quantization fact as discussed in Section 2.1.2, they We estimated the g and p for an inverter, a 2-input
can only add or subtract fins to size it and change the cur- NAND and a 2-input NOR for different technologies using
rent. Second, since body biasing is generally ineffective, simulation. For this, we use a simple simulation setup
as discussed in last section, this might lead to more logi- consisting of fanout of 1 and fanout of 4 gate delay
cal inputs on complex gates in FinFET libraries. Coming chains. The results obtained are summarized in Table II.
to the physical design, the FinFET devices have periodic The values of g and p have been normalized to the respec-
structures, and the optimal Wp /Wn ratio is almost 1:1, thus tive inverter values for each technology. The table shows
the FinFETs layout looks more regular, and the PMOS and that the g and p values vary slightly across technologies

10 J. Low Power Electron. 13, 1–18, 2017

Guo et al. Back to the Future: Digital Circuit Design in the FinFET Era

Table II. Normalized logical effort g and parasitic delay p values.

7 nm FinFET 1 × nm FinFET 28 nm FDSOI 130 nm Bulk Textbook

INV NAND NOR INV NAND NOR INV NAND NOR INV NAND NOR INV NAND NOR

g 1.00 1.35 1.59 1.00 1.06 1.34 1.00 1.11 1.52 1.00 1.14 1.54 1 1.33 1.67
p 1.68 2.59 3.38 0.62 1.30 0.95 2.90 4.21 4.52 0.49 0.96 0.80 1 2 2

depending on transistor sizing for different technologies. happens due to the fact that FinFET channels are usually
Measured normalized delays for different gates are pre- undoped or lightly doped, so they exhibit only a small
sented in Figure 14 which shows that gates maintain a change in mobility with temperature. It has been shown in
similar trend for increase in complexity across different Ref. [43] that TEI’s inflection voltage approaches nominal
technologies. NOR gates with stacked PMOS are slower supply and the impact of this effect can no longer be safely
than NANDs (stacked NMOS) even in FinFETs where the discounted when scaling into future FinFET and FDSOI
ratio of ON current in NMOS to PMOS is close to 1 as devices with smaller feature sizes. To validate this, we sim-
shown in Table I. ulate the delay vs. temperature for a 9-stage ring oscillator
in multiple technology nodes. The simulation results are
3.5. Thermal Effect Inversion (TEI) shown in Figure 15; the results show that for all technolo-
Thermal behavior is one of the important device char- gies, the increased temperature slow down the devices if
acteristics that affect the design decisions like margins, they work under near and sub-threshold region. Interest-
floorplan and cooling costs. It has been shown in the lit- ingly, for the 28 nm FDSOI node, TEI appears across all
erature that temperature characteristics of FinFET-based voltages, and for 1xnm bulk FinFET node, the TEI effect
circuits are fundamentally different from those of con- has already approached 0.7 V, which is only 0.1 V below
ventional bulk CMOS circuits.41 In a bulk technology, if the nominal voltage (0.8 V). Similarly, for 7 nm bulk Fin-
the transistor operates in the super-threshold region, the FET, the inversion starts from around 0.6 V (0.1 V below
delay increases with the temperature, and in the near/sub- the nominal voltage of 0.7 V). We can conclude that the
threshold region, the delay decreases with the increasing TEI effect is indeec becoming increasingly important in
temperature. While in FinFET, it has been reported that current and future technologies as it will cover all of the
the circuits run faster at higher temperatures in all supply operating voltage ranges.
voltage regimes (including the super-threshold one), and The TEI effect introduces new tradeoffs and also chal-
this is called the Temperature Effect Inversion (TEI) phe- lenges in circuit design. On one hand, a higher tempera-
nomenon.41 In both planar devices and FinFET devices, ture increases the leakage and cooling budget, but, on the
the threshold voltage decreases at the higher temperature, another hand, it helps with the performance. The benefits
and the mobility of charge carriers in the channel decreases of TEI can be maximized with the assist of novel power
due to the ionized impurity and phonon scattering.42 TEI management techniques that can dynamically tune the
voltage or frequency based on the real-time temperature43
10 or novel algorithms that can determine the maximum per-
formance under power constraints.44 Since thermal issues
9 also emerge as important reliability concerns throughout
Delay (Normalized to a 7nm F04 INV)

8 the system lifetime, the TEI effect can compensate some

of the performance degradation introduced by reliability
7 FO4 INV threats such as BTI and EM.42, 45 The optimal operat-
FO4 NAND ing temperature can be exploited to reduce design cost
6 FO4 NOR
and runtime operating power for overall cooling with the
5 proper utilization of the TEI effect.
4
3.6. SRAM Design
3
SRAMs are one of the most area and power hungry com-
2 ponents on a chip. The never-ending demand for pack-
ing more functionality per area and the requirement of
1
higher performance from processing units leads to con-
0 tinuous scaling of devices.46 This scaling trickles down
130nm 28nm 1xnm 7nm to smaller bitcells and enables an increase in memory
Fig. 14. Simulated FO4 delays for Inverter, 2-input NAND and 2-input array density in terms of number of bits stored per area.
NOR gates in different technology nodes (all values are normalized to Hence from the density point of view, minimum sized tran-
the 7nm FO4 INV delay). sistors are desired in bitcells. This translates to a 1:1:1

J. Low Power Electron. 13, 1–18, 2017 11

Back to the Future: Digital Circuit Design in the FinFET Era Guo et al.
-7
-10 -9 1.0x10
3.7x10 1.2x10

130nm Bulk, Vdd = 0.7V (Nearthreshold) 130nm Bulk, Vdd = 0.4V (Subthreshold)
3.6x10
-10 130nm Bulk, Vdd =1.2V (Nominal)
-9 -8
1.1x10 8.0x10
-10
3.5x10

-10
3.4x10 -9
1.1x10 6.0x10
-8

Delay (s)
-10

Delay (s)
3.3x10
Delay (s)

-9
3.2x10
-10 1.0x10 -8
4.0x10
-10
3.1x10
-9
1.0x10
-10 -8
3.0x10 2.0x10

-10
2.9x10 9.5x10
-10

-10
0.0
2.8x10
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
Temperature (°C)
-11 -9 -6
7.8x10 4.0x10 1.8x10

28nm FDSOI, Vdd = 0.5V (Near-threshold) 1.6x10

-6 28nm FDSOI, Vdd = 0.3V (Sub-threshold)
28nm FDSOI, Vdd = 1V (Nominal)
-11 -6
7.6x10 1.4x10
-9
3.0x10
-6
1.2x10

-11 -6
7.4x10 1.0x10

Delay (s)
Delay (s)
Delay (s)

-9 -7
2.0x10 8.0x10

-11 -7
7.2x10 6.0x10
-7
4.0x10
-9
1.0x10
-11 -7
7.0x10 2.0x10

0.0

-7
6.8x10
-11 0.0 -2.0x10
-60 -40 -20 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120
Temperature (°C) Temperature (°C) Temperature (°C)
-7

1xnm FinFET, Vdd = 0.7V (Nominal) 2.600x10

-10
1xnm FinFET, Vdd = 0.4V (Near-threshold) 2.500x10 1xnm FinFET, Vdd = 0.2V (Sub-threshold)
1.750x10
-11
1xnm FinFET, Vdd = 0.8V (Nominal) -11
2.160x10 -10
2.400x10
-7
-11 2.000x10
1.740x10 2.200x10
-10

-11
-11
2.150x10 2.000x10
-10
1.730x10 1.500x10
-7

-10
Delay (s)
Delay (s)

1.800x10

Delay (s)
Delay (s)

-11
1.720x10 -10
-11
2.140x10 1.600x10 1.000x10
-7

-11 -10
1.710x10 1.400x10
-8
-11 1.200x10
-10 5.000x10
1.700x10
-11 2.130x10
-10
1.000x10
-11 0.000
1.690x10 8.000x10
-11
-11
2.120x10
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C) Temperature (°C) Temperature (°C)
-5
-10 -10 4.0x10
1.3x10 2.3x10 8.0x10
-9

7nm FinFET, Vdd = 0.7V (Nominal) 7nm FinFET, Vdd = 0.1V (Subthrehsold)
7nm FinFET, Vdd = 0.5V 7nm FinFET, Vdd = 0.3V (Near-threshold) 3.5x10-5
-10 -10
1.2x10 2.2x10 -9
7.0x10
-5
-10 -10
3.0x10
1.2x10 2.2x10 -9
6.0x10 -5
2.5x10
-10 -10
1.2x10 2.2x10
-9
5.0x10 -5
2.0x10
Delay (s)
Delay (s)
Delay (s)
Delay (s)

-10 -10
1.2x10 2.2x10
-9 -5
4.0x10 1.5x10
-10 -10
1.2x10 2.2x10
-9 -5
3.0x10 1.0x10
-10 -10
1.1x10 2.1x10
-6
2.0x10
-9 5.0x10
-10 -10
1.1x10 2.1x10
-9
0.0
-10
1.0x10
-10
1.1x10 2.1x10 -6
-5.0x10
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)
Temperature (°C) Temperature (°C)
Temperature (°C)

Fig. 15. Simulated temperature characteristics (delay vs. temperature) in multiple technology nodes for a 9-stage ring oscillator.

(PU:PG:PD) fin bitcell for FinFETs (where PU is the size SRAM performance and lower operational V min. These
of the Pull-up PMOS, PD is the size of the Pull-down techniques focus on improving PD:PG strength ratio for
NMOS, and PG is the size of the pass-gate NMOS in a read assists and PG:PU strength ratio for write assists.
6T SRAM cell). The 1:1:1 bitcell provides highest array These techniques become increasingly necessary in the era
density but it suffers from flaws in terms of lower read of FinFET SRAM design because transistor width quan-
stability and writability.46, 47 The constant need for volt- tization in terms of number of fins decreases device level
age scaling to lower power further exacerbates SRAM sizing options to improve SRAM bitcell functionality.
readability and writability issues. This calls for alternate
bitcells like the Low Voltage (LV) 1:1:2 cell and High 3.7. Variability and Reliability
Performance (HP) 1:2:2 cell46 along with read and write A reduced feature size causes statistical fluctuations in
assist techniques to improve SRAM metrics. Several assist nanoscale device parameters which are known as process
techniques48, 49 have been proposed and studied to improve variations. They lead to mismatched device behaviors and

12 J. Low Power Electron. 13, 1–18, 2017

Guo et al. Back to the Future: Digital Circuit Design in the FinFET Era

degrade the yield of the entire die. In planar devices, a Vdd: 1V (Nominal - 0.8V )
850
number of dopants must be inserted in the channel which Temperature: 100 °C
lead to Random Doping Fluctuations (RDF) causing sig- Test Structure: 17-Stage RO with 1XINV
800
nificant variations in threshold voltage. In FinFETs, since
the channel is undoped or lightly doped, this reduces the 750

Frequency (MHz)
statistical impact of RDF on Vt . The variability associ-
ated with line-edge roughness (LER), the random devi- 700
ation of gate line edges from the intended ideal shape,
650 34.3% Degradation
which results in non-uniform channel lengths, is also lower
in FinFETs. But other process variations do appear in Fin-
600
FETs. Since they have small dimensions and lithographic
limitations, these devices suffer physical fluctuations on 550
gate length, fin thickness or oxide thickness.1, 50, 51 Overall,
FinFETs emerge superior to planar devices by overcoming 500
RDF and LER, which are two major sources of process 0 2 4 6 8 10
variation.
Time (year)
Besides process variations, which represent the time-
zero process variability, time-dependent variations (aging) Fig. 16. Aging simulation with 1 × nm bulk FinFET with foundry-
such as Bias Temperature Instability (BTI), Hot Carrier provided aging models (BTI + HCI).
Injection (HCI) and Electromigration (EM) also appear
to be critical for reliability considerations. These aging parasitic delay will affect the performance in a more sig-
issues conspire to worsen metrics like performance, power nificant way and become one of the bottlenecks on the
and lifetime. As the technology scaling is reaching the scaling roadmap. To address this, interconnect materials
nanoscale FinFET regime, the transistors become more such as Aluminum, cobalt (Co) or ruthenium (Ru) could
susceptible to voltage stress due to the increased effec- be better alternatives due to the better sheet resistance,
tive field associated with the scaling of the thin oxide. but there are also cost and reliability considerations in the
Similarly, the shrinking geometries of metal layers ren- interconnect scheme design.58 The pitch size of the metal
der higher current densities, and the tremendous num- lines also doesn’t scale down that much as the technology
ber of transistors within a compact area results in higher moves into the sub-20 nm regime due to the RC parasitic
power densities. Together, these lead to increased on- and coupling consideration as well. For designers, since
chip temperatures which potentially accelerate the wearout they don’t have control over the materials and design rules,
effects.52, 53 Besides, the thermal resistance (Rth ) of the the only knob they have is the dimension of the wire. This
multi-gate topology and the reduced gate pitch in Fin- requires to consider interconnect capacitance in the early
FET devices exacerbate self-heating which will accelerate design phase even before the physical design. The FinFET
aging.54 Figure 16 shows our simulation results with the PDKs usually provide relatively accurate wire models to
industrial aging models; the results show a very significant account this.
performance degradation under accelerated stress condi-
tion, and if we scale this to the normal operating condition 3.9. Power and Energy
(nominal Vdd and normal on-chip temperature), the degra- FinFETs provide improvements in power and energy con-
dation is still much larger than that in the planar devices. sumption since they overcome the leakage problems of
For interconnect reliability, EM no longer can be signed planar devices and deliver better performance. To fur-
off using aggressive margins, a comprehensive thermal- ther investigate this aspect, we simulate a NAND-based
aware EM signoff methodology needs to be adopted for ring oscillator 59 across multiple technologies. The duty
FinFET designs. New types of EM rules that are dependent cycle of the ring oscillator can be tuned and in our case,
on the direction of current flow, metal topology, via types, it is set as 10%. Shown in Figure 17(a) is the simu-
co-vertical metal overlaps etc. are required to address the lated delay versus Vdd , in which the values of each node
potential reliability issues.55 are normalized to the delay at their own nominal volt-
ages. It shows that FinFETs provide a significant per-
3.8. Interconnect formance advantage at any operating voltages, and the
As the devices become smaller and smaller, the intercon- reduced performance due to lowering the voltage is much
nect becomes more and more dominant in determining lower in FinFETs compared to other technology nodes as
circuit performance. This is because of the yield and EM well. Figure 17(b) presents the energy versus Vdd plot,
requirements, the interconnect can’t scale at the same rate similar normalization is applied. As it shows, although
as the transistors. As interconnect is becoming more com- the minimum energy optimal points are similar for all
pact at each node below 20 nm,56, 57 the interconnect RC the technologies (around 0.2–0.3 V range), the energy of

J. Low Power Electron. 13, 1–18, 2017 13

Back to the Future: Digital Circuit Design in the FinFET Era Guo et al.

1.0

(Normalized to Nominal Voltage Value)

(Normalized to Nominal Voltage Value)

130nm Bulk
40000 28nm FDSOI
0.9
1xnm FinFET Bulk 0.8
7nm FinFET Bulk
30000 0.7
6

Energy/cycle
Delay 0.6
4
20000 0.5
2
0.4
10000 0 0.3
0.6 0.8 1.0 1.2 130nm Bulk
0.2 28nm FDSOI
0 0.1
1xnm FinFET Bulk
7nm FinFET Bulk
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Voltage (V) Voltage (V)
(a) (b)

10-22
Vdd=0.9V
10000

Minimum Energy Delay Product (J.s)

130nm Bulk
(Normalized to Nominal Voltage Value)

28nm FDSOI
1xnm FinFETBulk
8000 7nm FinFET Bulk 10-23
Vdd=0.9V
Energy Delay Product

3.0

2.5
6000 10-24 Vdd=0.5V
Vdd=0.6V
2.0

1.5
4000
1.0 10-25

0.5
2000 0.60.81.0
10-26

0
10-27
0.0 0.2 0.4 0.6 0.8 1.0 1.2 130nm 28nm 1xnm 7nm

Voltage (V)
(c) (d)

Fig. 17. (a) Delay versus Vdd ; (b) Energy/cycle versus Vdd ; (c) Energy Delay Product (EDP) versus Vdd and (d) Minimum EDP values across multiple
technology nodes (simulated with the same NAND-based ring oscillator structure).

FinFET scales the best with voltage; in other words, as 4. SUMMARY—DIGITAL CIRCUIT
the voltage is scaled down, FinFETs offer more energy DESIGN WITH FINFETS
savings than planar devices. In Figure 17(c), the energy We have shown in previous sections that FinFET devices
delay product versus Vdd is plotted. FinFETs offers the offer significant performance improvements and power
best energy efficiency for circuit operating under a wide reduction compared to planar devices. Digital circuit
range of voltages since, as the voltage scales down, the design with FinFET broadens the design window once
energy delay product doesn’t change significantly for Fin- again. Operating voltage continues to scale down, short
FETs compared to planar devices. Figure 17(d) presents channel effects are reduced significantly, the process vari-
the minimum energy delay product across the four tech- ation have been improved, the FinFET devices have lower
nology nodes. As technology scales, the EDP improves as leakage power in standby mode, etc.
expected. Although FinFET devices offer advantages in many
The above study shows that FinFETs provide more dimensions, they also bring challenges in the design
options for performance versus other metrics tradeoffs. For process. FinFET devices have non-standard shapes and
example, since FinFETs offer very good energy efficiency require complex modeling of the parasitics in the TCAD
over a wide range of voltages, voltage scaling techniques tools. Moreover, the physical layout-dependent effects
can be very effective as designers strive to maximize per- have a significant impact on the metrics. Therefore, the
formance per mW without hurting energy. FinFET-based design tools and design flows need to be able to assist
design will be able to support wider use of dynamic volt- the designers to build circuits that accurately correlate to
age frequency scaling (DVFS) and enable a wider range of the models. During the design process, extraction plays a
applications from high-end performance critical systems to big role to obtain accurate timing analysis and power esti-
energy-constraint devices. mation for FinFETs, so enhancement to the foundational

14 J. Low Power Electron. 13, 1–18, 2017

Guo et al. Back to the Future: Digital Circuit Design in the FinFET Era

EDA tools, in particular SPICE simulations, extraction and necessary, and more parallelism is required. Because of
physical verification that operate on part of the design the increased complexity and number of instances on chip,
below the first metal layer are required.7 Interconnect an increasing number of signoff corners are required to
resistance is becoming more important, so IR drop and cover process and environmental variations. Addressing
power-grid design becomes more critical. Besides, to meet these new challenges together with the new, more complex
the double/multipatterning requirements, the standard cell, design-for-manufacturing rules, including double/multi-
floorplanning, placement and route (P and R) need to be patterning, along with the increasing design scale, require
colored correctly. For example, during power planning, all close collaboration between the foundry, tool vendors and
power rails need to be free of double patterning viola- designers to fully take advantages of what FinFETs have
tions. Similarly, all the placement of standard cells and to offer.
hard macros need to be double patterning-compliant. Phys-
ical verification (e.g., DRC) engines need to be able to
5. CONCLUSION
check and guide the designers to meet the double pattern-
FinFETs present a new frontier for the electronics industry
ing rules. More verifications are required, and more check-
and have enabled high performance and power sensitive
points need to be inserted during the design phase to make
applications ranging from small portable devices to super-
sure the design specification is met.
computers. In this paper, we studied the changes since
For custom designers and standard cell designers, all
the advent of the FinFET devices and addressed the chal-
of the blocks require a redesign due to the following rea-
lenges we face with these devices. FinFETs offer benefits
sons. First, the options of sizing are less granular due to
in many dimensions such as the significantly improved
the width quantization fact in FinFET, getting more drive
power and performance metrics and lesser short-channel
strength will require more fins in parallel. Second, the
effect. FinFETs endeavour to offer advantages of future
thermal behavior and options available to circuit designers
scaled devices while offsetting the problems introduced by
are different than what they may be used to with planar
many generations of planar CMOS scaling. But new chal-
devices. For example, body biasing will be impractical,
lenges also appear due to many unique properties which
thermal effect inversion (TEI) fact introduces new trade-
FinFETs have shown. Adapting to the new challenges and
offs, higher fan-in and complex logic are possible due to
fully benefiting from FinFETs will require the growing
the insensitivity to the stack effect. As dozens of new and
knowledge and design experiences and this paper attempts
complicated design rules arise for FinFET devices, phys-
to add to that knowledge base.
ical design efforts are increasing, but the bright side for
FinFET devices is the more regular layout and equal P
and N regions, and because of this, the foundry usually Acknowledgments: This work was supported by NSF
provides a template layout on which fingers and gates are grants CCF 1619127 and CCF 1543837, by DARPA under
already placed, physical designers don’t need to start from the UPSIDE and PERFECT programs and by the Center
scratch, but the layout tools still need to automate confor- for Future Architecture Research (C-FAR), one of six SRC
mance to rules as much as possible. STARnet Centers, sponsored by MARCO and DARPA.
FinFETs also offer more design options for trading per- The authors would like to thank the anonymous reviewers.
formance with other metrics. As discussed in Section 3.9,
one major design optimization benefit of FinFETs is much References
higher performance with the same energy budget. Sim- 1. D. Bhattacharya and N. K. Jha, FinFETs: From devices to architec-
ilarly, they consume much lower power and energy to tures. Advances in Electronics 2014 (2014).
achieve equal performance to planar devices. This essen- 2. B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T. Pileggi, R. A. Rutenbar,
and K. L. Shepard, Digital circuit design challenges and opportuni-
tially gives designers the ability to extract the highest
ties in the era of nanoscale CMOS, Proceedings of the IEEE (2008),
performance for the lowest power, which is a critical opti- Vol. 96, pp. 343–365.
mization for battery-powered devices. Since FinFETs have 3. J. Warnock, Circuit design challenges at the 14 nm technology
lower leakage and can operate faster, the circuit can afford node, Proceedings of the 48th Design Automation Conference, ACM
to have more and fine-grained power gating structures to (2011), pp. 464–467.
4. R. Aitken, G. Yeric, B. Cline, S. Sinha, L. Shifren, I. Iqbal, and
further save power in standby mode. Runtime techniques
V. Chandra, Physical design and FinFETs, Proceedings of the 2014
like DVFS can be used with a lower cost to maximize on International Symposium on Physical Design, ACM (2014),
energy efficiency. On top of all these benefits, the circuit pp. 65–68.
can operate in near-threshold to save energy with lower 5. J.-H. Lee, Bulk FinFETs: Design at 14 nm node and key character-
performance penalties.60 istics, Nano Devices and Circuit Techniques for Low-Energy Appli-
cations and Energy Harvesting, Springer (2016), pp. 33–64.
As more transistors fit on one chip in the FinFET era,
6. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery,
the design flow needs to be able to handle big designs C. Ho, Q. Xiang, and T.-J. King, et al., FinFET scaling to 10 nm
which have billions of transistor at a fullchip level, thus gate length. IEEE International Electron Devices Meeting, 2002,
optimizing the runtime and reducing peak memory are IEDM’02 251 (2002).

J. Low Power Electron. 13, 1–18, 2017 15

Back to the Future: Digital Circuit Design in the FinFET Era Guo et al.

7. J. Kawa, Designing with FinFETs: The opportunities and the chal- 28. T. Sakurai and A. R. Newton, Alpha-power law MOSFET model and
lenges, Synopsys White Paper, Synopsys (2012), pp. 1–8. its applications to CMOS inverter delay and other formulas. IEEE
8. P. Mishra, A. Muttreja, and N. K. Jha, FinFET circuit design, Nano- Journal of Solid-State Circuits 25, 584 (1990).
electronic Circuit Design, Springer (2011), pp. 23–54. 29. H. Zhou, Y. Song, Q. Xu, Y. Li, and H. Yin, Fabrication of bulk-Si
9. A. Muttreja, N. Agarwal, and N. K. Jha, CMOS logic design with FinFET using CMOS compatible process. Microelectronic Engineer-
independent-gate FinFETs, 25th International Conference on Com- ing 94, 26 (2012).
puter Design, 2007, ICCD 2007, IEEE (2007), pp. 560–567. 30. FinFET and Multi-Patterning Aware Place and Route Implementa-
10. F. Sheikh and V. Varadarajan, The impact of device-width quantiza- tion: http://go.mentor.com/4h_c2.
tion on digital circuit design using FinFET structures. Proc. EE241 31. Mastering the Magic of Multi-Patterning: http://go.mentor.com/
Spring 1 (2004). 4gue4.
11. J. Gu, J. Keane, S. Sapatnekar, and C. Kim, Width quantization 32. Y. Liu, K. Ishii, M. Masahara, T. Tsutsumi, H. Takashima,
aware FinFET circuit design, Custom Integrated Circuits Confer- H. Yamauchi, and E. Suzuki, Cross-sectional channel shape depen-
ence, 2006. CICC’06. IEEE (2006), pp. 337–340. dence of short-channel effects in Fin-type double-gate metal oxide
12. W.-K. Yeh, W. Zhang, Y.-L. Yang, A.-N. Dai, K. Wu, T.-H. Chou, semiconductor field-effect transistors. Japanese Journal of Applied
C.-L. Lin, K.-J. Gan, C.-H. Shih, and P.-Y. Chen, The observation Physics 43, 2151 (2004).
of width quantization impact on device performance and reliability 33. B. D. Gaynor and S. Hassoun, Fin shape impact on FinFET leak-
for high-k/metal tri-gate FinFET. IEEE Transactions on Device and age with application to multithreshold and ultralow-leakage FinFET
Materials Reliability 16, 610 (2016). design. IEEE Transactions on Electron Devices 61, 2738 (2014).
13. B. Swahn and S. Hassoun, Gate Sizing: FinFETs versus 32 nm Bulk 34. A. Biddle and J. S. Chen, FinFET technology-understanding and
MOSFETs, Design Automation Conference, 2006 43rd ACM/IEEE, productizing a new transistor. A Joint Whitepaper from TSMC and
IEEE (2006), pp. 528–531. Synopsys (2013).
14. T.-L. Lee, C. C. Yeh, C.-Y. Chang, and F. Yuan, FinFETs with dif- 35. M. Rashed, N. Jain, J. Kim, M. Tarabbia, I. Rahim, S. Ahmed,
ferent Fin heights, US Patent 9,425, 102 (2016). J. Kim, I. Lin, S. Chan, H. Yoshida, et al., Innovations in special
15. C.-H. Lin, C.-S. Chen, Y.-H. Chang, Y.-T. Zhang, S.-R. Fang, constructs for standard cell libraries in Sub 28 nm technologies, 2013
S. Santra, and R.-B. Lin, Design space exploration of FinFETs IEEE International Electron Devices Meeting (IEDM), IEEE (2013),
with double Fin heights for standard cell library, 2016 IEEE Com- pp. 9–7.
puter Society Annual Symposium on VLSI (ISVLSI), IEEE (2016),
36. C.-S. Lee, B. Cline, S. Sinha, G. Yeric, and H.-S. P. Wong, 32-bit
pp. 673–678.
processor core at 5-nm technology: Analysis of transistor and inter-
16. Re-Engineering The FinFET: http://semiengineering.com/re-
connect impact on VLSI system performance, IEEE International
engineering-the-finfet/.
Electron Devices Meeting (IEDM), 2016, IEEE (2016), pp. 28–3.
17. L. T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline,
37. J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis,
C. Ramamurthy, and G. Yeric, ASAP7: A 7-nm FinFET predictive
A. P. Chandrakasan, and V. De, Adaptive body bias for reducing
process design kit. Microelectronics Journal 53, 105 (2016).
impacts of die-to-die and within-die parameter variations on micro-
18. FreePDK45 from NCSU: https://www.eda.ncsu.edu/wiki/freepdk45:
processor frequency and leakage. IEEE Journal of Solid-State Cir-
contents.
cuits 37, 1396 (2002).
19. S. S. Rodriguez, J. C. Tinoco, A. G. Martinez-Lopez, J. Alvarado,
38. W.-T. Chang, S.-W. Lin, C.-T. Shih, and W.-K. Yeh, Back bias mod-
and J.-P. Raskin, Parasitic gate capacitance model for triple-gate Fin-
ulation of UTBB FDSOI, bulk FinFET, and SOI FinFET, 2016 IEEE
FETs. IEEE Transactions on Electron Devices 60, 3710 (2013).
International Nanoelectronics Conference (INEC), IEEE (2016),
20. N. Lu, T. B. Hook, J. B. Johnson, C. Wermer, C. Putnam, and
pp. 1–2.
R. A. Wachnik, Efficient and accurate schematic transistor model of
FinFET parasitic elements. IEEE Electron Device Letters 34, 1100 39. A. Whetzel and M. R. Stan, Gate overdrive with split-circuit biasing
(2013). to substitute for body biasing in FinFET and UTB FDSOI circuits,
21. C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI),
Part 7: MOSFETs in ICs–Scaling, Leakage, and Other Topics (2011). IEEE (2016), pp. 467–472.
22. P. Royer, P. Zuber, B. Cheng, A. Asenov, and M. Lopez-Vallejo, 40. PTM Model: http://ptm.asu.edu/.
Circuit-level modeling of FinFET sub-threshold slope and DIBL 41. W. Lee, Y. Wang, T. Cui, S. Nazarian, and M. Pedram, Dynamic
mismatch beyond 22 nm, 2013 International Conference on Sim- thermal management for FinFET-based circuits exploiting the tem-
ulation of Semiconductor Processes and Devices (SISPAD), IEEE perature effect inversion phenomenon, Proceedings of the 2014
(2013), pp. 204–207. International Symposium on Low Power Electronics and Design,
23. P. Kerber, Q. Zhang, S. Koswatta, and A. Bryant, GIDL in doped ACM (2014), pp. 105–110.
and undoped FinFET devices for low-leakage applications. IEEE 42. W. Sootkaneung, S. Chookaew, and S. Howimanporn, Combined
Electron Device Letters 34, 6 (2013). impact of BTI and temperature effect inversion on circuit perfor-
24. S. Cho, J. H. Lee, S. Ouchi, K. Endo, M. Masahara, and B.-G. mance, 2016 IEEE 25th Asian Test Symposium (ATS), IEEE (2016),
Park, Design of SOI FinFET on 32 nm technology node for low pp. 310–315.
standby power (LSTP) operation considering gate-induced drain 43. Y. Zu, W. Huang, I. Paul, and V. J. Reddi, Ti -states: Proces-
leakage (GIDL). Solid-State Electronics 54, 1060 (2010). sor power management in the temperature inversion region, 49th
25. T. Chiarella, L. Witters, A. Mercha, C. Kerner, M. Rakowski, Annual IEEE/ACM International Symposium on Microarchitecture
C. Ortolland, L.-Å. Ragnarsson, B. Parvais, A. De Keersgieter, (MICRO), 2016, IEEE (2016), pp. 1–13.
S. Kubicek, et al., Benchmarking SOI and bulk FinFET alternatives 44. E. Cai and D. Marculescu, TEI-turbo: Temperature effect inversion-
for planar CMOS scaling succession. Solid-State Electronics 54, 855 aware turbo boost for FinFET-based multi-core systems, Proceed-
(2010). ings of the IEEE/ACM International Conference on Computer-Aided
26. W. P. Maszara and M. R. Lin, FinFETs-technology and circuit Design, IEEE Press (2015), pp. 500–507.
design challenges, 2013 Proceedings of the ESSCIRC (ESSCIRC), 45. E. Cai, D. Stamoulis, and D. Marculescu, Exploring aging deceler-
September (2013), pp. 3–8. ation in FinFET-based multi-core systems, 2016 IEEE/ACM Inter-
27. N. H. Weste and D. M. Harris, CMOS VLSI Design: A Circuits and national Conference on Computer-Aided Design (ICCAD), IEEE
Systems Perspective, Pearson Addison-Wesley (2005). (2016), pp. 1–8.

16 J. Low Power Electron. 13, 1–18, 2017

Guo et al. Back to the Future: Digital Circuit Design in the FinFET Era

46. D. Burnett, S. Parihar, H. Ramamurthy, and S. Balasubramanian, 53. X. Guo and M. R. Stan, Implications of accelerated self-healing as
Finfet sram design challenges, 2014 IEEE International Conference a key design knob for cross-layer resilience. Integration, the VLSI
on IC Design Technology May (2014), pp. 1–4. Journal 56, 167 (2017).
47. W. P. Maszara, Finfets: Designing for new logic technology, Micro- 54. H. Jiang, S. Shin, X. Liu, X. Zhang, and M. A. Alam, The impact of
and Nanoelectronics: Emerging Device Challenges and Solutions, self-heating on HCI reliability in high-performance digital circuits.
CRC Press (2014), pp. 113–136. IEEE Electron Device Letters 38, 430 (2017).
48. B. Zimmer, S. O. Toh, H. Vo, Y. Lee, O. Thomas, K. Asanovic, and 55. Reliability Challenges in 16 nm FinFET Design: http://
B. Nikolic, Sram assist techniques for operation in a wide voltage semiengineering.com/reliability-challenges-16nm-finfet-design/.
range in 28-nm cmos. IEEE Transactions on Circuits and Systems 56. Interconnect Challenges Rising: http://semiengineering.com/interconnect-
II: Express Briefs 59, 853 (2012). challenges-grow-3/.
49. T. Song, W. Rim, S. Park, Y. Kim, G. Yang, H. Kim, S. Baek, J. Jung, 57. N. Lu and R. A. Wachnik, Modeling of resistance in FinFET local
B. Kwon, S. Cho, H. Jung, Y. Choo, and J. Choi, A 10 nm finfet interconnect. IEEE Transactions on Circuits and Systems I: Regular
128 mb sram with assist adjustment system for power, performance, Papers 62, 1899 (2015).
and area optimization. IEEE Journal of Solid-State Circuits 52, 240 58. S. Tu, Putting the pieces together in the materials space: Advanced
(2017). materials solutions for 10 nm and beyond. SEMICON Taiwan
50. E. Baravelli, M. Jurczak, N. Speciale, K. De Meyer, and A. Dixit, (2015).
Impact of LER and random dopant fluctuations on FinFET match- 59. A. Wang, A. P. Chandrakasan, and S. V. Kosonocky, Optimal supply
ing performance. IEEE Transactions on Nanotechnology 7, 291 and threshold scaling for subthreshold CMOS circuits, 2002 Pro-
(2008). ceedings IEEE Computer Society Annual Symposium on VLSI, IEEE
51. X. Wang, A. R. Brown, B. Cheng, and A. Asenov, Statistical vari- (2002), pp. 7–11.
ability and reliability in nanoscale FinFETs. 2011 IEEE Interna- 60. N. Pinckney, L. Shifren, B. Cline, S. Sinha, S. Jeloka, R. G.
tional Electron Devices Meeting (IEDM), IEEE 5 (2011). Dreslinski, T. Mudge, D. Sylvester, and D. Blaauw, Near-threshold
52. S. Taghipour and R. N. Asli, Aging comparative analysis of high- computing in FinFET technologies: Opportunities for improved volt-
performance FinFET and CMOS flip-flops. Microelectronics Relia- age scalability, Proceedings of the 53rd Annual Design Automation
bility 69, 52 (2017). Conference, ACM (2016), p. 76.

Xinfei Guo
Xinfei Guo received the B.S. degree in Microelectronics from Xidian University, Xi’an, China, in 2010 and the M.S. degree in Electrical
and Computer Engineering from the University of Florida, Gainesville, FL, in 2012. Currently, he is a Ph.D. candidate in Computer
Engineering at the University of Virginia, Charlottesville, VA. He has a broad interest in digital circuit and microarchitectures. His
current research focus on Reliability (Wearout and Accelerated Recovery Techniques), Cross-layer power and reliability co-design
methodology, Low-power and Energy-efficient design. He is a student member of the IEEE and ACM and a recipient of the 2017 IEEE
Circuits and Systems (CAS) Pre-Doctoral Scholarship. He also received the Best Paper Award at SELSE 2017 and A. Richard Newton
Young Student Fellowship in 2013.

Vaibhav Verma
Vaibhav Verma received his B.E. in Electrical and Electronics Engineering from Birla Institute of Technology and Science-Pilani,
Hyderabad, India in 2013. He worked as an R&D Engineer at Synopsys, India from 2013 to 2016. He is currently working towards
his Ph.D. in Electrical Engineering at the University of Virginia. His research interest lies in energy-efficient circuit design and
high-performance, low-power memory design.

Patricia Gonzalez-Guerrero
Patricia Gonzalez-Guerrero received her M.S. degree in Electrical Engineering from the University of Virginia in 2014. She worked as
an ASIC design and verification engineer in the ESSN R&D in Hewlett Packard, Costa Rica. She received, her B.S. degree in electronics
engineering from Pontifical Xavierian University, Bogota, Colombia. She is currently working towards her Ph.D. at the University of
Virginia. Her main research interests are system level integration, applications influence in system level design, subthreshold digital
design for ultralow power-low frequency systems and mixed signal design.

Sergiu Mosanu
Sergiu Mosanu received the B.Sc. degree in Electrical and Computer Engineering from Jacobs University, Bremen, Germany, in
2011 and the M.Sc. degree in Information and Media Technologies from Hamburg University of Technology, Hamburg, Germany, in
2014. He is currently a Ph.D. candidate in Electrical Engineering at the University of Virginia, in Charlottesville, VA as part of the
High-Performance Low-Power Laboratory. He is passionate about reconfigurable hardware, heterogeneous computing and emerging
computer architectures. His current research activities focus on security for small low-power IoT devices, processing in memory
techniques as well as testing and verification of RISC-V systems. During his studies he also did several research oriented internships
at the German Aerospace Center, German Center for Artificial Intelligence, Micron Technology, and collaborated with Vector Foiltec
and Airbus.

J. Low Power Electron. 13, 1–18, 2017 17

Back to the Future: Digital Circuit Design in the FinFET Era Guo et al.

Mircea R. Stan
Mircea R. Stan received the Ph.D. (1996) and the M.S. (1994) degrees in Electrical and Computer Engineering from the University
of Massachusetts at Amherst and the Diploma (1984) in Electronics and Communications from Politehnica University in Bucharest,
Romania. Since 1996 he has been with the Charles L. Brown Department of Electrical and Computer Engineering at the University of
Virginia, where he is now a professor. Professor Stan is teaching and doing research in the areas of high-performance low-power VLSI,
temperature-aware circuits and architecture, embedded systems, spintronics, and nanoelectronics. He leads the High-Performance
Low-Power (HPLP) lab and is a co-director of the Center for Automata Processing (CAP). He has more than eight years of industrial
experience, has been a visiting faculty at UC Berkeley in 2004–2005, at IBM in 2000, and at Intel in 2002 and 1999. He has received
the NSF CAREER award in 1997 and was a co-author on best paper awards at SELSE 2017, ISQED 2008, GLSVLSI 2006, ISCA
2003 and SHAMAN 2002. He was the chair of the VLSI Systems and Applications Technical Committee (VSA-TC) of IEEE CAS in
2005–2007, general chair for ISLPED 2006 and for GLSVLSI 2004, technical program chair for NanoNets 2007 and ISLPED 2005,
and on technical committees for numerous conferences. He is a Senior Editor for the IEEE Transactions on Nanotechnology since
2014, and was an AE for the IEEE Transactions on Nanotechnology in 2012-2014, IEEE Transactions on Circuits and Systems I in
2004–2008 and for the IEEE Transactions on VLSI Systems in 2001–2003. He was Guest Editor for the IEEE Computer special issue
on Power-Aware Computing in December 2003 and a Distinguished Lecturer for the IEEE Circuits and Systems (CAS) Society in
2012–2013 and 2004–2005, and for the Solid-State Circuits Society (SSCS) in 2007–2008. Professor Stan is a Fellow of the IEEE, a
member of ACM, and of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi.

18 J. Low Power Electron. 13, 1–18, 2017